Type Definition stm32wl::stm32wle5::tim1::cr2::MMS2_W

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pub type MMS2_W<'a, const O: u8> = FieldWriterSafe<'a, u32, CR2_SPEC, u8, MMS2_A, 4, O>;

Expand description

Field MMS2 writer - Master mode selection 2

Implementations

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impl<'a, const O: u8> MMS2_W<'a, O>

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pub fn reset(self) -> &'a mut W

Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset

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pub fn enable(self) -> &'a mut W

Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register)

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pub fn update(self) -> &'a mut W

Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer

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pub fn compare_pulse(self) -> &'a mut W

Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2)

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