#[repr(u8)]
pub enum PLLM_A {
Div1,
Div2,
Div3,
Div4,
Div5,
Div6,
Div7,
Div8,
}
Expand description
Division factor for the main PLL input clock
Value on reset: 0
Variants
Div1
0: VCO input = PLL input / PLLM
Div2
1: VCO input = PLL input / PLLM
Div3
2: VCO input = PLL input / PLLM
Div4
3: VCO input = PLL input / PLLM
Div5
4: VCO input = PLL input / PLLM
Div6
5: VCO input = PLL input / PLLM
Div7
6: VCO input = PLL input / PLLM
Div8
7: VCO input = PLL input / PLLM
Trait Implementations
impl Copy for PLLM_A
impl StructuralPartialEq for PLLM_A
Auto Trait Implementations
impl RefUnwindSafe for PLLM_A
impl Send for PLLM_A
impl Sync for PLLM_A
impl Unpin for PLLM_A
impl UnwindSafe for PLLM_A
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more