Module stm32wb_stm32hal::stm32wb55::usb[][src]

Expand description

Universal serial bus full-speed device interface

Modules

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Battery charging detector(

Buffer table address

control register

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

device address

endpoint 0 register

endpoint 1 register

endpoint 2 register

endpoint 3 register

endpoint 4 register

endpoint 5 register

endpoint 6 register

endpoint 7 register

frame number register

interrupt status register

control and status register

Structs

Register block

Type Definitions

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Reception buffer address 0

Battery charging detector(

Buffer table address

control register

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

Reception byte count 0

Transmission byte count 0

device address

endpoint 0 register

endpoint 1 register

endpoint 2 register

endpoint 3 register

endpoint 4 register

endpoint 5 register

endpoint 6 register

endpoint 7 register

frame number register

interrupt status register

control and status register