stm32wb_pac/tim2/
ccmr1_output.rs

1#[doc = "Reader of register CCMR1_Output"]
2pub type R = crate::R<u32, super::CCMR1_OUTPUT>;
3#[doc = "Writer for register CCMR1_Output"]
4pub type W = crate::W<u32, super::CCMR1_OUTPUT>;
5#[doc = "Register CCMR1_Output `reset()`'s with value 0"]
6impl crate::ResetValue for super::CCMR1_OUTPUT {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `OC2M_3`"]
14pub type OC2M_3_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `OC2M_3`"]
16pub struct OC2M_3_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> OC2M_3_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
34        self.w
35    }
36}
37#[doc = "Reader of field `OC1M_3`"]
38pub type OC1M_3_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `OC1M_3`"]
40pub struct OC1M_3_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> OC1M_3_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
58        self.w
59    }
60}
61#[doc = "Reader of field `OC2CE`"]
62pub type OC2CE_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `OC2CE`"]
64pub struct OC2CE_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> OC2CE_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
82        self.w
83    }
84}
85#[doc = "Reader of field `OC2M`"]
86pub type OC2M_R = crate::R<u8, u8>;
87#[doc = "Write proxy for field `OC2M`"]
88pub struct OC2M_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> OC2M_W<'a> {
92    #[doc = r"Writes raw bits to the field"]
93    #[inline(always)]
94    pub unsafe fn bits(self, value: u8) -> &'a mut W {
95        self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
96        self.w
97    }
98}
99#[doc = "Reader of field `OC2PE`"]
100pub type OC2PE_R = crate::R<bool, bool>;
101#[doc = "Write proxy for field `OC2PE`"]
102pub struct OC2PE_W<'a> {
103    w: &'a mut W,
104}
105impl<'a> OC2PE_W<'a> {
106    #[doc = r"Sets the field bit"]
107    #[inline(always)]
108    pub fn set_bit(self) -> &'a mut W {
109        self.bit(true)
110    }
111    #[doc = r"Clears the field bit"]
112    #[inline(always)]
113    pub fn clear_bit(self) -> &'a mut W {
114        self.bit(false)
115    }
116    #[doc = r"Writes raw bits to the field"]
117    #[inline(always)]
118    pub fn bit(self, value: bool) -> &'a mut W {
119        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
120        self.w
121    }
122}
123#[doc = "Reader of field `OC2FE`"]
124pub type OC2FE_R = crate::R<bool, bool>;
125#[doc = "Write proxy for field `OC2FE`"]
126pub struct OC2FE_W<'a> {
127    w: &'a mut W,
128}
129impl<'a> OC2FE_W<'a> {
130    #[doc = r"Sets the field bit"]
131    #[inline(always)]
132    pub fn set_bit(self) -> &'a mut W {
133        self.bit(true)
134    }
135    #[doc = r"Clears the field bit"]
136    #[inline(always)]
137    pub fn clear_bit(self) -> &'a mut W {
138        self.bit(false)
139    }
140    #[doc = r"Writes raw bits to the field"]
141    #[inline(always)]
142    pub fn bit(self, value: bool) -> &'a mut W {
143        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
144        self.w
145    }
146}
147#[doc = "Reader of field `CC2S`"]
148pub type CC2S_R = crate::R<u8, u8>;
149#[doc = "Write proxy for field `CC2S`"]
150pub struct CC2S_W<'a> {
151    w: &'a mut W,
152}
153impl<'a> CC2S_W<'a> {
154    #[doc = r"Writes raw bits to the field"]
155    #[inline(always)]
156    pub unsafe fn bits(self, value: u8) -> &'a mut W {
157        self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
158        self.w
159    }
160}
161#[doc = "Reader of field `OC1CE`"]
162pub type OC1CE_R = crate::R<bool, bool>;
163#[doc = "Write proxy for field `OC1CE`"]
164pub struct OC1CE_W<'a> {
165    w: &'a mut W,
166}
167impl<'a> OC1CE_W<'a> {
168    #[doc = r"Sets the field bit"]
169    #[inline(always)]
170    pub fn set_bit(self) -> &'a mut W {
171        self.bit(true)
172    }
173    #[doc = r"Clears the field bit"]
174    #[inline(always)]
175    pub fn clear_bit(self) -> &'a mut W {
176        self.bit(false)
177    }
178    #[doc = r"Writes raw bits to the field"]
179    #[inline(always)]
180    pub fn bit(self, value: bool) -> &'a mut W {
181        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
182        self.w
183    }
184}
185#[doc = "Reader of field `OC1M`"]
186pub type OC1M_R = crate::R<u8, u8>;
187#[doc = "Write proxy for field `OC1M`"]
188pub struct OC1M_W<'a> {
189    w: &'a mut W,
190}
191impl<'a> OC1M_W<'a> {
192    #[doc = r"Writes raw bits to the field"]
193    #[inline(always)]
194    pub unsafe fn bits(self, value: u8) -> &'a mut W {
195        self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
196        self.w
197    }
198}
199#[doc = "Reader of field `OC1PE`"]
200pub type OC1PE_R = crate::R<bool, bool>;
201#[doc = "Write proxy for field `OC1PE`"]
202pub struct OC1PE_W<'a> {
203    w: &'a mut W,
204}
205impl<'a> OC1PE_W<'a> {
206    #[doc = r"Sets the field bit"]
207    #[inline(always)]
208    pub fn set_bit(self) -> &'a mut W {
209        self.bit(true)
210    }
211    #[doc = r"Clears the field bit"]
212    #[inline(always)]
213    pub fn clear_bit(self) -> &'a mut W {
214        self.bit(false)
215    }
216    #[doc = r"Writes raw bits to the field"]
217    #[inline(always)]
218    pub fn bit(self, value: bool) -> &'a mut W {
219        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
220        self.w
221    }
222}
223#[doc = "Reader of field `OC1FE`"]
224pub type OC1FE_R = crate::R<bool, bool>;
225#[doc = "Write proxy for field `OC1FE`"]
226pub struct OC1FE_W<'a> {
227    w: &'a mut W,
228}
229impl<'a> OC1FE_W<'a> {
230    #[doc = r"Sets the field bit"]
231    #[inline(always)]
232    pub fn set_bit(self) -> &'a mut W {
233        self.bit(true)
234    }
235    #[doc = r"Clears the field bit"]
236    #[inline(always)]
237    pub fn clear_bit(self) -> &'a mut W {
238        self.bit(false)
239    }
240    #[doc = r"Writes raw bits to the field"]
241    #[inline(always)]
242    pub fn bit(self, value: bool) -> &'a mut W {
243        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
244        self.w
245    }
246}
247#[doc = "Reader of field `CC1S`"]
248pub type CC1S_R = crate::R<u8, u8>;
249#[doc = "Write proxy for field `CC1S`"]
250pub struct CC1S_W<'a> {
251    w: &'a mut W,
252}
253impl<'a> CC1S_W<'a> {
254    #[doc = r"Writes raw bits to the field"]
255    #[inline(always)]
256    pub unsafe fn bits(self, value: u8) -> &'a mut W {
257        self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
258        self.w
259    }
260}
261impl R {
262    #[doc = "Bit 24 - Output Compare 2 mode - bit 3"]
263    #[inline(always)]
264    pub fn oc2m_3(&self) -> OC2M_3_R {
265        OC2M_3_R::new(((self.bits >> 24) & 0x01) != 0)
266    }
267    #[doc = "Bit 16 - Output Compare 1 mode - bit 3"]
268    #[inline(always)]
269    pub fn oc1m_3(&self) -> OC1M_3_R {
270        OC1M_3_R::new(((self.bits >> 16) & 0x01) != 0)
271    }
272    #[doc = "Bit 15 - Output compare 2 clear enable"]
273    #[inline(always)]
274    pub fn oc2ce(&self) -> OC2CE_R {
275        OC2CE_R::new(((self.bits >> 15) & 0x01) != 0)
276    }
277    #[doc = "Bits 12:14 - Output compare 2 mode"]
278    #[inline(always)]
279    pub fn oc2m(&self) -> OC2M_R {
280        OC2M_R::new(((self.bits >> 12) & 0x07) as u8)
281    }
282    #[doc = "Bit 11 - Output compare 2 preload enable"]
283    #[inline(always)]
284    pub fn oc2pe(&self) -> OC2PE_R {
285        OC2PE_R::new(((self.bits >> 11) & 0x01) != 0)
286    }
287    #[doc = "Bit 10 - Output compare 2 fast enable"]
288    #[inline(always)]
289    pub fn oc2fe(&self) -> OC2FE_R {
290        OC2FE_R::new(((self.bits >> 10) & 0x01) != 0)
291    }
292    #[doc = "Bits 8:9 - Capture/Compare 2 selection"]
293    #[inline(always)]
294    pub fn cc2s(&self) -> CC2S_R {
295        CC2S_R::new(((self.bits >> 8) & 0x03) as u8)
296    }
297    #[doc = "Bit 7 - Output compare 1 clear enable"]
298    #[inline(always)]
299    pub fn oc1ce(&self) -> OC1CE_R {
300        OC1CE_R::new(((self.bits >> 7) & 0x01) != 0)
301    }
302    #[doc = "Bits 4:6 - Output compare 1 mode"]
303    #[inline(always)]
304    pub fn oc1m(&self) -> OC1M_R {
305        OC1M_R::new(((self.bits >> 4) & 0x07) as u8)
306    }
307    #[doc = "Bit 3 - Output compare 1 preload enable"]
308    #[inline(always)]
309    pub fn oc1pe(&self) -> OC1PE_R {
310        OC1PE_R::new(((self.bits >> 3) & 0x01) != 0)
311    }
312    #[doc = "Bit 2 - Output compare 1 fast enable"]
313    #[inline(always)]
314    pub fn oc1fe(&self) -> OC1FE_R {
315        OC1FE_R::new(((self.bits >> 2) & 0x01) != 0)
316    }
317    #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
318    #[inline(always)]
319    pub fn cc1s(&self) -> CC1S_R {
320        CC1S_R::new((self.bits & 0x03) as u8)
321    }
322}
323impl W {
324    #[doc = "Bit 24 - Output Compare 2 mode - bit 3"]
325    #[inline(always)]
326    pub fn oc2m_3(&mut self) -> OC2M_3_W {
327        OC2M_3_W { w: self }
328    }
329    #[doc = "Bit 16 - Output Compare 1 mode - bit 3"]
330    #[inline(always)]
331    pub fn oc1m_3(&mut self) -> OC1M_3_W {
332        OC1M_3_W { w: self }
333    }
334    #[doc = "Bit 15 - Output compare 2 clear enable"]
335    #[inline(always)]
336    pub fn oc2ce(&mut self) -> OC2CE_W {
337        OC2CE_W { w: self }
338    }
339    #[doc = "Bits 12:14 - Output compare 2 mode"]
340    #[inline(always)]
341    pub fn oc2m(&mut self) -> OC2M_W {
342        OC2M_W { w: self }
343    }
344    #[doc = "Bit 11 - Output compare 2 preload enable"]
345    #[inline(always)]
346    pub fn oc2pe(&mut self) -> OC2PE_W {
347        OC2PE_W { w: self }
348    }
349    #[doc = "Bit 10 - Output compare 2 fast enable"]
350    #[inline(always)]
351    pub fn oc2fe(&mut self) -> OC2FE_W {
352        OC2FE_W { w: self }
353    }
354    #[doc = "Bits 8:9 - Capture/Compare 2 selection"]
355    #[inline(always)]
356    pub fn cc2s(&mut self) -> CC2S_W {
357        CC2S_W { w: self }
358    }
359    #[doc = "Bit 7 - Output compare 1 clear enable"]
360    #[inline(always)]
361    pub fn oc1ce(&mut self) -> OC1CE_W {
362        OC1CE_W { w: self }
363    }
364    #[doc = "Bits 4:6 - Output compare 1 mode"]
365    #[inline(always)]
366    pub fn oc1m(&mut self) -> OC1M_W {
367        OC1M_W { w: self }
368    }
369    #[doc = "Bit 3 - Output compare 1 preload enable"]
370    #[inline(always)]
371    pub fn oc1pe(&mut self) -> OC1PE_W {
372        OC1PE_W { w: self }
373    }
374    #[doc = "Bit 2 - Output compare 1 fast enable"]
375    #[inline(always)]
376    pub fn oc1fe(&mut self) -> OC1FE_W {
377        OC1FE_W { w: self }
378    }
379    #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
380    #[inline(always)]
381    pub fn cc1s(&mut self) -> CC1S_W {
382        CC1S_W { w: self }
383    }
384}
stm32wb_pac/tim2/ccmr1_output.rs

stm32wb_pac/tim2/
ccmr1_output.rs
