stm32wb_pac/tim1/
ccmr1_output.rs

1#[doc = "Reader of register CCMR1_Output"]
2pub type R = crate::R<u32, super::CCMR1_OUTPUT>;
3#[doc = "Writer for register CCMR1_Output"]
4pub type W = crate::W<u32, super::CCMR1_OUTPUT>;
5#[doc = "Register CCMR1_Output `reset()`'s with value 0"]
6impl crate::ResetValue for super::CCMR1_OUTPUT {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `CC1S`"]
14pub type CC1S_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `CC1S`"]
16pub struct CC1S_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> CC1S_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
24        self.w
25    }
26}
27#[doc = "Reader of field `OC1FE`"]
28pub type OC1FE_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `OC1FE`"]
30pub struct OC1FE_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> OC1FE_W<'a> {
34    #[doc = r"Sets the field bit"]
35    #[inline(always)]
36    pub fn set_bit(self) -> &'a mut W {
37        self.bit(true)
38    }
39    #[doc = r"Clears the field bit"]
40    #[inline(always)]
41    pub fn clear_bit(self) -> &'a mut W {
42        self.bit(false)
43    }
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub fn bit(self, value: bool) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
48        self.w
49    }
50}
51#[doc = "Reader of field `OC1PE`"]
52pub type OC1PE_R = crate::R<bool, bool>;
53#[doc = "Write proxy for field `OC1PE`"]
54pub struct OC1PE_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> OC1PE_W<'a> {
58    #[doc = r"Sets the field bit"]
59    #[inline(always)]
60    pub fn set_bit(self) -> &'a mut W {
61        self.bit(true)
62    }
63    #[doc = r"Clears the field bit"]
64    #[inline(always)]
65    pub fn clear_bit(self) -> &'a mut W {
66        self.bit(false)
67    }
68    #[doc = r"Writes raw bits to the field"]
69    #[inline(always)]
70    pub fn bit(self, value: bool) -> &'a mut W {
71        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
72        self.w
73    }
74}
75#[doc = "Reader of field `OC1M`"]
76pub type OC1M_R = crate::R<u8, u8>;
77#[doc = "Write proxy for field `OC1M`"]
78pub struct OC1M_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> OC1M_W<'a> {
82    #[doc = r"Writes raw bits to the field"]
83    #[inline(always)]
84    pub unsafe fn bits(self, value: u8) -> &'a mut W {
85        self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
86        self.w
87    }
88}
89#[doc = "Reader of field `OC1CE`"]
90pub type OC1CE_R = crate::R<bool, bool>;
91#[doc = "Write proxy for field `OC1CE`"]
92pub struct OC1CE_W<'a> {
93    w: &'a mut W,
94}
95impl<'a> OC1CE_W<'a> {
96    #[doc = r"Sets the field bit"]
97    #[inline(always)]
98    pub fn set_bit(self) -> &'a mut W {
99        self.bit(true)
100    }
101    #[doc = r"Clears the field bit"]
102    #[inline(always)]
103    pub fn clear_bit(self) -> &'a mut W {
104        self.bit(false)
105    }
106    #[doc = r"Writes raw bits to the field"]
107    #[inline(always)]
108    pub fn bit(self, value: bool) -> &'a mut W {
109        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
110        self.w
111    }
112}
113#[doc = "Reader of field `CC2S`"]
114pub type CC2S_R = crate::R<u8, u8>;
115#[doc = "Write proxy for field `CC2S`"]
116pub struct CC2S_W<'a> {
117    w: &'a mut W,
118}
119impl<'a> CC2S_W<'a> {
120    #[doc = r"Writes raw bits to the field"]
121    #[inline(always)]
122    pub unsafe fn bits(self, value: u8) -> &'a mut W {
123        self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
124        self.w
125    }
126}
127#[doc = "Reader of field `OC2FE`"]
128pub type OC2FE_R = crate::R<bool, bool>;
129#[doc = "Write proxy for field `OC2FE`"]
130pub struct OC2FE_W<'a> {
131    w: &'a mut W,
132}
133impl<'a> OC2FE_W<'a> {
134    #[doc = r"Sets the field bit"]
135    #[inline(always)]
136    pub fn set_bit(self) -> &'a mut W {
137        self.bit(true)
138    }
139    #[doc = r"Clears the field bit"]
140    #[inline(always)]
141    pub fn clear_bit(self) -> &'a mut W {
142        self.bit(false)
143    }
144    #[doc = r"Writes raw bits to the field"]
145    #[inline(always)]
146    pub fn bit(self, value: bool) -> &'a mut W {
147        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
148        self.w
149    }
150}
151#[doc = "Reader of field `OC2PE`"]
152pub type OC2PE_R = crate::R<bool, bool>;
153#[doc = "Write proxy for field `OC2PE`"]
154pub struct OC2PE_W<'a> {
155    w: &'a mut W,
156}
157impl<'a> OC2PE_W<'a> {
158    #[doc = r"Sets the field bit"]
159    #[inline(always)]
160    pub fn set_bit(self) -> &'a mut W {
161        self.bit(true)
162    }
163    #[doc = r"Clears the field bit"]
164    #[inline(always)]
165    pub fn clear_bit(self) -> &'a mut W {
166        self.bit(false)
167    }
168    #[doc = r"Writes raw bits to the field"]
169    #[inline(always)]
170    pub fn bit(self, value: bool) -> &'a mut W {
171        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
172        self.w
173    }
174}
175#[doc = "Reader of field `OC2M`"]
176pub type OC2M_R = crate::R<u8, u8>;
177#[doc = "Write proxy for field `OC2M`"]
178pub struct OC2M_W<'a> {
179    w: &'a mut W,
180}
181impl<'a> OC2M_W<'a> {
182    #[doc = r"Writes raw bits to the field"]
183    #[inline(always)]
184    pub unsafe fn bits(self, value: u8) -> &'a mut W {
185        self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
186        self.w
187    }
188}
189#[doc = "Reader of field `OC2CE`"]
190pub type OC2CE_R = crate::R<bool, bool>;
191#[doc = "Write proxy for field `OC2CE`"]
192pub struct OC2CE_W<'a> {
193    w: &'a mut W,
194}
195impl<'a> OC2CE_W<'a> {
196    #[doc = r"Sets the field bit"]
197    #[inline(always)]
198    pub fn set_bit(self) -> &'a mut W {
199        self.bit(true)
200    }
201    #[doc = r"Clears the field bit"]
202    #[inline(always)]
203    pub fn clear_bit(self) -> &'a mut W {
204        self.bit(false)
205    }
206    #[doc = r"Writes raw bits to the field"]
207    #[inline(always)]
208    pub fn bit(self, value: bool) -> &'a mut W {
209        self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
210        self.w
211    }
212}
213#[doc = "Reader of field `OC1M_3`"]
214pub type OC1M_3_R = crate::R<bool, bool>;
215#[doc = "Write proxy for field `OC1M_3`"]
216pub struct OC1M_3_W<'a> {
217    w: &'a mut W,
218}
219impl<'a> OC1M_3_W<'a> {
220    #[doc = r"Sets the field bit"]
221    #[inline(always)]
222    pub fn set_bit(self) -> &'a mut W {
223        self.bit(true)
224    }
225    #[doc = r"Clears the field bit"]
226    #[inline(always)]
227    pub fn clear_bit(self) -> &'a mut W {
228        self.bit(false)
229    }
230    #[doc = r"Writes raw bits to the field"]
231    #[inline(always)]
232    pub fn bit(self, value: bool) -> &'a mut W {
233        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
234        self.w
235    }
236}
237#[doc = "Reader of field `OC2M_3`"]
238pub type OC2M_3_R = crate::R<bool, bool>;
239#[doc = "Write proxy for field `OC2M_3`"]
240pub struct OC2M_3_W<'a> {
241    w: &'a mut W,
242}
243impl<'a> OC2M_3_W<'a> {
244    #[doc = r"Sets the field bit"]
245    #[inline(always)]
246    pub fn set_bit(self) -> &'a mut W {
247        self.bit(true)
248    }
249    #[doc = r"Clears the field bit"]
250    #[inline(always)]
251    pub fn clear_bit(self) -> &'a mut W {
252        self.bit(false)
253    }
254    #[doc = r"Writes raw bits to the field"]
255    #[inline(always)]
256    pub fn bit(self, value: bool) -> &'a mut W {
257        self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
258        self.w
259    }
260}
261impl R {
262    #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
263    #[inline(always)]
264    pub fn cc1s(&self) -> CC1S_R {
265        CC1S_R::new((self.bits & 0x03) as u8)
266    }
267    #[doc = "Bit 2 - Output Compare 1 fast enable"]
268    #[inline(always)]
269    pub fn oc1fe(&self) -> OC1FE_R {
270        OC1FE_R::new(((self.bits >> 2) & 0x01) != 0)
271    }
272    #[doc = "Bit 3 - Output Compare 1 preload enable"]
273    #[inline(always)]
274    pub fn oc1pe(&self) -> OC1PE_R {
275        OC1PE_R::new(((self.bits >> 3) & 0x01) != 0)
276    }
277    #[doc = "Bits 4:6 - Output Compare 1 mode"]
278    #[inline(always)]
279    pub fn oc1m(&self) -> OC1M_R {
280        OC1M_R::new(((self.bits >> 4) & 0x07) as u8)
281    }
282    #[doc = "Bit 7 - Output Compare 1 clear enable"]
283    #[inline(always)]
284    pub fn oc1ce(&self) -> OC1CE_R {
285        OC1CE_R::new(((self.bits >> 7) & 0x01) != 0)
286    }
287    #[doc = "Bits 8:9 - Capture/Compare 2 selection"]
288    #[inline(always)]
289    pub fn cc2s(&self) -> CC2S_R {
290        CC2S_R::new(((self.bits >> 8) & 0x03) as u8)
291    }
292    #[doc = "Bit 10 - Output Compare 2 fast enable"]
293    #[inline(always)]
294    pub fn oc2fe(&self) -> OC2FE_R {
295        OC2FE_R::new(((self.bits >> 10) & 0x01) != 0)
296    }
297    #[doc = "Bit 11 - Output Compare 2 preload enable"]
298    #[inline(always)]
299    pub fn oc2pe(&self) -> OC2PE_R {
300        OC2PE_R::new(((self.bits >> 11) & 0x01) != 0)
301    }
302    #[doc = "Bits 12:14 - Output Compare 2 mode"]
303    #[inline(always)]
304    pub fn oc2m(&self) -> OC2M_R {
305        OC2M_R::new(((self.bits >> 12) & 0x07) as u8)
306    }
307    #[doc = "Bit 15 - Output Compare 2 clear enable"]
308    #[inline(always)]
309    pub fn oc2ce(&self) -> OC2CE_R {
310        OC2CE_R::new(((self.bits >> 15) & 0x01) != 0)
311    }
312    #[doc = "Bit 16 - Output Compare 1 mode - bit 3"]
313    #[inline(always)]
314    pub fn oc1m_3(&self) -> OC1M_3_R {
315        OC1M_3_R::new(((self.bits >> 16) & 0x01) != 0)
316    }
317    #[doc = "Bit 24 - Output Compare 2 mode - bit 3"]
318    #[inline(always)]
319    pub fn oc2m_3(&self) -> OC2M_3_R {
320        OC2M_3_R::new(((self.bits >> 24) & 0x01) != 0)
321    }
322}
323impl W {
324    #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
325    #[inline(always)]
326    pub fn cc1s(&mut self) -> CC1S_W {
327        CC1S_W { w: self }
328    }
329    #[doc = "Bit 2 - Output Compare 1 fast enable"]
330    #[inline(always)]
331    pub fn oc1fe(&mut self) -> OC1FE_W {
332        OC1FE_W { w: self }
333    }
334    #[doc = "Bit 3 - Output Compare 1 preload enable"]
335    #[inline(always)]
336    pub fn oc1pe(&mut self) -> OC1PE_W {
337        OC1PE_W { w: self }
338    }
339    #[doc = "Bits 4:6 - Output Compare 1 mode"]
340    #[inline(always)]
341    pub fn oc1m(&mut self) -> OC1M_W {
342        OC1M_W { w: self }
343    }
344    #[doc = "Bit 7 - Output Compare 1 clear enable"]
345    #[inline(always)]
346    pub fn oc1ce(&mut self) -> OC1CE_W {
347        OC1CE_W { w: self }
348    }
349    #[doc = "Bits 8:9 - Capture/Compare 2 selection"]
350    #[inline(always)]
351    pub fn cc2s(&mut self) -> CC2S_W {
352        CC2S_W { w: self }
353    }
354    #[doc = "Bit 10 - Output Compare 2 fast enable"]
355    #[inline(always)]
356    pub fn oc2fe(&mut self) -> OC2FE_W {
357        OC2FE_W { w: self }
358    }
359    #[doc = "Bit 11 - Output Compare 2 preload enable"]
360    #[inline(always)]
361    pub fn oc2pe(&mut self) -> OC2PE_W {
362        OC2PE_W { w: self }
363    }
364    #[doc = "Bits 12:14 - Output Compare 2 mode"]
365    #[inline(always)]
366    pub fn oc2m(&mut self) -> OC2M_W {
367        OC2M_W { w: self }
368    }
369    #[doc = "Bit 15 - Output Compare 2 clear enable"]
370    #[inline(always)]
371    pub fn oc2ce(&mut self) -> OC2CE_W {
372        OC2CE_W { w: self }
373    }
374    #[doc = "Bit 16 - Output Compare 1 mode - bit 3"]
375    #[inline(always)]
376    pub fn oc1m_3(&mut self) -> OC1M_3_W {
377        OC1M_3_W { w: self }
378    }
379    #[doc = "Bit 24 - Output Compare 2 mode - bit 3"]
380    #[inline(always)]
381    pub fn oc2m_3(&mut self) -> OC2M_3_W {
382        OC2M_3_W { w: self }
383    }
384}
stm32wb_pac/tim1/ccmr1_output.rs

stm32wb_pac/tim1/
ccmr1_output.rs
