stm32wb_pac/tim17/
ccmr1_output.rs

1#[doc = "Reader of register CCMR1_Output"]
2pub type R = crate::R<u32, super::CCMR1_OUTPUT>;
3#[doc = "Writer for register CCMR1_Output"]
4pub type W = crate::W<u32, super::CCMR1_OUTPUT>;
5#[doc = "Register CCMR1_Output `reset()`'s with value 0"]
6impl crate::ResetValue for super::CCMR1_OUTPUT {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `OC1M_2`"]
14pub type OC1M_2_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `OC1M_2`"]
16pub struct OC1M_2_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> OC1M_2_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
34        self.w
35    }
36}
37#[doc = "Reader of field `OC1M`"]
38pub type OC1M_R = crate::R<u8, u8>;
39#[doc = "Write proxy for field `OC1M`"]
40pub struct OC1M_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> OC1M_W<'a> {
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub unsafe fn bits(self, value: u8) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
48        self.w
49    }
50}
51#[doc = "Reader of field `OC1PE`"]
52pub type OC1PE_R = crate::R<bool, bool>;
53#[doc = "Write proxy for field `OC1PE`"]
54pub struct OC1PE_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> OC1PE_W<'a> {
58    #[doc = r"Sets the field bit"]
59    #[inline(always)]
60    pub fn set_bit(self) -> &'a mut W {
61        self.bit(true)
62    }
63    #[doc = r"Clears the field bit"]
64    #[inline(always)]
65    pub fn clear_bit(self) -> &'a mut W {
66        self.bit(false)
67    }
68    #[doc = r"Writes raw bits to the field"]
69    #[inline(always)]
70    pub fn bit(self, value: bool) -> &'a mut W {
71        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
72        self.w
73    }
74}
75#[doc = "Reader of field `OC1FE`"]
76pub type OC1FE_R = crate::R<bool, bool>;
77#[doc = "Write proxy for field `OC1FE`"]
78pub struct OC1FE_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> OC1FE_W<'a> {
82    #[doc = r"Sets the field bit"]
83    #[inline(always)]
84    pub fn set_bit(self) -> &'a mut W {
85        self.bit(true)
86    }
87    #[doc = r"Clears the field bit"]
88    #[inline(always)]
89    pub fn clear_bit(self) -> &'a mut W {
90        self.bit(false)
91    }
92    #[doc = r"Writes raw bits to the field"]
93    #[inline(always)]
94    pub fn bit(self, value: bool) -> &'a mut W {
95        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
96        self.w
97    }
98}
99#[doc = "Reader of field `CC1S`"]
100pub type CC1S_R = crate::R<u8, u8>;
101#[doc = "Write proxy for field `CC1S`"]
102pub struct CC1S_W<'a> {
103    w: &'a mut W,
104}
105impl<'a> CC1S_W<'a> {
106    #[doc = r"Writes raw bits to the field"]
107    #[inline(always)]
108    pub unsafe fn bits(self, value: u8) -> &'a mut W {
109        self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
110        self.w
111    }
112}
113impl R {
114    #[doc = "Bit 16 - Output Compare 1 mode"]
115    #[inline(always)]
116    pub fn oc1m_2(&self) -> OC1M_2_R {
117        OC1M_2_R::new(((self.bits >> 16) & 0x01) != 0)
118    }
119    #[doc = "Bits 4:6 - Output Compare 1 mode"]
120    #[inline(always)]
121    pub fn oc1m(&self) -> OC1M_R {
122        OC1M_R::new(((self.bits >> 4) & 0x07) as u8)
123    }
124    #[doc = "Bit 3 - Output Compare 1 preload enable"]
125    #[inline(always)]
126    pub fn oc1pe(&self) -> OC1PE_R {
127        OC1PE_R::new(((self.bits >> 3) & 0x01) != 0)
128    }
129    #[doc = "Bit 2 - Output Compare 1 fast enable"]
130    #[inline(always)]
131    pub fn oc1fe(&self) -> OC1FE_R {
132        OC1FE_R::new(((self.bits >> 2) & 0x01) != 0)
133    }
134    #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
135    #[inline(always)]
136    pub fn cc1s(&self) -> CC1S_R {
137        CC1S_R::new((self.bits & 0x03) as u8)
138    }
139}
140impl W {
141    #[doc = "Bit 16 - Output Compare 1 mode"]
142    #[inline(always)]
143    pub fn oc1m_2(&mut self) -> OC1M_2_W {
144        OC1M_2_W { w: self }
145    }
146    #[doc = "Bits 4:6 - Output Compare 1 mode"]
147    #[inline(always)]
148    pub fn oc1m(&mut self) -> OC1M_W {
149        OC1M_W { w: self }
150    }
151    #[doc = "Bit 3 - Output Compare 1 preload enable"]
152    #[inline(always)]
153    pub fn oc1pe(&mut self) -> OC1PE_W {
154        OC1PE_W { w: self }
155    }
156    #[doc = "Bit 2 - Output Compare 1 fast enable"]
157    #[inline(always)]
158    pub fn oc1fe(&mut self) -> OC1FE_W {
159        OC1FE_W { w: self }
160    }
161    #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
162    #[inline(always)]
163    pub fn cc1s(&mut self) -> CC1S_W {
164        CC1S_W { w: self }
165    }
166}
stm32wb_pac/tim17/ccmr1_output.rs

stm32wb_pac/tim17/
ccmr1_output.rs
