stm32wb_pac/tim1/
or.rs

1#[doc = "Reader of register OR"]
2pub type R = crate::R<u32, super::OR>;
3#[doc = "Writer for register OR"]
4pub type W = crate::W<u32, super::OR>;
5#[doc = "Register OR `reset()`'s with value 0"]
6impl crate::ResetValue for super::OR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `TIM1_ETR_ADC1_RMP`"]
14pub type TIM1_ETR_ADC1_RMP_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `TIM1_ETR_ADC1_RMP`"]
16pub struct TIM1_ETR_ADC1_RMP_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> TIM1_ETR_ADC1_RMP_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
24        self.w
25    }
26}
27#[doc = "Reader of field `TI1_RMP`"]
28pub type TI1_RMP_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `TI1_RMP`"]
30pub struct TI1_RMP_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> TI1_RMP_W<'a> {
34    #[doc = r"Sets the field bit"]
35    #[inline(always)]
36    pub fn set_bit(self) -> &'a mut W {
37        self.bit(true)
38    }
39    #[doc = r"Clears the field bit"]
40    #[inline(always)]
41    pub fn clear_bit(self) -> &'a mut W {
42        self.bit(false)
43    }
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub fn bit(self, value: bool) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
48        self.w
49    }
50}
51impl R {
52    #[doc = "Bits 0:1 - TIM1_ETR_ADC1 remapping capability"]
53    #[inline(always)]
54    pub fn tim1_etr_adc1_rmp(&self) -> TIM1_ETR_ADC1_RMP_R {
55        TIM1_ETR_ADC1_RMP_R::new((self.bits & 0x03) as u8)
56    }
57    #[doc = "Bit 4 - Input Capture 1 remap"]
58    #[inline(always)]
59    pub fn ti1_rmp(&self) -> TI1_RMP_R {
60        TI1_RMP_R::new(((self.bits >> 4) & 0x01) != 0)
61    }
62}
63impl W {
64    #[doc = "Bits 0:1 - TIM1_ETR_ADC1 remapping capability"]
65    #[inline(always)]
66    pub fn tim1_etr_adc1_rmp(&mut self) -> TIM1_ETR_ADC1_RMP_W {
67        TIM1_ETR_ADC1_RMP_W { w: self }
68    }
69    #[doc = "Bit 4 - Input Capture 1 remap"]
70    #[inline(always)]
71    pub fn ti1_rmp(&mut self) -> TI1_RMP_W {
72        TI1_RMP_W { w: self }
73    }
74}
stm32wb_pac/tim1/or.rs

stm32wb_pac/tim1/
or.rs
