stm32wb_pac/rng/
sr.rs

1#[doc = "Reader of register SR"]
2pub type R = crate::R<u32, super::SR>;
3#[doc = "Writer for register SR"]
4pub type W = crate::W<u32, super::SR>;
5#[doc = "Register SR `reset()`'s with value 0"]
6impl crate::ResetValue for super::SR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `SEIS`"]
14pub type SEIS_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `SEIS`"]
16pub struct SEIS_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> SEIS_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
34        self.w
35    }
36}
37#[doc = "Reader of field `CEIS`"]
38pub type CEIS_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `CEIS`"]
40pub struct CEIS_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> CEIS_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
58        self.w
59    }
60}
61#[doc = "Reader of field `SECS`"]
62pub type SECS_R = crate::R<bool, bool>;
63#[doc = "Reader of field `CECS`"]
64pub type CECS_R = crate::R<bool, bool>;
65#[doc = "Reader of field `DRDY`"]
66pub type DRDY_R = crate::R<bool, bool>;
67impl R {
68    #[doc = "Bit 6 - Seed error interrupt status"]
69    #[inline(always)]
70    pub fn seis(&self) -> SEIS_R {
71        SEIS_R::new(((self.bits >> 6) & 0x01) != 0)
72    }
73    #[doc = "Bit 5 - Clock error interrupt status"]
74    #[inline(always)]
75    pub fn ceis(&self) -> CEIS_R {
76        CEIS_R::new(((self.bits >> 5) & 0x01) != 0)
77    }
78    #[doc = "Bit 2 - Seed error current status"]
79    #[inline(always)]
80    pub fn secs(&self) -> SECS_R {
81        SECS_R::new(((self.bits >> 2) & 0x01) != 0)
82    }
83    #[doc = "Bit 1 - Clock error current status"]
84    #[inline(always)]
85    pub fn cecs(&self) -> CECS_R {
86        CECS_R::new(((self.bits >> 1) & 0x01) != 0)
87    }
88    #[doc = "Bit 0 - Data ready"]
89    #[inline(always)]
90    pub fn drdy(&self) -> DRDY_R {
91        DRDY_R::new((self.bits & 0x01) != 0)
92    }
93}
94impl W {
95    #[doc = "Bit 6 - Seed error interrupt status"]
96    #[inline(always)]
97    pub fn seis(&mut self) -> SEIS_W {
98        SEIS_W { w: self }
99    }
100    #[doc = "Bit 5 - Clock error interrupt status"]
101    #[inline(always)]
102    pub fn ceis(&mut self) -> CEIS_W {
103        CEIS_W { w: self }
104    }
105}
stm32wb_pac/rng/sr.rs

stm32wb_pac/rng/
sr.rs
