stm32wb_pac/quadspi/
ccr.rs

1#[doc = "Reader of register CCR"]
2pub type R = crate::R<u32, super::CCR>;
3#[doc = "Writer for register CCR"]
4pub type W = crate::W<u32, super::CCR>;
5#[doc = "Register CCR `reset()`'s with value 0"]
6impl crate::ResetValue for super::CCR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DDRM`"]
14pub type DDRM_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `DDRM`"]
16pub struct DDRM_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DDRM_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
34        self.w
35    }
36}
37#[doc = "Reader of field `SIOO`"]
38pub type SIOO_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `SIOO`"]
40pub struct SIOO_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> SIOO_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
58        self.w
59    }
60}
61#[doc = "Reader of field `FMODE`"]
62pub type FMODE_R = crate::R<u8, u8>;
63#[doc = "Write proxy for field `FMODE`"]
64pub struct FMODE_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> FMODE_W<'a> {
68    #[doc = r"Writes raw bits to the field"]
69    #[inline(always)]
70    pub unsafe fn bits(self, value: u8) -> &'a mut W {
71        self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
72        self.w
73    }
74}
75#[doc = "Reader of field `DMODE`"]
76pub type DMODE_R = crate::R<u8, u8>;
77#[doc = "Write proxy for field `DMODE`"]
78pub struct DMODE_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> DMODE_W<'a> {
82    #[doc = r"Writes raw bits to the field"]
83    #[inline(always)]
84    pub unsafe fn bits(self, value: u8) -> &'a mut W {
85        self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
86        self.w
87    }
88}
89#[doc = "Reader of field `DCYC`"]
90pub type DCYC_R = crate::R<u8, u8>;
91#[doc = "Write proxy for field `DCYC`"]
92pub struct DCYC_W<'a> {
93    w: &'a mut W,
94}
95impl<'a> DCYC_W<'a> {
96    #[doc = r"Writes raw bits to the field"]
97    #[inline(always)]
98    pub unsafe fn bits(self, value: u8) -> &'a mut W {
99        self.w.bits = (self.w.bits & !(0x1f << 18)) | (((value as u32) & 0x1f) << 18);
100        self.w
101    }
102}
103#[doc = "Reader of field `ABSIZE`"]
104pub type ABSIZE_R = crate::R<u8, u8>;
105#[doc = "Write proxy for field `ABSIZE`"]
106pub struct ABSIZE_W<'a> {
107    w: &'a mut W,
108}
109impl<'a> ABSIZE_W<'a> {
110    #[doc = r"Writes raw bits to the field"]
111    #[inline(always)]
112    pub unsafe fn bits(self, value: u8) -> &'a mut W {
113        self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
114        self.w
115    }
116}
117#[doc = "Reader of field `ABMODE`"]
118pub type ABMODE_R = crate::R<u8, u8>;
119#[doc = "Write proxy for field `ABMODE`"]
120pub struct ABMODE_W<'a> {
121    w: &'a mut W,
122}
123impl<'a> ABMODE_W<'a> {
124    #[doc = r"Writes raw bits to the field"]
125    #[inline(always)]
126    pub unsafe fn bits(self, value: u8) -> &'a mut W {
127        self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
128        self.w
129    }
130}
131#[doc = "Reader of field `ADSIZE`"]
132pub type ADSIZE_R = crate::R<u8, u8>;
133#[doc = "Write proxy for field `ADSIZE`"]
134pub struct ADSIZE_W<'a> {
135    w: &'a mut W,
136}
137impl<'a> ADSIZE_W<'a> {
138    #[doc = r"Writes raw bits to the field"]
139    #[inline(always)]
140    pub unsafe fn bits(self, value: u8) -> &'a mut W {
141        self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
142        self.w
143    }
144}
145#[doc = "Reader of field `ADMODE`"]
146pub type ADMODE_R = crate::R<u8, u8>;
147#[doc = "Write proxy for field `ADMODE`"]
148pub struct ADMODE_W<'a> {
149    w: &'a mut W,
150}
151impl<'a> ADMODE_W<'a> {
152    #[doc = r"Writes raw bits to the field"]
153    #[inline(always)]
154    pub unsafe fn bits(self, value: u8) -> &'a mut W {
155        self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
156        self.w
157    }
158}
159#[doc = "Reader of field `IMODE`"]
160pub type IMODE_R = crate::R<u8, u8>;
161#[doc = "Write proxy for field `IMODE`"]
162pub struct IMODE_W<'a> {
163    w: &'a mut W,
164}
165impl<'a> IMODE_W<'a> {
166    #[doc = r"Writes raw bits to the field"]
167    #[inline(always)]
168    pub unsafe fn bits(self, value: u8) -> &'a mut W {
169        self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
170        self.w
171    }
172}
173#[doc = "Reader of field `INSTRUCTION`"]
174pub type INSTRUCTION_R = crate::R<u8, u8>;
175#[doc = "Write proxy for field `INSTRUCTION`"]
176pub struct INSTRUCTION_W<'a> {
177    w: &'a mut W,
178}
179impl<'a> INSTRUCTION_W<'a> {
180    #[doc = r"Writes raw bits to the field"]
181    #[inline(always)]
182    pub unsafe fn bits(self, value: u8) -> &'a mut W {
183        self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
184        self.w
185    }
186}
187impl R {
188    #[doc = "Bit 31 - Double data rate mode"]
189    #[inline(always)]
190    pub fn ddrm(&self) -> DDRM_R {
191        DDRM_R::new(((self.bits >> 31) & 0x01) != 0)
192    }
193    #[doc = "Bit 28 - Send instruction only once mode"]
194    #[inline(always)]
195    pub fn sioo(&self) -> SIOO_R {
196        SIOO_R::new(((self.bits >> 28) & 0x01) != 0)
197    }
198    #[doc = "Bits 26:27 - Functional mode"]
199    #[inline(always)]
200    pub fn fmode(&self) -> FMODE_R {
201        FMODE_R::new(((self.bits >> 26) & 0x03) as u8)
202    }
203    #[doc = "Bits 24:25 - Data mode"]
204    #[inline(always)]
205    pub fn dmode(&self) -> DMODE_R {
206        DMODE_R::new(((self.bits >> 24) & 0x03) as u8)
207    }
208    #[doc = "Bits 18:22 - Number of dummy cycles"]
209    #[inline(always)]
210    pub fn dcyc(&self) -> DCYC_R {
211        DCYC_R::new(((self.bits >> 18) & 0x1f) as u8)
212    }
213    #[doc = "Bits 16:17 - Alternate bytes size"]
214    #[inline(always)]
215    pub fn absize(&self) -> ABSIZE_R {
216        ABSIZE_R::new(((self.bits >> 16) & 0x03) as u8)
217    }
218    #[doc = "Bits 14:15 - Alternate bytes mode"]
219    #[inline(always)]
220    pub fn abmode(&self) -> ABMODE_R {
221        ABMODE_R::new(((self.bits >> 14) & 0x03) as u8)
222    }
223    #[doc = "Bits 12:13 - Address size"]
224    #[inline(always)]
225    pub fn adsize(&self) -> ADSIZE_R {
226        ADSIZE_R::new(((self.bits >> 12) & 0x03) as u8)
227    }
228    #[doc = "Bits 10:11 - Address mode"]
229    #[inline(always)]
230    pub fn admode(&self) -> ADMODE_R {
231        ADMODE_R::new(((self.bits >> 10) & 0x03) as u8)
232    }
233    #[doc = "Bits 8:9 - Instruction mode"]
234    #[inline(always)]
235    pub fn imode(&self) -> IMODE_R {
236        IMODE_R::new(((self.bits >> 8) & 0x03) as u8)
237    }
238    #[doc = "Bits 0:7 - Instruction"]
239    #[inline(always)]
240    pub fn instruction(&self) -> INSTRUCTION_R {
241        INSTRUCTION_R::new((self.bits & 0xff) as u8)
242    }
243}
244impl W {
245    #[doc = "Bit 31 - Double data rate mode"]
246    #[inline(always)]
247    pub fn ddrm(&mut self) -> DDRM_W {
248        DDRM_W { w: self }
249    }
250    #[doc = "Bit 28 - Send instruction only once mode"]
251    #[inline(always)]
252    pub fn sioo(&mut self) -> SIOO_W {
253        SIOO_W { w: self }
254    }
255    #[doc = "Bits 26:27 - Functional mode"]
256    #[inline(always)]
257    pub fn fmode(&mut self) -> FMODE_W {
258        FMODE_W { w: self }
259    }
260    #[doc = "Bits 24:25 - Data mode"]
261    #[inline(always)]
262    pub fn dmode(&mut self) -> DMODE_W {
263        DMODE_W { w: self }
264    }
265    #[doc = "Bits 18:22 - Number of dummy cycles"]
266    #[inline(always)]
267    pub fn dcyc(&mut self) -> DCYC_W {
268        DCYC_W { w: self }
269    }
270    #[doc = "Bits 16:17 - Alternate bytes size"]
271    #[inline(always)]
272    pub fn absize(&mut self) -> ABSIZE_W {
273        ABSIZE_W { w: self }
274    }
275    #[doc = "Bits 14:15 - Alternate bytes mode"]
276    #[inline(always)]
277    pub fn abmode(&mut self) -> ABMODE_W {
278        ABMODE_W { w: self }
279    }
280    #[doc = "Bits 12:13 - Address size"]
281    #[inline(always)]
282    pub fn adsize(&mut self) -> ADSIZE_W {
283        ADSIZE_W { w: self }
284    }
285    #[doc = "Bits 10:11 - Address mode"]
286    #[inline(always)]
287    pub fn admode(&mut self) -> ADMODE_W {
288        ADMODE_W { w: self }
289    }
290    #[doc = "Bits 8:9 - Instruction mode"]
291    #[inline(always)]
292    pub fn imode(&mut self) -> IMODE_W {
293        IMODE_W { w: self }
294    }
295    #[doc = "Bits 0:7 - Instruction"]
296    #[inline(always)]
297    pub fn instruction(&mut self) -> INSTRUCTION_W {
298        INSTRUCTION_W { w: self }
299    }
300}
stm32wb_pac/quadspi/ccr.rs

stm32wb_pac/quadspi/
ccr.rs
