stm32wb_pac/dma1/
ccr2.rs

1#[doc = "Reader of register CCR2"]
2pub type R = crate::R<u32, super::CCR2>;
3#[doc = "Writer for register CCR2"]
4pub type W = crate::W<u32, super::CCR2>;
5#[doc = "Register CCR2 `reset()`'s with value 0"]
6impl crate::ResetValue for super::CCR2 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `MEM2MEM`"]
14pub type MEM2MEM_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `MEM2MEM`"]
16pub struct MEM2MEM_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> MEM2MEM_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
34        self.w
35    }
36}
37#[doc = "Reader of field `PL`"]
38pub type PL_R = crate::R<u8, u8>;
39#[doc = "Write proxy for field `PL`"]
40pub struct PL_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> PL_W<'a> {
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub unsafe fn bits(self, value: u8) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
48        self.w
49    }
50}
51#[doc = "Reader of field `MSIZE`"]
52pub type MSIZE_R = crate::R<u8, u8>;
53#[doc = "Write proxy for field `MSIZE`"]
54pub struct MSIZE_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> MSIZE_W<'a> {
58    #[doc = r"Writes raw bits to the field"]
59    #[inline(always)]
60    pub unsafe fn bits(self, value: u8) -> &'a mut W {
61        self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
62        self.w
63    }
64}
65#[doc = "Reader of field `PSIZE`"]
66pub type PSIZE_R = crate::R<u8, u8>;
67#[doc = "Write proxy for field `PSIZE`"]
68pub struct PSIZE_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> PSIZE_W<'a> {
72    #[doc = r"Writes raw bits to the field"]
73    #[inline(always)]
74    pub unsafe fn bits(self, value: u8) -> &'a mut W {
75        self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
76        self.w
77    }
78}
79#[doc = "Reader of field `MINC`"]
80pub type MINC_R = crate::R<bool, bool>;
81#[doc = "Write proxy for field `MINC`"]
82pub struct MINC_W<'a> {
83    w: &'a mut W,
84}
85impl<'a> MINC_W<'a> {
86    #[doc = r"Sets the field bit"]
87    #[inline(always)]
88    pub fn set_bit(self) -> &'a mut W {
89        self.bit(true)
90    }
91    #[doc = r"Clears the field bit"]
92    #[inline(always)]
93    pub fn clear_bit(self) -> &'a mut W {
94        self.bit(false)
95    }
96    #[doc = r"Writes raw bits to the field"]
97    #[inline(always)]
98    pub fn bit(self, value: bool) -> &'a mut W {
99        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
100        self.w
101    }
102}
103#[doc = "Reader of field `PINC`"]
104pub type PINC_R = crate::R<bool, bool>;
105#[doc = "Write proxy for field `PINC`"]
106pub struct PINC_W<'a> {
107    w: &'a mut W,
108}
109impl<'a> PINC_W<'a> {
110    #[doc = r"Sets the field bit"]
111    #[inline(always)]
112    pub fn set_bit(self) -> &'a mut W {
113        self.bit(true)
114    }
115    #[doc = r"Clears the field bit"]
116    #[inline(always)]
117    pub fn clear_bit(self) -> &'a mut W {
118        self.bit(false)
119    }
120    #[doc = r"Writes raw bits to the field"]
121    #[inline(always)]
122    pub fn bit(self, value: bool) -> &'a mut W {
123        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
124        self.w
125    }
126}
127#[doc = "Reader of field `CIRC`"]
128pub type CIRC_R = crate::R<bool, bool>;
129#[doc = "Write proxy for field `CIRC`"]
130pub struct CIRC_W<'a> {
131    w: &'a mut W,
132}
133impl<'a> CIRC_W<'a> {
134    #[doc = r"Sets the field bit"]
135    #[inline(always)]
136    pub fn set_bit(self) -> &'a mut W {
137        self.bit(true)
138    }
139    #[doc = r"Clears the field bit"]
140    #[inline(always)]
141    pub fn clear_bit(self) -> &'a mut W {
142        self.bit(false)
143    }
144    #[doc = r"Writes raw bits to the field"]
145    #[inline(always)]
146    pub fn bit(self, value: bool) -> &'a mut W {
147        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
148        self.w
149    }
150}
151#[doc = "Reader of field `DIR`"]
152pub type DIR_R = crate::R<bool, bool>;
153#[doc = "Write proxy for field `DIR`"]
154pub struct DIR_W<'a> {
155    w: &'a mut W,
156}
157impl<'a> DIR_W<'a> {
158    #[doc = r"Sets the field bit"]
159    #[inline(always)]
160    pub fn set_bit(self) -> &'a mut W {
161        self.bit(true)
162    }
163    #[doc = r"Clears the field bit"]
164    #[inline(always)]
165    pub fn clear_bit(self) -> &'a mut W {
166        self.bit(false)
167    }
168    #[doc = r"Writes raw bits to the field"]
169    #[inline(always)]
170    pub fn bit(self, value: bool) -> &'a mut W {
171        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
172        self.w
173    }
174}
175#[doc = "Reader of field `TEIE`"]
176pub type TEIE_R = crate::R<bool, bool>;
177#[doc = "Write proxy for field `TEIE`"]
178pub struct TEIE_W<'a> {
179    w: &'a mut W,
180}
181impl<'a> TEIE_W<'a> {
182    #[doc = r"Sets the field bit"]
183    #[inline(always)]
184    pub fn set_bit(self) -> &'a mut W {
185        self.bit(true)
186    }
187    #[doc = r"Clears the field bit"]
188    #[inline(always)]
189    pub fn clear_bit(self) -> &'a mut W {
190        self.bit(false)
191    }
192    #[doc = r"Writes raw bits to the field"]
193    #[inline(always)]
194    pub fn bit(self, value: bool) -> &'a mut W {
195        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
196        self.w
197    }
198}
199#[doc = "Reader of field `HTIE`"]
200pub type HTIE_R = crate::R<bool, bool>;
201#[doc = "Write proxy for field `HTIE`"]
202pub struct HTIE_W<'a> {
203    w: &'a mut W,
204}
205impl<'a> HTIE_W<'a> {
206    #[doc = r"Sets the field bit"]
207    #[inline(always)]
208    pub fn set_bit(self) -> &'a mut W {
209        self.bit(true)
210    }
211    #[doc = r"Clears the field bit"]
212    #[inline(always)]
213    pub fn clear_bit(self) -> &'a mut W {
214        self.bit(false)
215    }
216    #[doc = r"Writes raw bits to the field"]
217    #[inline(always)]
218    pub fn bit(self, value: bool) -> &'a mut W {
219        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
220        self.w
221    }
222}
223#[doc = "Reader of field `TCIE`"]
224pub type TCIE_R = crate::R<bool, bool>;
225#[doc = "Write proxy for field `TCIE`"]
226pub struct TCIE_W<'a> {
227    w: &'a mut W,
228}
229impl<'a> TCIE_W<'a> {
230    #[doc = r"Sets the field bit"]
231    #[inline(always)]
232    pub fn set_bit(self) -> &'a mut W {
233        self.bit(true)
234    }
235    #[doc = r"Clears the field bit"]
236    #[inline(always)]
237    pub fn clear_bit(self) -> &'a mut W {
238        self.bit(false)
239    }
240    #[doc = r"Writes raw bits to the field"]
241    #[inline(always)]
242    pub fn bit(self, value: bool) -> &'a mut W {
243        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
244        self.w
245    }
246}
247#[doc = "Reader of field `EN`"]
248pub type EN_R = crate::R<bool, bool>;
249#[doc = "Write proxy for field `EN`"]
250pub struct EN_W<'a> {
251    w: &'a mut W,
252}
253impl<'a> EN_W<'a> {
254    #[doc = r"Sets the field bit"]
255    #[inline(always)]
256    pub fn set_bit(self) -> &'a mut W {
257        self.bit(true)
258    }
259    #[doc = r"Clears the field bit"]
260    #[inline(always)]
261    pub fn clear_bit(self) -> &'a mut W {
262        self.bit(false)
263    }
264    #[doc = r"Writes raw bits to the field"]
265    #[inline(always)]
266    pub fn bit(self, value: bool) -> &'a mut W {
267        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
268        self.w
269    }
270}
271impl R {
272    #[doc = "Bit 14 - Memory to memory mode"]
273    #[inline(always)]
274    pub fn mem2mem(&self) -> MEM2MEM_R {
275        MEM2MEM_R::new(((self.bits >> 14) & 0x01) != 0)
276    }
277    #[doc = "Bits 12:13 - Channel priority level"]
278    #[inline(always)]
279    pub fn pl(&self) -> PL_R {
280        PL_R::new(((self.bits >> 12) & 0x03) as u8)
281    }
282    #[doc = "Bits 10:11 - Memory size"]
283    #[inline(always)]
284    pub fn msize(&self) -> MSIZE_R {
285        MSIZE_R::new(((self.bits >> 10) & 0x03) as u8)
286    }
287    #[doc = "Bits 8:9 - Peripheral size"]
288    #[inline(always)]
289    pub fn psize(&self) -> PSIZE_R {
290        PSIZE_R::new(((self.bits >> 8) & 0x03) as u8)
291    }
292    #[doc = "Bit 7 - Memory increment mode"]
293    #[inline(always)]
294    pub fn minc(&self) -> MINC_R {
295        MINC_R::new(((self.bits >> 7) & 0x01) != 0)
296    }
297    #[doc = "Bit 6 - Peripheral increment mode"]
298    #[inline(always)]
299    pub fn pinc(&self) -> PINC_R {
300        PINC_R::new(((self.bits >> 6) & 0x01) != 0)
301    }
302    #[doc = "Bit 5 - Circular mode"]
303    #[inline(always)]
304    pub fn circ(&self) -> CIRC_R {
305        CIRC_R::new(((self.bits >> 5) & 0x01) != 0)
306    }
307    #[doc = "Bit 4 - Data transfer direction"]
308    #[inline(always)]
309    pub fn dir(&self) -> DIR_R {
310        DIR_R::new(((self.bits >> 4) & 0x01) != 0)
311    }
312    #[doc = "Bit 3 - Transfer error interrupt enable"]
313    #[inline(always)]
314    pub fn teie(&self) -> TEIE_R {
315        TEIE_R::new(((self.bits >> 3) & 0x01) != 0)
316    }
317    #[doc = "Bit 2 - Half transfer interrupt enable"]
318    #[inline(always)]
319    pub fn htie(&self) -> HTIE_R {
320        HTIE_R::new(((self.bits >> 2) & 0x01) != 0)
321    }
322    #[doc = "Bit 1 - Transfer complete interrupt enable"]
323    #[inline(always)]
324    pub fn tcie(&self) -> TCIE_R {
325        TCIE_R::new(((self.bits >> 1) & 0x01) != 0)
326    }
327    #[doc = "Bit 0 - Channel enable"]
328    #[inline(always)]
329    pub fn en(&self) -> EN_R {
330        EN_R::new((self.bits & 0x01) != 0)
331    }
332}
333impl W {
334    #[doc = "Bit 14 - Memory to memory mode"]
335    #[inline(always)]
336    pub fn mem2mem(&mut self) -> MEM2MEM_W {
337        MEM2MEM_W { w: self }
338    }
339    #[doc = "Bits 12:13 - Channel priority level"]
340    #[inline(always)]
341    pub fn pl(&mut self) -> PL_W {
342        PL_W { w: self }
343    }
344    #[doc = "Bits 10:11 - Memory size"]
345    #[inline(always)]
346    pub fn msize(&mut self) -> MSIZE_W {
347        MSIZE_W { w: self }
348    }
349    #[doc = "Bits 8:9 - Peripheral size"]
350    #[inline(always)]
351    pub fn psize(&mut self) -> PSIZE_W {
352        PSIZE_W { w: self }
353    }
354    #[doc = "Bit 7 - Memory increment mode"]
355    #[inline(always)]
356    pub fn minc(&mut self) -> MINC_W {
357        MINC_W { w: self }
358    }
359    #[doc = "Bit 6 - Peripheral increment mode"]
360    #[inline(always)]
361    pub fn pinc(&mut self) -> PINC_W {
362        PINC_W { w: self }
363    }
364    #[doc = "Bit 5 - Circular mode"]
365    #[inline(always)]
366    pub fn circ(&mut self) -> CIRC_W {
367        CIRC_W { w: self }
368    }
369    #[doc = "Bit 4 - Data transfer direction"]
370    #[inline(always)]
371    pub fn dir(&mut self) -> DIR_W {
372        DIR_W { w: self }
373    }
374    #[doc = "Bit 3 - Transfer error interrupt enable"]
375    #[inline(always)]
376    pub fn teie(&mut self) -> TEIE_W {
377        TEIE_W { w: self }
378    }
379    #[doc = "Bit 2 - Half transfer interrupt enable"]
380    #[inline(always)]
381    pub fn htie(&mut self) -> HTIE_W {
382        HTIE_W { w: self }
383    }
384    #[doc = "Bit 1 - Transfer complete interrupt enable"]
385    #[inline(always)]
386    pub fn tcie(&mut self) -> TCIE_W {
387        TCIE_W { w: self }
388    }
389    #[doc = "Bit 0 - Channel enable"]
390    #[inline(always)]
391    pub fn en(&mut self) -> EN_W {
392        EN_W { w: self }
393    }
394}
stm32wb_pac/dma1/ccr2.rs

stm32wb_pac/dma1/
ccr2.rs
