[][src]Type Definition stm32wb_pac::ipcc::c1mr::W

type W = W<u32, C1MR>;

Writer for register C1MR

Implementations

impl W[src]

pub fn ch6fm(&mut self) -> CH6FM_W<'_>[src]

Bit 21 - processor 1 Transmit channel 6 free interrupt mask

pub fn ch5fm(&mut self) -> CH5FM_W<'_>[src]

Bit 20 - processor 1 Transmit channel 5 free interrupt mask

pub fn ch4fm(&mut self) -> CH4FM_W<'_>[src]

Bit 19 - processor 1 Transmit channel 4 free interrupt mask

pub fn ch3fm(&mut self) -> CH3FM_W<'_>[src]

Bit 18 - processor 1 Transmit channel 3 free interrupt mask

pub fn ch2fm(&mut self) -> CH2FM_W<'_>[src]

Bit 17 - processor 1 Transmit channel 2 free interrupt mask

pub fn ch1fm(&mut self) -> CH1FM_W<'_>[src]

Bit 16 - processor 1 Transmit channel 1 free interrupt mask

pub fn ch6om(&mut self) -> CH6OM_W<'_>[src]

Bit 5 - processor 1 Receive channel 6 occupied interrupt enable

pub fn ch5om(&mut self) -> CH5OM_W<'_>[src]

Bit 4 - processor 1 Receive channel 5 occupied interrupt enable

pub fn ch4om(&mut self) -> CH4OM_W<'_>[src]

Bit 3 - processor 1 Receive channel 4 occupied interrupt enable

pub fn ch3om(&mut self) -> CH3OM_W<'_>[src]

Bit 2 - processor 1 Receive channel 3 occupied interrupt enable

pub fn ch2om(&mut self) -> CH2OM_W<'_>[src]

Bit 1 - processor 1 Receive channel 2 occupied interrupt enable

pub fn ch1om(&mut self) -> CH1OM_W<'_>[src]

Bit 0 - processor 1 Receive channel 1 occupied interrupt enable