stm32wb_pac/nvic_stir/
stir.rs

1#[doc = "Reader of register STIR"]
2pub type R = crate::R<u32, super::STIR>;
3#[doc = "Writer for register STIR"]
4pub type W = crate::W<u32, super::STIR>;
5#[doc = "Register STIR `reset()`'s with value 0"]
6impl crate::ResetValue for super::STIR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `INTID`"]
14pub type INTID_R = crate::R<u16, u16>;
15#[doc = "Write proxy for field `INTID`"]
16pub struct INTID_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> INTID_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u16) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0x01ff) | ((value as u32) & 0x01ff);
24        self.w
25    }
26}
27impl R {
28    #[doc = "Bits 0:8 - Software generated interrupt ID"]
29    #[inline(always)]
30    pub fn intid(&self) -> INTID_R {
31        INTID_R::new((self.bits & 0x01ff) as u16)
32    }
33}
34impl W {
35    #[doc = "Bits 0:8 - Software generated interrupt ID"]
36    #[inline(always)]
37    pub fn intid(&mut self) -> INTID_W {
38        INTID_W { w: self }
39    }
40}
stm32wb_pac/nvic_stir/stir.rs

stm32wb_pac/nvic_stir/
stir.rs
