stm32wb_pac/gpioh/
moder.rs

1#[doc = "Reader of register MODER"]
2pub type R = crate::R<u32, super::MODER>;
3#[doc = "Writer for register MODER"]
4pub type W = crate::W<u32, super::MODER>;
5#[doc = "Register MODER `reset()`'s with value 0xcf"]
6impl crate::ResetValue for super::MODER {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0xcf
11    }
12}
13#[doc = "Reader of field `MODER3`"]
14pub type MODER3_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `MODER3`"]
16pub struct MODER3_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> MODER3_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
24        self.w
25    }
26}
27#[doc = "Reader of field `MODER1`"]
28pub type MODER1_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `MODER1`"]
30pub struct MODER1_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> MODER1_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
38        self.w
39    }
40}
41#[doc = "Reader of field `MODER0`"]
42pub type MODER0_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `MODER0`"]
44pub struct MODER0_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> MODER0_W<'a> {
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub unsafe fn bits(self, value: u8) -> &'a mut W {
51        self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
52        self.w
53    }
54}
55impl R {
56    #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"]
57    #[inline(always)]
58    pub fn moder3(&self) -> MODER3_R {
59        MODER3_R::new(((self.bits >> 6) & 0x03) as u8)
60    }
61    #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"]
62    #[inline(always)]
63    pub fn moder1(&self) -> MODER1_R {
64        MODER1_R::new(((self.bits >> 2) & 0x03) as u8)
65    }
66    #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"]
67    #[inline(always)]
68    pub fn moder0(&self) -> MODER0_R {
69        MODER0_R::new((self.bits & 0x03) as u8)
70    }
71}
72impl W {
73    #[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"]
74    #[inline(always)]
75    pub fn moder3(&mut self) -> MODER3_W {
76        MODER3_W { w: self }
77    }
78    #[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"]
79    #[inline(always)]
80    pub fn moder1(&mut self) -> MODER1_W {
81        MODER1_W { w: self }
82    }
83    #[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"]
84    #[inline(always)]
85    pub fn moder0(&mut self) -> MODER0_W {
86        MODER0_W { w: self }
87    }
88}
stm32wb_pac/gpioh/moder.rs

stm32wb_pac/gpioh/
moder.rs
