Module fmc

FMC

Modules

bcr

SRAM/NOR-Flash chip-select control register for bank %s

bcr1

SRAM/NOR-Flash chip-select control register for bank 1

btr

SRAM/NOR-Flash chip-select timing register for bank %s

bwtr

SRAM/NOR-Flash write timing registers %s

eccr

This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

patt

The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).

pcr

NAND Flash control registers

pcscntr

PSRAM chip select counter register

pmem

Common memory space timing register

sr

status and interrupt register

Structs

RegisterBlock

Register block

Type Aliases

BCR

BCR (rw) register accessor: SRAM/NOR-Flash chip-select control register for bank %s

BCR1

BCR1 (rw) register accessor: SRAM/NOR-Flash chip-select control register for bank 1

BTR

BTR (rw) register accessor: SRAM/NOR-Flash chip-select timing register for bank %s

BWTR

BWTR (rw) register accessor: SRAM/NOR-Flash write timing registers %s

ECCR

ECCR (r) register accessor: This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

PATT

PATT (rw) register accessor: The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).

PCR

PCR (rw) register accessor: NAND Flash control registers

PCSCNTR

PCSCNTR (rw) register accessor: PSRAM chip select counter register

PMEM

PMEM (rw) register accessor: Common memory space timing register

SR

SR (rw) register accessor: status and interrupt register