stm32u5/stm32u5a9/ucpd1/
icr.rs

1///Register `ICR` writer
2pub type W = crate::W<ICRrs>;
3/**TXMSGDISCCF
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum TXMSGDISCCFW {
9    ///1: Clear flag in UCPD_SR
10    Clear = 1,
11}
12impl From<TXMSGDISCCFW> for bool {
13    #[inline(always)]
14    fn from(variant: TXMSGDISCCFW) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `TXMSGDISCCF` writer - TXMSGDISCCF
19pub type TXMSGDISCCF_W<'a, REG> = crate::BitWriter<'a, REG, TXMSGDISCCFW>;
20impl<'a, REG> TXMSGDISCCF_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Clear flag in UCPD_SR
25    #[inline(always)]
26    pub fn clear(self) -> &'a mut crate::W<REG> {
27        self.variant(TXMSGDISCCFW::Clear)
28    }
29}
30///Field `TXMSGSENTCF` writer - TXMSGSENTCF
31pub use TXMSGDISCCF_W as TXMSGSENTCF_W;
32///Field `TXMSGABTCF` writer - TXMSGABTCF
33pub use TXMSGDISCCF_W as TXMSGABTCF_W;
34///Field `HRSTDISCCF` writer - HRSTDISCCF
35pub use TXMSGDISCCF_W as HRSTDISCCF_W;
36///Field `HRSTSENTCF` writer - HRSTSENTCF
37pub use TXMSGDISCCF_W as HRSTSENTCF_W;
38///Field `TXUNDCF` writer - TXUNDCF
39pub use TXMSGDISCCF_W as TXUNDCF_W;
40///Field `RXORDDETCF` writer - RXORDDETCF
41pub use TXMSGDISCCF_W as RXORDDETCF_W;
42///Field `RXHRSTDETCF` writer - RXHRSTDETCF
43pub use TXMSGDISCCF_W as RXHRSTDETCF_W;
44///Field `RXOVRCF` writer - RXOVRCF
45pub use TXMSGDISCCF_W as RXOVRCF_W;
46///Field `RXMSGENDCF` writer - RXMSGENDCF
47pub use TXMSGDISCCF_W as RXMSGENDCF_W;
48///Field `TYPECEVT1CF` writer - TYPECEVT1CF
49pub use TXMSGDISCCF_W as TYPECEVT1CF_W;
50///Field `TYPECEVT2CF` writer - TYPECEVT2CF
51pub use TXMSGDISCCF_W as TYPECEVT2CF_W;
52///Field `FRSEVTCF` writer - FRSEVTCF
53pub use TXMSGDISCCF_W as FRSEVTCF_W;
54impl core::fmt::Debug for crate::generic::Reg<ICRrs> {
55    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
56        write!(f, "(not readable)")
57    }
58}
59impl W {
60    ///Bit 1 - TXMSGDISCCF
61    #[inline(always)]
62    pub fn txmsgdisccf(&mut self) -> TXMSGDISCCF_W<ICRrs> {
63        TXMSGDISCCF_W::new(self, 1)
64    }
65    ///Bit 2 - TXMSGSENTCF
66    #[inline(always)]
67    pub fn txmsgsentcf(&mut self) -> TXMSGSENTCF_W<ICRrs> {
68        TXMSGSENTCF_W::new(self, 2)
69    }
70    ///Bit 3 - TXMSGABTCF
71    #[inline(always)]
72    pub fn txmsgabtcf(&mut self) -> TXMSGABTCF_W<ICRrs> {
73        TXMSGABTCF_W::new(self, 3)
74    }
75    ///Bit 4 - HRSTDISCCF
76    #[inline(always)]
77    pub fn hrstdisccf(&mut self) -> HRSTDISCCF_W<ICRrs> {
78        HRSTDISCCF_W::new(self, 4)
79    }
80    ///Bit 5 - HRSTSENTCF
81    #[inline(always)]
82    pub fn hrstsentcf(&mut self) -> HRSTSENTCF_W<ICRrs> {
83        HRSTSENTCF_W::new(self, 5)
84    }
85    ///Bit 6 - TXUNDCF
86    #[inline(always)]
87    pub fn txundcf(&mut self) -> TXUNDCF_W<ICRrs> {
88        TXUNDCF_W::new(self, 6)
89    }
90    ///Bit 9 - RXORDDETCF
91    #[inline(always)]
92    pub fn rxorddetcf(&mut self) -> RXORDDETCF_W<ICRrs> {
93        RXORDDETCF_W::new(self, 9)
94    }
95    ///Bit 10 - RXHRSTDETCF
96    #[inline(always)]
97    pub fn rxhrstdetcf(&mut self) -> RXHRSTDETCF_W<ICRrs> {
98        RXHRSTDETCF_W::new(self, 10)
99    }
100    ///Bit 11 - RXOVRCF
101    #[inline(always)]
102    pub fn rxovrcf(&mut self) -> RXOVRCF_W<ICRrs> {
103        RXOVRCF_W::new(self, 11)
104    }
105    ///Bit 12 - RXMSGENDCF
106    #[inline(always)]
107    pub fn rxmsgendcf(&mut self) -> RXMSGENDCF_W<ICRrs> {
108        RXMSGENDCF_W::new(self, 12)
109    }
110    ///Bit 14 - TYPECEVT1CF
111    #[inline(always)]
112    pub fn typecevt1cf(&mut self) -> TYPECEVT1CF_W<ICRrs> {
113        TYPECEVT1CF_W::new(self, 14)
114    }
115    ///Bit 15 - TYPECEVT2CF
116    #[inline(always)]
117    pub fn typecevt2cf(&mut self) -> TYPECEVT2CF_W<ICRrs> {
118        TYPECEVT2CF_W::new(self, 15)
119    }
120    ///Bit 20 - FRSEVTCF
121    #[inline(always)]
122    pub fn frsevtcf(&mut self) -> FRSEVTCF_W<ICRrs> {
123        FRSEVTCF_W::new(self, 20)
124    }
125}
126/**UCPD Interrupt Clear Register
127
128You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
129
130See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U5A9.html#UCPD1:ICR)*/
131pub struct ICRrs;
132impl crate::RegisterSpec for ICRrs {
133    type Ux = u32;
134}
135///`write(|w| ..)` method takes [`icr::W`](W) writer structure
136impl crate::Writable for ICRrs {
137    type Safety = crate::Unsafe;
138}
139///`reset()` method sets ICR to value 0
140impl crate::Resettable for ICRrs {}
stm32u5/stm32u5a9/ucpd1/icr.rs

stm32u5/stm32u5a9/ucpd1/
icr.rs
