stm32u5/stm32u5a9/lptim4/
icr.rs

1///Register `ICR` writer
2pub type W = crate::W<ICRrs>;
3///Field `CC1IF` writer - Capture/compare 1 clear flag
4pub type CC1IF_W<'a, REG> = crate::BitWriter<'a, REG>;
5///Field `ARRMCF` writer - Autoreload match Clear Flag
6pub type ARRMCF_W<'a, REG> = crate::BitWriter<'a, REG>;
7///Field `EXTTRIGCF` writer - External trigger valid edge Clear Flag
8pub type EXTTRIGCF_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `CMP1OKCF` writer - Compare register 1 update OK Clear Flag
10pub type CMP1OKCF_W<'a, REG> = crate::BitWriter<'a, REG>;
11///Field `ARROKCF` writer - Autoreload register update OK Clear Flag
12pub type ARROKCF_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `UPCF` writer - Direction change to UP Clear Flag
14pub type UPCF_W<'a, REG> = crate::BitWriter<'a, REG>;
15///Field `DOWNCF` writer - Direction change to down Clear Flag
16pub type DOWNCF_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `UECF` writer - Update event clear flag
18pub type UECF_W<'a, REG> = crate::BitWriter<'a, REG>;
19///Field `REPOKCF` writer - Repetition register update OK clear flag
20pub type REPOKCF_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `DIEROKCF` writer - Interrupt enable register update OK clear flag
22pub type DIEROKCF_W<'a, REG> = crate::BitWriter<'a, REG>;
23impl core::fmt::Debug for crate::generic::Reg<ICRrs> {
24    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
25        write!(f, "(not readable)")
26    }
27}
28impl W {
29    ///Bit 0 - Capture/compare 1 clear flag
30    #[inline(always)]
31    pub fn cc1if(&mut self) -> CC1IF_W<ICRrs> {
32        CC1IF_W::new(self, 0)
33    }
34    ///Bit 1 - Autoreload match Clear Flag
35    #[inline(always)]
36    pub fn arrmcf(&mut self) -> ARRMCF_W<ICRrs> {
37        ARRMCF_W::new(self, 1)
38    }
39    ///Bit 2 - External trigger valid edge Clear Flag
40    #[inline(always)]
41    pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<ICRrs> {
42        EXTTRIGCF_W::new(self, 2)
43    }
44    ///Bit 3 - Compare register 1 update OK Clear Flag
45    #[inline(always)]
46    pub fn cmp1okcf(&mut self) -> CMP1OKCF_W<ICRrs> {
47        CMP1OKCF_W::new(self, 3)
48    }
49    ///Bit 4 - Autoreload register update OK Clear Flag
50    #[inline(always)]
51    pub fn arrokcf(&mut self) -> ARROKCF_W<ICRrs> {
52        ARROKCF_W::new(self, 4)
53    }
54    ///Bit 5 - Direction change to UP Clear Flag
55    #[inline(always)]
56    pub fn upcf(&mut self) -> UPCF_W<ICRrs> {
57        UPCF_W::new(self, 5)
58    }
59    ///Bit 6 - Direction change to down Clear Flag
60    #[inline(always)]
61    pub fn downcf(&mut self) -> DOWNCF_W<ICRrs> {
62        DOWNCF_W::new(self, 6)
63    }
64    ///Bit 7 - Update event clear flag
65    #[inline(always)]
66    pub fn uecf(&mut self) -> UECF_W<ICRrs> {
67        UECF_W::new(self, 7)
68    }
69    ///Bit 8 - Repetition register update OK clear flag
70    #[inline(always)]
71    pub fn repokcf(&mut self) -> REPOKCF_W<ICRrs> {
72        REPOKCF_W::new(self, 8)
73    }
74    ///Bit 24 - Interrupt enable register update OK clear flag
75    #[inline(always)]
76    pub fn dierokcf(&mut self) -> DIEROKCF_W<ICRrs> {
77        DIEROKCF_W::new(self, 24)
78    }
79}
80/**Interrupt Clear Register
81
82You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
83
84See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U5A9.html#LPTIM4:ICR)*/
85pub struct ICRrs;
86impl crate::RegisterSpec for ICRrs {
87    type Ux = u32;
88}
89///`write(|w| ..)` method takes [`icr::W`](W) writer structure
90impl crate::Writable for ICRrs {
91    type Safety = crate::Unsafe;
92}
93///`reset()` method sets ICR to value 0
94impl crate::Resettable for ICRrs {}
stm32u5/stm32u5a9/lptim4/icr.rs

stm32u5/stm32u5a9/lptim4/
icr.rs
