stm32u5/stm32u5a9/dcmi/
icr.rs

1///Register `ICR` writer
2pub type W = crate::W<ICRrs>;
3/**Capture complete interrupt status clear
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum FRAME_ISC {
9    ///1: Setting this bit clears the FRAME_RIS flag in the DCMI_RIS register
10    Clear = 1,
11}
12impl From<FRAME_ISC> for bool {
13    #[inline(always)]
14    fn from(variant: FRAME_ISC) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `FRAME_ISC` writer - Capture complete interrupt status clear
19pub type FRAME_ISC_W<'a, REG> = crate::BitWriter<'a, REG, FRAME_ISC>;
20impl<'a, REG> FRAME_ISC_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Setting this bit clears the FRAME_RIS flag in the DCMI_RIS register
25    #[inline(always)]
26    pub fn clear(self) -> &'a mut crate::W<REG> {
27        self.variant(FRAME_ISC::Clear)
28    }
29}
30/**Overrun interrupt status clear
31
32Value on reset: 0*/
33#[cfg_attr(feature = "defmt", derive(defmt::Format))]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35pub enum OVR_ISC {
36    ///1: Setting this bit clears the OVR_RIS flag in the DCMI_RIS register
37    Clear = 1,
38}
39impl From<OVR_ISC> for bool {
40    #[inline(always)]
41    fn from(variant: OVR_ISC) -> Self {
42        variant as u8 != 0
43    }
44}
45///Field `OVR_ISC` writer - Overrun interrupt status clear
46pub type OVR_ISC_W<'a, REG> = crate::BitWriter<'a, REG, OVR_ISC>;
47impl<'a, REG> OVR_ISC_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    ///Setting this bit clears the OVR_RIS flag in the DCMI_RIS register
52    #[inline(always)]
53    pub fn clear(self) -> &'a mut crate::W<REG> {
54        self.variant(OVR_ISC::Clear)
55    }
56}
57/**Synchronization error interrupt status clear
58
59Value on reset: 0*/
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum ERR_ISC {
63    ///1: Setting this bit clears the ERR_RIS flag in the DCMI_RIS register
64    Clear = 1,
65}
66impl From<ERR_ISC> for bool {
67    #[inline(always)]
68    fn from(variant: ERR_ISC) -> Self {
69        variant as u8 != 0
70    }
71}
72///Field `ERR_ISC` writer - Synchronization error interrupt status clear
73pub type ERR_ISC_W<'a, REG> = crate::BitWriter<'a, REG, ERR_ISC>;
74impl<'a, REG> ERR_ISC_W<'a, REG>
75where
76    REG: crate::Writable + crate::RegisterSpec,
77{
78    ///Setting this bit clears the ERR_RIS flag in the DCMI_RIS register
79    #[inline(always)]
80    pub fn clear(self) -> &'a mut crate::W<REG> {
81        self.variant(ERR_ISC::Clear)
82    }
83}
84/**Vertical Synchronization interrupt status clear
85
86Value on reset: 0*/
87#[cfg_attr(feature = "defmt", derive(defmt::Format))]
88#[derive(Clone, Copy, Debug, PartialEq, Eq)]
89pub enum VSYNC_ISC {
90    ///1: Setting this bit clears the VSYNC_RIS flag in the DCMI_RIS register
91    Clear = 1,
92}
93impl From<VSYNC_ISC> for bool {
94    #[inline(always)]
95    fn from(variant: VSYNC_ISC) -> Self {
96        variant as u8 != 0
97    }
98}
99///Field `VSYNC_ISC` writer - Vertical Synchronization interrupt status clear
100pub type VSYNC_ISC_W<'a, REG> = crate::BitWriter<'a, REG, VSYNC_ISC>;
101impl<'a, REG> VSYNC_ISC_W<'a, REG>
102where
103    REG: crate::Writable + crate::RegisterSpec,
104{
105    ///Setting this bit clears the VSYNC_RIS flag in the DCMI_RIS register
106    #[inline(always)]
107    pub fn clear(self) -> &'a mut crate::W<REG> {
108        self.variant(VSYNC_ISC::Clear)
109    }
110}
111/**line interrupt status clear
112
113Value on reset: 0*/
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum LINE_ISC {
117    ///1: Setting this bit clears the LINE_RIS flag in the DCMI_RIS register
118    Clear = 1,
119}
120impl From<LINE_ISC> for bool {
121    #[inline(always)]
122    fn from(variant: LINE_ISC) -> Self {
123        variant as u8 != 0
124    }
125}
126///Field `LINE_ISC` writer - line interrupt status clear
127pub type LINE_ISC_W<'a, REG> = crate::BitWriter<'a, REG, LINE_ISC>;
128impl<'a, REG> LINE_ISC_W<'a, REG>
129where
130    REG: crate::Writable + crate::RegisterSpec,
131{
132    ///Setting this bit clears the LINE_RIS flag in the DCMI_RIS register
133    #[inline(always)]
134    pub fn clear(self) -> &'a mut crate::W<REG> {
135        self.variant(LINE_ISC::Clear)
136    }
137}
138impl core::fmt::Debug for crate::generic::Reg<ICRrs> {
139    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
140        write!(f, "(not readable)")
141    }
142}
143impl W {
144    ///Bit 0 - Capture complete interrupt status clear
145    #[inline(always)]
146    pub fn frame_isc(&mut self) -> FRAME_ISC_W<ICRrs> {
147        FRAME_ISC_W::new(self, 0)
148    }
149    ///Bit 1 - Overrun interrupt status clear
150    #[inline(always)]
151    pub fn ovr_isc(&mut self) -> OVR_ISC_W<ICRrs> {
152        OVR_ISC_W::new(self, 1)
153    }
154    ///Bit 2 - Synchronization error interrupt status clear
155    #[inline(always)]
156    pub fn err_isc(&mut self) -> ERR_ISC_W<ICRrs> {
157        ERR_ISC_W::new(self, 2)
158    }
159    ///Bit 3 - Vertical Synchronization interrupt status clear
160    #[inline(always)]
161    pub fn vsync_isc(&mut self) -> VSYNC_ISC_W<ICRrs> {
162        VSYNC_ISC_W::new(self, 3)
163    }
164    ///Bit 4 - line interrupt status clear
165    #[inline(always)]
166    pub fn line_isc(&mut self) -> LINE_ISC_W<ICRrs> {
167        LINE_ISC_W::new(self, 4)
168    }
169}
170/**interrupt clear register
171
172You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
173
174See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U5A9.html#DCMI:ICR)*/
175pub struct ICRrs;
176impl crate::RegisterSpec for ICRrs {
177    type Ux = u32;
178}
179///`write(|w| ..)` method takes [`icr::W`](W) writer structure
180impl crate::Writable for ICRrs {
181    type Safety = crate::Unsafe;
182}
183///`reset()` method sets ICR to value 0
184impl crate::Resettable for ICRrs {}
stm32u5/stm32u5a9/dcmi/icr.rs

stm32u5/stm32u5a9/dcmi/
icr.rs
