stm32u5/stm32u5a5/tim16/
egr.rs

1///Register `EGR` writer
2pub type W = crate::W<EGRrs>;
3/**Update generation
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum UG {
9    ///1: Re-initializes the timer counter and generates an update of the registers.
10    Update = 1,
11}
12impl From<UG> for bool {
13    #[inline(always)]
14    fn from(variant: UG) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `UG` writer - Update generation
19pub type UG_W<'a, REG> = crate::BitWriter<'a, REG, UG>;
20impl<'a, REG> UG_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Re-initializes the timer counter and generates an update of the registers.
25    #[inline(always)]
26    pub fn update(self) -> &'a mut crate::W<REG> {
27        self.variant(UG::Update)
28    }
29}
30/**Capture/compare %s generation
31
32Value on reset: 0*/
33#[cfg_attr(feature = "defmt", derive(defmt::Format))]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35pub enum CC1GW {
36    ///1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
37    Trigger = 1,
38}
39impl From<CC1GW> for bool {
40    #[inline(always)]
41    fn from(variant: CC1GW) -> Self {
42        variant as u8 != 0
43    }
44}
45///Field `CCG(1-1)` writer - Capture/compare %s generation
46pub type CCG_W<'a, REG> = crate::BitWriter<'a, REG, CC1GW>;
47impl<'a, REG> CCG_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    ///If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
52    #[inline(always)]
53    pub fn trigger(self) -> &'a mut crate::W<REG> {
54        self.variant(CC1GW::Trigger)
55    }
56}
57/**Capture/Compare control update generation
58
59Value on reset: 0*/
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum COMGW {
63    ///1: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
64    Trigger = 1,
65}
66impl From<COMGW> for bool {
67    #[inline(always)]
68    fn from(variant: COMGW) -> Self {
69        variant as u8 != 0
70    }
71}
72///Field `COMG` writer - Capture/Compare control update generation
73pub type COMG_W<'a, REG> = crate::BitWriter<'a, REG, COMGW>;
74impl<'a, REG> COMG_W<'a, REG>
75where
76    REG: crate::Writable + crate::RegisterSpec,
77{
78    ///When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
79    #[inline(always)]
80    pub fn trigger(self) -> &'a mut crate::W<REG> {
81        self.variant(COMGW::Trigger)
82    }
83}
84/**Break generation
85
86Value on reset: 0*/
87#[cfg_attr(feature = "defmt", derive(defmt::Format))]
88#[derive(Clone, Copy, Debug, PartialEq, Eq)]
89pub enum BGW {
90    ///1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
91    Trigger = 1,
92}
93impl From<BGW> for bool {
94    #[inline(always)]
95    fn from(variant: BGW) -> Self {
96        variant as u8 != 0
97    }
98}
99///Field `BG` writer - Break generation
100pub type BG_W<'a, REG> = crate::BitWriter<'a, REG, BGW>;
101impl<'a, REG> BG_W<'a, REG>
102where
103    REG: crate::Writable + crate::RegisterSpec,
104{
105    ///A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
106    #[inline(always)]
107    pub fn trigger(self) -> &'a mut crate::W<REG> {
108        self.variant(BGW::Trigger)
109    }
110}
111impl core::fmt::Debug for crate::generic::Reg<EGRrs> {
112    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
113        write!(f, "(not readable)")
114    }
115}
116impl W {
117    ///Bit 0 - Update generation
118    #[inline(always)]
119    pub fn ug(&mut self) -> UG_W<EGRrs> {
120        UG_W::new(self, 0)
121    }
122    ///Capture/compare (1-1) generation
123    ///
124    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1G` field.</div>
125    #[inline(always)]
126    pub fn ccg(&mut self, n: u8) -> CCG_W<EGRrs> {
127        #[allow(clippy::no_effect)]
128        [(); 1][n as usize];
129        CCG_W::new(self, n * 0 + 1)
130    }
131    ///Bit 1 - Capture/compare 1 generation
132    #[inline(always)]
133    pub fn cc1g(&mut self) -> CCG_W<EGRrs> {
134        CCG_W::new(self, 1)
135    }
136    ///Bit 5 - Capture/Compare control update generation
137    #[inline(always)]
138    pub fn comg(&mut self) -> COMG_W<EGRrs> {
139        COMG_W::new(self, 5)
140    }
141    ///Bit 7 - Break generation
142    #[inline(always)]
143    pub fn bg(&mut self) -> BG_W<EGRrs> {
144        BG_W::new(self, 7)
145    }
146}
147/**event generation register
148
149You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
150
151See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U5A5.html#TIM16:EGR)*/
152pub struct EGRrs;
153impl crate::RegisterSpec for EGRrs {
154    type Ux = u32;
155}
156///`write(|w| ..)` method takes [`egr::W`](W) writer structure
157impl crate::Writable for EGRrs {
158    type Safety = crate::Unsafe;
159}
160///`reset()` method sets EGR to value 0
161impl crate::Resettable for EGRrs {}
stm32u5/stm32u5a5/tim16/egr.rs

stm32u5/stm32u5a5/tim16/
egr.rs
