stm32u5/stm32u5a5/tim1/
egr.rs

1///Register `EGR` writer
2pub type W = crate::W<EGRrs>;
3/**Update generation
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum UG {
9    ///1: Re-initializes the timer counter and generates an update of the registers.
10    Update = 1,
11}
12impl From<UG> for bool {
13    #[inline(always)]
14    fn from(variant: UG) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `UG` writer - Update generation
19pub type UG_W<'a, REG> = crate::BitWriter<'a, REG, UG>;
20impl<'a, REG> UG_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Re-initializes the timer counter and generates an update of the registers.
25    #[inline(always)]
26    pub fn update(self) -> &'a mut crate::W<REG> {
27        self.variant(UG::Update)
28    }
29}
30/**Capture/compare %s generation
31
32Value on reset: 0*/
33#[cfg_attr(feature = "defmt", derive(defmt::Format))]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35pub enum CC1GW {
36    ///1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
37    Trigger = 1,
38}
39impl From<CC1GW> for bool {
40    #[inline(always)]
41    fn from(variant: CC1GW) -> Self {
42        variant as u8 != 0
43    }
44}
45///Field `CCG(1-4)` writer - Capture/compare %s generation
46pub type CCG_W<'a, REG> = crate::BitWriter<'a, REG, CC1GW>;
47impl<'a, REG> CCG_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    ///If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
52    #[inline(always)]
53    pub fn trigger(self) -> &'a mut crate::W<REG> {
54        self.variant(CC1GW::Trigger)
55    }
56}
57/**Capture/Compare control update generation
58
59Value on reset: 0*/
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum COMGW {
63    ///1: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
64    Trigger = 1,
65}
66impl From<COMGW> for bool {
67    #[inline(always)]
68    fn from(variant: COMGW) -> Self {
69        variant as u8 != 0
70    }
71}
72///Field `COMG` writer - Capture/Compare control update generation
73pub type COMG_W<'a, REG> = crate::BitWriter<'a, REG, COMGW>;
74impl<'a, REG> COMG_W<'a, REG>
75where
76    REG: crate::Writable + crate::RegisterSpec,
77{
78    ///When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
79    #[inline(always)]
80    pub fn trigger(self) -> &'a mut crate::W<REG> {
81        self.variant(COMGW::Trigger)
82    }
83}
84/**Trigger generation
85
86Value on reset: 0*/
87#[cfg_attr(feature = "defmt", derive(defmt::Format))]
88#[derive(Clone, Copy, Debug, PartialEq, Eq)]
89pub enum TGW {
90    ///1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
91    Trigger = 1,
92}
93impl From<TGW> for bool {
94    #[inline(always)]
95    fn from(variant: TGW) -> Self {
96        variant as u8 != 0
97    }
98}
99///Field `TG` writer - Trigger generation
100pub type TG_W<'a, REG> = crate::BitWriter<'a, REG, TGW>;
101impl<'a, REG> TG_W<'a, REG>
102where
103    REG: crate::Writable + crate::RegisterSpec,
104{
105    ///The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
106    #[inline(always)]
107    pub fn trigger(self) -> &'a mut crate::W<REG> {
108        self.variant(TGW::Trigger)
109    }
110}
111/**Break generation
112
113Value on reset: 0*/
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum BGW {
117    ///1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
118    Trigger = 1,
119}
120impl From<BGW> for bool {
121    #[inline(always)]
122    fn from(variant: BGW) -> Self {
123        variant as u8 != 0
124    }
125}
126///Field `BG` writer - Break generation
127pub type BG_W<'a, REG> = crate::BitWriter<'a, REG, BGW>;
128impl<'a, REG> BG_W<'a, REG>
129where
130    REG: crate::Writable + crate::RegisterSpec,
131{
132    ///A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
133    #[inline(always)]
134    pub fn trigger(self) -> &'a mut crate::W<REG> {
135        self.variant(BGW::Trigger)
136    }
137}
138/**Break 2 generation
139
140Value on reset: 0*/
141#[cfg_attr(feature = "defmt", derive(defmt::Format))]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum B2GW {
144    ///1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled
145    Trigger = 1,
146}
147impl From<B2GW> for bool {
148    #[inline(always)]
149    fn from(variant: B2GW) -> Self {
150        variant as u8 != 0
151    }
152}
153///Field `B2G` writer - Break 2 generation
154pub type B2G_W<'a, REG> = crate::BitWriter<'a, REG, B2GW>;
155impl<'a, REG> B2G_W<'a, REG>
156where
157    REG: crate::Writable + crate::RegisterSpec,
158{
159    ///A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled
160    #[inline(always)]
161    pub fn trigger(self) -> &'a mut crate::W<REG> {
162        self.variant(B2GW::Trigger)
163    }
164}
165impl core::fmt::Debug for crate::generic::Reg<EGRrs> {
166    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
167        write!(f, "(not readable)")
168    }
169}
170impl W {
171    ///Bit 0 - Update generation
172    #[inline(always)]
173    pub fn ug(&mut self) -> UG_W<EGRrs> {
174        UG_W::new(self, 0)
175    }
176    ///Capture/compare (1-4) generation
177    ///
178    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1G` field.</div>
179    #[inline(always)]
180    pub fn ccg(&mut self, n: u8) -> CCG_W<EGRrs> {
181        #[allow(clippy::no_effect)]
182        [(); 4][n as usize];
183        CCG_W::new(self, n + 1)
184    }
185    ///Bit 1 - Capture/compare 1 generation
186    #[inline(always)]
187    pub fn cc1g(&mut self) -> CCG_W<EGRrs> {
188        CCG_W::new(self, 1)
189    }
190    ///Bit 2 - Capture/compare 2 generation
191    #[inline(always)]
192    pub fn cc2g(&mut self) -> CCG_W<EGRrs> {
193        CCG_W::new(self, 2)
194    }
195    ///Bit 3 - Capture/compare 3 generation
196    #[inline(always)]
197    pub fn cc3g(&mut self) -> CCG_W<EGRrs> {
198        CCG_W::new(self, 3)
199    }
200    ///Bit 4 - Capture/compare 4 generation
201    #[inline(always)]
202    pub fn cc4g(&mut self) -> CCG_W<EGRrs> {
203        CCG_W::new(self, 4)
204    }
205    ///Bit 5 - Capture/Compare control update generation
206    #[inline(always)]
207    pub fn comg(&mut self) -> COMG_W<EGRrs> {
208        COMG_W::new(self, 5)
209    }
210    ///Bit 6 - Trigger generation
211    #[inline(always)]
212    pub fn tg(&mut self) -> TG_W<EGRrs> {
213        TG_W::new(self, 6)
214    }
215    ///Bit 7 - Break generation
216    #[inline(always)]
217    pub fn bg(&mut self) -> BG_W<EGRrs> {
218        BG_W::new(self, 7)
219    }
220    ///Bit 8 - Break 2 generation
221    #[inline(always)]
222    pub fn b2g(&mut self) -> B2G_W<EGRrs> {
223        B2G_W::new(self, 8)
224    }
225}
226/**event generation register
227
228You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
229
230See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U5A5.html#TIM1:EGR)*/
231pub struct EGRrs;
232impl crate::RegisterSpec for EGRrs {
233    type Ux = u32;
234}
235///`write(|w| ..)` method takes [`egr::W`](W) writer structure
236impl crate::Writable for EGRrs {
237    type Safety = crate::Unsafe;
238}
239///`reset()` method sets EGR to value 0
240impl crate::Resettable for EGRrs {}
stm32u5/stm32u5a5/tim1/egr.rs

stm32u5/stm32u5a5/tim1/
egr.rs
