stm32u5/stm32u5a5/rtc/
scr.rs

1///Register `SCR` writer
2pub type W = crate::W<SCRrs>;
3/**CALRAF
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum CALRAF {
9    ///1: Clear interrupt flag
10    Clear = 1,
11}
12impl From<CALRAF> for bool {
13    #[inline(always)]
14    fn from(variant: CALRAF) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `CALRAF` writer - CALRAF
19pub type CALRAF_W<'a, REG> = crate::BitWriter<'a, REG, CALRAF>;
20impl<'a, REG> CALRAF_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Clear interrupt flag
25    #[inline(always)]
26    pub fn clear(self) -> &'a mut crate::W<REG> {
27        self.variant(CALRAF::Clear)
28    }
29}
30///Field `CALRBF` writer - CALRBF
31pub use CALRAF_W as CALRBF_W;
32///Field `CWUTF` writer - CWUTF
33pub use CALRAF_W as CWUTF_W;
34///Field `CTSF` writer - CTSF
35pub use CALRAF_W as CTSF_W;
36///Field `CTSOVF` writer - CTSOVF
37pub use CALRAF_W as CTSOVF_W;
38///Field `CITSF` writer - CITSF
39pub use CALRAF_W as CITSF_W;
40///Field `CSSRUF` writer - CSSRUF
41pub use CALRAF_W as CSSRUF_W;
42impl core::fmt::Debug for crate::generic::Reg<SCRrs> {
43    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
44        write!(f, "(not readable)")
45    }
46}
47impl W {
48    ///Bit 0 - CALRAF
49    #[inline(always)]
50    pub fn calraf(&mut self) -> CALRAF_W<SCRrs> {
51        CALRAF_W::new(self, 0)
52    }
53    ///Bit 1 - CALRBF
54    #[inline(always)]
55    pub fn calrbf(&mut self) -> CALRBF_W<SCRrs> {
56        CALRBF_W::new(self, 1)
57    }
58    ///Bit 2 - CWUTF
59    #[inline(always)]
60    pub fn cwutf(&mut self) -> CWUTF_W<SCRrs> {
61        CWUTF_W::new(self, 2)
62    }
63    ///Bit 3 - CTSF
64    #[inline(always)]
65    pub fn ctsf(&mut self) -> CTSF_W<SCRrs> {
66        CTSF_W::new(self, 3)
67    }
68    ///Bit 4 - CTSOVF
69    #[inline(always)]
70    pub fn ctsovf(&mut self) -> CTSOVF_W<SCRrs> {
71        CTSOVF_W::new(self, 4)
72    }
73    ///Bit 5 - CITSF
74    #[inline(always)]
75    pub fn citsf(&mut self) -> CITSF_W<SCRrs> {
76        CITSF_W::new(self, 5)
77    }
78    ///Bit 6 - CSSRUF
79    #[inline(always)]
80    pub fn cssruf(&mut self) -> CSSRUF_W<SCRrs> {
81        CSSRUF_W::new(self, 6)
82    }
83}
84/**RTC status clear register
85
86You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
87
88See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U5A5.html#RTC:SCR)*/
89pub struct SCRrs;
90impl crate::RegisterSpec for SCRrs {
91    type Ux = u32;
92}
93///`write(|w| ..)` method takes [`scr::W`](W) writer structure
94impl crate::Writable for SCRrs {
95    type Safety = crate::Unsafe;
96}
97///`reset()` method sets SCR to value 0
98impl crate::Resettable for SCRrs {}
stm32u5/stm32u5a5/rtc/scr.rs

stm32u5/stm32u5a5/rtc/
scr.rs
