stm32u5/stm32u5a5/gtzc2_tzic/
fcr2.rs

1///Register `FCR2` writer
2pub type W = crate::W<FCR2rs>;
3///Field `CSYSCFGF` writer - clear the illegal access flag for SYSCFG
4pub type CSYSCFGF_W<'a, REG> = crate::BitWriter<'a, REG>;
5///Field `CRTCF` writer - clear the illegal access flag for RTC
6pub type CRTCF_W<'a, REG> = crate::BitWriter<'a, REG>;
7///Field `CTAMPF` writer - clear the illegal access flag for TAMP
8pub type CTAMPF_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `CPWRF` writer - clear the illegal access flag for PWR
10pub type CPWRF_W<'a, REG> = crate::BitWriter<'a, REG>;
11///Field `CRCCF` writer - clear the illegal access flag for RCC
12pub type CRCCF_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `CLPDMA1F` writer - clear the illegal access flag for LPDMA
14pub type CLPDMA1F_W<'a, REG> = crate::BitWriter<'a, REG>;
15///Field `CEXTIF` writer - clear the illegal access flag for EXTI
16pub type CEXTIF_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `CTZSC2F` writer - clear the illegal access flag for GTZC2 TZSC registers
18pub type CTZSC2F_W<'a, REG> = crate::BitWriter<'a, REG>;
19///Field `CTZIC2F` writer - clear the illegal access flag for GTZC2 TZIC registers
20pub type CTZIC2F_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `CSRAM4F` writer - clear the illegal access flag for SRAM4
22pub type CSRAM4F_W<'a, REG> = crate::BitWriter<'a, REG>;
23///Field `CMPCBB4_REGF` writer - clear the illegal access flag for MPCBB4 registers
24pub type CMPCBB4_REGF_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl core::fmt::Debug for crate::generic::Reg<FCR2rs> {
26    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
27        write!(f, "(not readable)")
28    }
29}
30impl W {
31    ///Bit 0 - clear the illegal access flag for SYSCFG
32    #[inline(always)]
33    pub fn csyscfgf(&mut self) -> CSYSCFGF_W<FCR2rs> {
34        CSYSCFGF_W::new(self, 0)
35    }
36    ///Bit 1 - clear the illegal access flag for RTC
37    #[inline(always)]
38    pub fn crtcf(&mut self) -> CRTCF_W<FCR2rs> {
39        CRTCF_W::new(self, 1)
40    }
41    ///Bit 2 - clear the illegal access flag for TAMP
42    #[inline(always)]
43    pub fn ctampf(&mut self) -> CTAMPF_W<FCR2rs> {
44        CTAMPF_W::new(self, 2)
45    }
46    ///Bit 3 - clear the illegal access flag for PWR
47    #[inline(always)]
48    pub fn cpwrf(&mut self) -> CPWRF_W<FCR2rs> {
49        CPWRF_W::new(self, 3)
50    }
51    ///Bit 4 - clear the illegal access flag for RCC
52    #[inline(always)]
53    pub fn crccf(&mut self) -> CRCCF_W<FCR2rs> {
54        CRCCF_W::new(self, 4)
55    }
56    ///Bit 5 - clear the illegal access flag for LPDMA
57    #[inline(always)]
58    pub fn clpdma1f(&mut self) -> CLPDMA1F_W<FCR2rs> {
59        CLPDMA1F_W::new(self, 5)
60    }
61    ///Bit 6 - clear the illegal access flag for EXTI
62    #[inline(always)]
63    pub fn cextif(&mut self) -> CEXTIF_W<FCR2rs> {
64        CEXTIF_W::new(self, 6)
65    }
66    ///Bit 14 - clear the illegal access flag for GTZC2 TZSC registers
67    #[inline(always)]
68    pub fn ctzsc2f(&mut self) -> CTZSC2F_W<FCR2rs> {
69        CTZSC2F_W::new(self, 14)
70    }
71    ///Bit 15 - clear the illegal access flag for GTZC2 TZIC registers
72    #[inline(always)]
73    pub fn ctzic2f(&mut self) -> CTZIC2F_W<FCR2rs> {
74        CTZIC2F_W::new(self, 15)
75    }
76    ///Bit 24 - clear the illegal access flag for SRAM4
77    #[inline(always)]
78    pub fn csram4f(&mut self) -> CSRAM4F_W<FCR2rs> {
79        CSRAM4F_W::new(self, 24)
80    }
81    ///Bit 25 - clear the illegal access flag for MPCBB4 registers
82    #[inline(always)]
83    pub fn cmpcbb4_regf(&mut self) -> CMPCBB4_REGF_W<FCR2rs> {
84        CMPCBB4_REGF_W::new(self, 25)
85    }
86}
87/**TZIC flag clear register 2
88
89You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
90
91See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U5A5.html#GTZC2_TZIC:FCR2)*/
92pub struct FCR2rs;
93impl crate::RegisterSpec for FCR2rs {
94    type Ux = u32;
95}
96///`write(|w| ..)` method takes [`fcr2::W`](W) writer structure
97impl crate::Writable for FCR2rs {
98    type Safety = crate::Unsafe;
99}
100///`reset()` method sets FCR2 to value 0
101impl crate::Resettable for FCR2rs {}
stm32u5/stm32u5a5/gtzc2_tzic/fcr2.rs

stm32u5/stm32u5a5/gtzc2_tzic/
fcr2.rs
