stm32u5/stm32u585/lpuart1/
rqr.rs

1///Register `RQR` writer
2pub type W = crate::W<RQRrs>;
3///Field `SBKRQ` writer - Send break request
4pub type SBKRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
5///Field `MMRQ` writer - Mute mode request
6pub type MMRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
7///Field `RXFRQ` writer - Receive data flush request
8pub type RXFRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `TXFRQ` writer - TXFRQ
10pub type TXFRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
11impl core::fmt::Debug for crate::generic::Reg<RQRrs> {
12    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
13        write!(f, "(not readable)")
14    }
15}
16impl W {
17    ///Bit 1 - Send break request
18    #[inline(always)]
19    pub fn sbkrq(&mut self) -> SBKRQ_W<RQRrs> {
20        SBKRQ_W::new(self, 1)
21    }
22    ///Bit 2 - Mute mode request
23    #[inline(always)]
24    pub fn mmrq(&mut self) -> MMRQ_W<RQRrs> {
25        MMRQ_W::new(self, 2)
26    }
27    ///Bit 3 - Receive data flush request
28    #[inline(always)]
29    pub fn rxfrq(&mut self) -> RXFRQ_W<RQRrs> {
30        RXFRQ_W::new(self, 3)
31    }
32    ///Bit 4 - TXFRQ
33    #[inline(always)]
34    pub fn txfrq(&mut self) -> TXFRQ_W<RQRrs> {
35        TXFRQ_W::new(self, 4)
36    }
37}
38/**Request register
39
40You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rqr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
41
42See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#LPUART1:RQR)*/
43pub struct RQRrs;
44impl crate::RegisterSpec for RQRrs {
45    type Ux = u32;
46}
47///`write(|w| ..)` method takes [`rqr::W`](W) writer structure
48impl crate::Writable for RQRrs {
49    type Safety = crate::Unsafe;
50}
51///`reset()` method sets RQR to value 0
52impl crate::Resettable for RQRrs {}
stm32u5/stm32u585/lpuart1/rqr.rs

stm32u5/stm32u585/lpuart1/
rqr.rs
