stm32u5/stm32u585/gtzc1_tzic/
fcr2.rs

1///Register `FCR2` writer
2pub type W = crate::W<FCR2rs>;
3///Field `CTIM1F` writer - clear the illegal access flag for TIM1
4pub type CTIM1F_W<'a, REG> = crate::BitWriter<'a, REG>;
5///Field `CSPI1F` writer - clear the illegal access flag for SPI1
6pub type CSPI1F_W<'a, REG> = crate::BitWriter<'a, REG>;
7///Field `CTIM8F` writer - clear the illegal access flag for TIM8
8pub type CTIM8F_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `CUSART1F` writer - clear the illegal access flag for USART1
10pub type CUSART1F_W<'a, REG> = crate::BitWriter<'a, REG>;
11///Field `CTIM15F` writer - clear the illegal access flag for TIM5
12pub type CTIM15F_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `CTIM16F` writer - clear the illegal access flag for TIM6
14pub type CTIM16F_W<'a, REG> = crate::BitWriter<'a, REG>;
15///Field `CTIM17F` writer - clear the illegal access flag for TIM7
16pub type CTIM17F_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `CSAI1F` writer - clear the illegal access flag for SAI1
18pub type CSAI1F_W<'a, REG> = crate::BitWriter<'a, REG>;
19///Field `CSAI2F` writer - clear the illegal access flag for SAI2
20pub type CSAI2F_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl core::fmt::Debug for crate::generic::Reg<FCR2rs> {
22    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
23        write!(f, "(not readable)")
24    }
25}
26impl W {
27    ///Bit 0 - clear the illegal access flag for TIM1
28    #[inline(always)]
29    pub fn ctim1f(&mut self) -> CTIM1F_W<FCR2rs> {
30        CTIM1F_W::new(self, 0)
31    }
32    ///Bit 1 - clear the illegal access flag for SPI1
33    #[inline(always)]
34    pub fn cspi1f(&mut self) -> CSPI1F_W<FCR2rs> {
35        CSPI1F_W::new(self, 1)
36    }
37    ///Bit 2 - clear the illegal access flag for TIM8
38    #[inline(always)]
39    pub fn ctim8f(&mut self) -> CTIM8F_W<FCR2rs> {
40        CTIM8F_W::new(self, 2)
41    }
42    ///Bit 3 - clear the illegal access flag for USART1
43    #[inline(always)]
44    pub fn cusart1f(&mut self) -> CUSART1F_W<FCR2rs> {
45        CUSART1F_W::new(self, 3)
46    }
47    ///Bit 4 - clear the illegal access flag for TIM5
48    #[inline(always)]
49    pub fn ctim15f(&mut self) -> CTIM15F_W<FCR2rs> {
50        CTIM15F_W::new(self, 4)
51    }
52    ///Bit 5 - clear the illegal access flag for TIM6
53    #[inline(always)]
54    pub fn ctim16f(&mut self) -> CTIM16F_W<FCR2rs> {
55        CTIM16F_W::new(self, 5)
56    }
57    ///Bit 6 - clear the illegal access flag for TIM7
58    #[inline(always)]
59    pub fn ctim17f(&mut self) -> CTIM17F_W<FCR2rs> {
60        CTIM17F_W::new(self, 6)
61    }
62    ///Bit 7 - clear the illegal access flag for SAI1
63    #[inline(always)]
64    pub fn csai1f(&mut self) -> CSAI1F_W<FCR2rs> {
65        CSAI1F_W::new(self, 7)
66    }
67    ///Bit 8 - clear the illegal access flag for SAI2
68    #[inline(always)]
69    pub fn csai2f(&mut self) -> CSAI2F_W<FCR2rs> {
70        CSAI2F_W::new(self, 8)
71    }
72}
73/**TZIC flag clear register 2
74
75You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
76
77See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#GTZC1_TZIC:FCR2)*/
78pub struct FCR2rs;
79impl crate::RegisterSpec for FCR2rs {
80    type Ux = u32;
81}
82///`write(|w| ..)` method takes [`fcr2::W`](W) writer structure
83impl crate::Writable for FCR2rs {
84    type Safety = crate::Unsafe;
85}
86///`reset()` method sets FCR2 to value 0
87impl crate::Resettable for FCR2rs {}
stm32u5/stm32u585/gtzc1_tzic/fcr2.rs

stm32u5/stm32u585/gtzc1_tzic/
fcr2.rs
