stm32u5/stm32u575/spi1/
txdr.rs

1///Register `TXDR` writer
2pub type W = crate::W<TXDRrs>;
3///Field `TXDR` writer - transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFIFO. Note: data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is written by single access. halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be written by single access. word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be written by single access. Write access of this register less than the configured data size is forbidden.
4pub type TXDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32, crate::Safe>;
5impl core::fmt::Debug for crate::generic::Reg<TXDRrs> {
6    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
7        write!(f, "(not readable)")
8    }
9}
10impl W {
11    ///Bits 0:31 - transmit data register The register serves as an interface with TxFIFO. A write to it accesses TxFIFO. Note: data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. Note: DR can be accessed byte-wise (8-bit access): in this case only one data-byte is written by single access. halfword-wise (16 bit access) in this case 2 data-bytes or 1 halfword-data can be written by single access. word-wise (32 bit access). In this case 4 data-bytes or 2 halfword-data or word-data can be written by single access. Write access of this register less than the configured data size is forbidden.
12    #[inline(always)]
13    pub fn txdr(&mut self) -> TXDR_W<TXDRrs> {
14        TXDR_W::new(self, 0)
15    }
16}
17/**
18
19You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
20
21See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U575.html#SPI1:TXDR)*/
22pub struct TXDRrs;
23impl crate::RegisterSpec for TXDRrs {
24    type Ux = u32;
25}
26///`write(|w| ..)` method takes [`txdr::W`](W) writer structure
27impl crate::Writable for TXDRrs {
28    type Safety = crate::Safe;
29}
30///`reset()` method sets TXDR to value 0
31impl crate::Resettable for TXDRrs {}
stm32u5/stm32u575/spi1/txdr.rs

stm32u5/stm32u575/spi1/
txdr.rs
