stm32u5/stm32u575/spi1/
ifcr.rs

1///Register `IFCR` writer
2pub type W = crate::W<IFCRrs>;
3/**end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum EOTCW {
9    ///1: Clear interrupt flag
10    Clear = 1,
11}
12impl From<EOTCW> for bool {
13    #[inline(always)]
14    fn from(variant: EOTCW) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `EOTC` writer - end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register
19pub type EOTC_W<'a, REG> = crate::BitWriter1C<'a, REG, EOTCW>;
20impl<'a, REG> EOTC_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Clear interrupt flag
25    #[inline(always)]
26    pub fn clear(self) -> &'a mut crate::W<REG> {
27        self.variant(EOTCW::Clear)
28    }
29}
30///Field `TXTFC` writer - transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR register
31pub use EOTC_W as TXTFC_W;
32///Field `UDRC` writer - underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register
33pub use EOTC_W as UDRC_W;
34///Field `OVRC` writer - overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register
35pub use EOTC_W as OVRC_W;
36///Field `CRCEC` writer - CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register
37pub use EOTC_W as CRCEC_W;
38///Field `TIFREC` writer - TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register
39pub use EOTC_W as TIFREC_W;
40///Field `MODFC` writer - mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register
41pub use EOTC_W as MODFC_W;
42///Field `SUSPC` writer - SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register
43pub use EOTC_W as SUSPC_W;
44impl core::fmt::Debug for crate::generic::Reg<IFCRrs> {
45    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
46        write!(f, "(not readable)")
47    }
48}
49impl W {
50    ///Bit 3 - end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register
51    #[inline(always)]
52    pub fn eotc(&mut self) -> EOTC_W<IFCRrs> {
53        EOTC_W::new(self, 3)
54    }
55    ///Bit 4 - transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR register
56    #[inline(always)]
57    pub fn txtfc(&mut self) -> TXTFC_W<IFCRrs> {
58        TXTFC_W::new(self, 4)
59    }
60    ///Bit 5 - underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register
61    #[inline(always)]
62    pub fn udrc(&mut self) -> UDRC_W<IFCRrs> {
63        UDRC_W::new(self, 5)
64    }
65    ///Bit 6 - overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register
66    #[inline(always)]
67    pub fn ovrc(&mut self) -> OVRC_W<IFCRrs> {
68        OVRC_W::new(self, 6)
69    }
70    ///Bit 7 - CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register
71    #[inline(always)]
72    pub fn crcec(&mut self) -> CRCEC_W<IFCRrs> {
73        CRCEC_W::new(self, 7)
74    }
75    ///Bit 8 - TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register
76    #[inline(always)]
77    pub fn tifrec(&mut self) -> TIFREC_W<IFCRrs> {
78        TIFREC_W::new(self, 8)
79    }
80    ///Bit 9 - mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register
81    #[inline(always)]
82    pub fn modfc(&mut self) -> MODFC_W<IFCRrs> {
83        MODFC_W::new(self, 9)
84    }
85    ///Bit 11 - SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register
86    #[inline(always)]
87    pub fn suspc(&mut self) -> SUSPC_W<IFCRrs> {
88        SUSPC_W::new(self, 11)
89    }
90}
91/**
92
93You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
94
95See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U575.html#SPI1:IFCR)*/
96pub struct IFCRrs;
97impl crate::RegisterSpec for IFCRrs {
98    type Ux = u32;
99}
100///`write(|w| ..)` method takes [`ifcr::W`](W) writer structure
101impl crate::Writable for IFCRrs {
102    type Safety = crate::Unsafe;
103    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0bf8;
104}
105///`reset()` method sets IFCR to value 0
106impl crate::Resettable for IFCRrs {}
stm32u5/stm32u575/spi1/ifcr.rs

stm32u5/stm32u575/spi1/
ifcr.rs
