stm32u5/stm32u545/pssi/
icr.rs

1///Register `ICR` writer
2pub type W = crate::W<ICRrs>;
3/**OVR_ISC
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum OVR_ISC {
9    ///1: Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS
10    Clear = 1,
11}
12impl From<OVR_ISC> for bool {
13    #[inline(always)]
14    fn from(variant: OVR_ISC) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `OVR_ISC` writer - OVR_ISC
19pub type OVR_ISC_W<'a, REG> = crate::BitWriter<'a, REG, OVR_ISC>;
20impl<'a, REG> OVR_ISC_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS
25    #[inline(always)]
26    pub fn clear(self) -> &'a mut crate::W<REG> {
27        self.variant(OVR_ISC::Clear)
28    }
29}
30impl core::fmt::Debug for crate::generic::Reg<ICRrs> {
31    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
32        write!(f, "(not readable)")
33    }
34}
35impl W {
36    ///Bit 1 - OVR_ISC
37    #[inline(always)]
38    pub fn ovr_isc(&mut self) -> OVR_ISC_W<ICRrs> {
39        OVR_ISC_W::new(self, 1)
40    }
41}
42/**PSSI interrupt clear register
43
44You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
45
46See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U545.html#PSSI:ICR)*/
47pub struct ICRrs;
48impl crate::RegisterSpec for ICRrs {
49    type Ux = u32;
50}
51///`write(|w| ..)` method takes [`icr::W`](W) writer structure
52impl crate::Writable for ICRrs {
53    type Safety = crate::Unsafe;
54}
55///`reset()` method sets ICR to value 0
56impl crate::Resettable for ICRrs {}
stm32u5/stm32u545/pssi/icr.rs

stm32u5/stm32u545/pssi/
icr.rs
