stm32u5/stm32u545/octospi1/
tcr.rs

1///Register `TCR` reader
2pub type R = crate::R<TCRrs>;
3///Register `TCR` writer
4pub type W = crate::W<TCRrs>;
5///Field `DCYC` reader - Number of dummy cycles
6pub type DCYC_R = crate::FieldReader;
7///Field `DCYC` writer - Number of dummy cycles
8pub type DCYC_W<'a, REG> = crate::FieldWriter<'a, REG, 5, u8, crate::Safe>;
9/**Delay hold quarter cycle
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum DHQC {
15    ///0: No delay hold
16    NoDelay = 0,
17    ///1: 1/4 cycle hold
18    QuarterCycleHold = 1,
19}
20impl From<DHQC> for bool {
21    #[inline(always)]
22    fn from(variant: DHQC) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `DHQC` reader - Delay hold quarter cycle
27pub type DHQC_R = crate::BitReader<DHQC>;
28impl DHQC_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> DHQC {
32        match self.bits {
33            false => DHQC::NoDelay,
34            true => DHQC::QuarterCycleHold,
35        }
36    }
37    ///No delay hold
38    #[inline(always)]
39    pub fn is_no_delay(&self) -> bool {
40        *self == DHQC::NoDelay
41    }
42    ///1/4 cycle hold
43    #[inline(always)]
44    pub fn is_quarter_cycle_hold(&self) -> bool {
45        *self == DHQC::QuarterCycleHold
46    }
47}
48///Field `DHQC` writer - Delay hold quarter cycle
49pub type DHQC_W<'a, REG> = crate::BitWriter<'a, REG, DHQC>;
50impl<'a, REG> DHQC_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    ///No delay hold
55    #[inline(always)]
56    pub fn no_delay(self) -> &'a mut crate::W<REG> {
57        self.variant(DHQC::NoDelay)
58    }
59    ///1/4 cycle hold
60    #[inline(always)]
61    pub fn quarter_cycle_hold(self) -> &'a mut crate::W<REG> {
62        self.variant(DHQC::QuarterCycleHold)
63    }
64}
65/**Sample shift
66
67Value on reset: 0*/
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum SSHIFT {
71    ///0: No shift
72    NoShift = 0,
73    ///1: 1/2 cycle shift
74    HalfCycleShift = 1,
75}
76impl From<SSHIFT> for bool {
77    #[inline(always)]
78    fn from(variant: SSHIFT) -> Self {
79        variant as u8 != 0
80    }
81}
82///Field `SSHIFT` reader - Sample shift
83pub type SSHIFT_R = crate::BitReader<SSHIFT>;
84impl SSHIFT_R {
85    ///Get enumerated values variant
86    #[inline(always)]
87    pub const fn variant(&self) -> SSHIFT {
88        match self.bits {
89            false => SSHIFT::NoShift,
90            true => SSHIFT::HalfCycleShift,
91        }
92    }
93    ///No shift
94    #[inline(always)]
95    pub fn is_no_shift(&self) -> bool {
96        *self == SSHIFT::NoShift
97    }
98    ///1/2 cycle shift
99    #[inline(always)]
100    pub fn is_half_cycle_shift(&self) -> bool {
101        *self == SSHIFT::HalfCycleShift
102    }
103}
104///Field `SSHIFT` writer - Sample shift
105pub type SSHIFT_W<'a, REG> = crate::BitWriter<'a, REG, SSHIFT>;
106impl<'a, REG> SSHIFT_W<'a, REG>
107where
108    REG: crate::Writable + crate::RegisterSpec,
109{
110    ///No shift
111    #[inline(always)]
112    pub fn no_shift(self) -> &'a mut crate::W<REG> {
113        self.variant(SSHIFT::NoShift)
114    }
115    ///1/2 cycle shift
116    #[inline(always)]
117    pub fn half_cycle_shift(self) -> &'a mut crate::W<REG> {
118        self.variant(SSHIFT::HalfCycleShift)
119    }
120}
121impl R {
122    ///Bits 0:4 - Number of dummy cycles
123    #[inline(always)]
124    pub fn dcyc(&self) -> DCYC_R {
125        DCYC_R::new((self.bits & 0x1f) as u8)
126    }
127    ///Bit 28 - Delay hold quarter cycle
128    #[inline(always)]
129    pub fn dhqc(&self) -> DHQC_R {
130        DHQC_R::new(((self.bits >> 28) & 1) != 0)
131    }
132    ///Bit 30 - Sample shift
133    #[inline(always)]
134    pub fn sshift(&self) -> SSHIFT_R {
135        SSHIFT_R::new(((self.bits >> 30) & 1) != 0)
136    }
137}
138impl core::fmt::Debug for R {
139    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
140        f.debug_struct("TCR")
141            .field("dcyc", &self.dcyc())
142            .field("dhqc", &self.dhqc())
143            .field("sshift", &self.sshift())
144            .finish()
145    }
146}
147impl W {
148    ///Bits 0:4 - Number of dummy cycles
149    #[inline(always)]
150    pub fn dcyc(&mut self) -> DCYC_W<TCRrs> {
151        DCYC_W::new(self, 0)
152    }
153    ///Bit 28 - Delay hold quarter cycle
154    #[inline(always)]
155    pub fn dhqc(&mut self) -> DHQC_W<TCRrs> {
156        DHQC_W::new(self, 28)
157    }
158    ///Bit 30 - Sample shift
159    #[inline(always)]
160    pub fn sshift(&mut self) -> SSHIFT_W<TCRrs> {
161        SSHIFT_W::new(self, 30)
162    }
163}
164/**timing configuration register
165
166You can [`read`](crate::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U545.html#OCTOSPI1:TCR)*/
169pub struct TCRrs;
170impl crate::RegisterSpec for TCRrs {
171    type Ux = u32;
172}
173///`read()` method returns [`tcr::R`](R) reader structure
174impl crate::Readable for TCRrs {}
175///`write(|w| ..)` method takes [`tcr::W`](W) writer structure
176impl crate::Writable for TCRrs {
177    type Safety = crate::Unsafe;
178}
179///`reset()` method sets TCR to value 0
180impl crate::Resettable for TCRrs {}
stm32u5/stm32u545/octospi1/tcr.rs

stm32u5/stm32u545/octospi1/
tcr.rs
