stm32u5/stm32u545/lpgpio1/
bsrr.rs

1///Register `BSRR` writer
2pub type W = crate::W<BSRRrs>;
3///Field `BS(0-15)` writer - BS%s
4pub type BS_W<'a, REG> = crate::BitWriter<'a, REG>;
5///Field `BR(0-15)` writer - BR%s
6pub type BR_W<'a, REG> = crate::BitWriter<'a, REG>;
7impl core::fmt::Debug for crate::generic::Reg<BSRRrs> {
8    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
9        write!(f, "(not readable)")
10    }
11}
12impl W {
13    ///BS(0-15)
14    ///
15    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `BS0` field.</div>
16    #[inline(always)]
17    pub fn bs(&mut self, n: u8) -> BS_W<BSRRrs> {
18        #[allow(clippy::no_effect)]
19        [(); 16][n as usize];
20        BS_W::new(self, n)
21    }
22    ///Bit 0 - BS0
23    #[inline(always)]
24    pub fn bs0(&mut self) -> BS_W<BSRRrs> {
25        BS_W::new(self, 0)
26    }
27    ///Bit 1 - BS1
28    #[inline(always)]
29    pub fn bs1(&mut self) -> BS_W<BSRRrs> {
30        BS_W::new(self, 1)
31    }
32    ///Bit 2 - BS2
33    #[inline(always)]
34    pub fn bs2(&mut self) -> BS_W<BSRRrs> {
35        BS_W::new(self, 2)
36    }
37    ///Bit 3 - BS3
38    #[inline(always)]
39    pub fn bs3(&mut self) -> BS_W<BSRRrs> {
40        BS_W::new(self, 3)
41    }
42    ///Bit 4 - BS4
43    #[inline(always)]
44    pub fn bs4(&mut self) -> BS_W<BSRRrs> {
45        BS_W::new(self, 4)
46    }
47    ///Bit 5 - BS5
48    #[inline(always)]
49    pub fn bs5(&mut self) -> BS_W<BSRRrs> {
50        BS_W::new(self, 5)
51    }
52    ///Bit 6 - BS6
53    #[inline(always)]
54    pub fn bs6(&mut self) -> BS_W<BSRRrs> {
55        BS_W::new(self, 6)
56    }
57    ///Bit 7 - BS7
58    #[inline(always)]
59    pub fn bs7(&mut self) -> BS_W<BSRRrs> {
60        BS_W::new(self, 7)
61    }
62    ///Bit 8 - BS8
63    #[inline(always)]
64    pub fn bs8(&mut self) -> BS_W<BSRRrs> {
65        BS_W::new(self, 8)
66    }
67    ///Bit 9 - BS9
68    #[inline(always)]
69    pub fn bs9(&mut self) -> BS_W<BSRRrs> {
70        BS_W::new(self, 9)
71    }
72    ///Bit 10 - BS10
73    #[inline(always)]
74    pub fn bs10(&mut self) -> BS_W<BSRRrs> {
75        BS_W::new(self, 10)
76    }
77    ///Bit 11 - BS11
78    #[inline(always)]
79    pub fn bs11(&mut self) -> BS_W<BSRRrs> {
80        BS_W::new(self, 11)
81    }
82    ///Bit 12 - BS12
83    #[inline(always)]
84    pub fn bs12(&mut self) -> BS_W<BSRRrs> {
85        BS_W::new(self, 12)
86    }
87    ///Bit 13 - BS13
88    #[inline(always)]
89    pub fn bs13(&mut self) -> BS_W<BSRRrs> {
90        BS_W::new(self, 13)
91    }
92    ///Bit 14 - BS14
93    #[inline(always)]
94    pub fn bs14(&mut self) -> BS_W<BSRRrs> {
95        BS_W::new(self, 14)
96    }
97    ///Bit 15 - BS15
98    #[inline(always)]
99    pub fn bs15(&mut self) -> BS_W<BSRRrs> {
100        BS_W::new(self, 15)
101    }
102    ///BR(0-15)
103    ///
104    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `BR0` field.</div>
105    #[inline(always)]
106    pub fn br(&mut self, n: u8) -> BR_W<BSRRrs> {
107        #[allow(clippy::no_effect)]
108        [(); 16][n as usize];
109        BR_W::new(self, n + 16)
110    }
111    ///Bit 16 - BR0
112    #[inline(always)]
113    pub fn br0(&mut self) -> BR_W<BSRRrs> {
114        BR_W::new(self, 16)
115    }
116    ///Bit 17 - BR1
117    #[inline(always)]
118    pub fn br1(&mut self) -> BR_W<BSRRrs> {
119        BR_W::new(self, 17)
120    }
121    ///Bit 18 - BR2
122    #[inline(always)]
123    pub fn br2(&mut self) -> BR_W<BSRRrs> {
124        BR_W::new(self, 18)
125    }
126    ///Bit 19 - BR3
127    #[inline(always)]
128    pub fn br3(&mut self) -> BR_W<BSRRrs> {
129        BR_W::new(self, 19)
130    }
131    ///Bit 20 - BR4
132    #[inline(always)]
133    pub fn br4(&mut self) -> BR_W<BSRRrs> {
134        BR_W::new(self, 20)
135    }
136    ///Bit 21 - BR5
137    #[inline(always)]
138    pub fn br5(&mut self) -> BR_W<BSRRrs> {
139        BR_W::new(self, 21)
140    }
141    ///Bit 22 - BR6
142    #[inline(always)]
143    pub fn br6(&mut self) -> BR_W<BSRRrs> {
144        BR_W::new(self, 22)
145    }
146    ///Bit 23 - BR7
147    #[inline(always)]
148    pub fn br7(&mut self) -> BR_W<BSRRrs> {
149        BR_W::new(self, 23)
150    }
151    ///Bit 24 - BR8
152    #[inline(always)]
153    pub fn br8(&mut self) -> BR_W<BSRRrs> {
154        BR_W::new(self, 24)
155    }
156    ///Bit 25 - BR9
157    #[inline(always)]
158    pub fn br9(&mut self) -> BR_W<BSRRrs> {
159        BR_W::new(self, 25)
160    }
161    ///Bit 26 - BR10
162    #[inline(always)]
163    pub fn br10(&mut self) -> BR_W<BSRRrs> {
164        BR_W::new(self, 26)
165    }
166    ///Bit 27 - BR11
167    #[inline(always)]
168    pub fn br11(&mut self) -> BR_W<BSRRrs> {
169        BR_W::new(self, 27)
170    }
171    ///Bit 28 - BR12
172    #[inline(always)]
173    pub fn br12(&mut self) -> BR_W<BSRRrs> {
174        BR_W::new(self, 28)
175    }
176    ///Bit 29 - BR13
177    #[inline(always)]
178    pub fn br13(&mut self) -> BR_W<BSRRrs> {
179        BR_W::new(self, 29)
180    }
181    ///Bit 30 - BR14
182    #[inline(always)]
183    pub fn br14(&mut self) -> BR_W<BSRRrs> {
184        BR_W::new(self, 30)
185    }
186    ///Bit 31 - BR15
187    #[inline(always)]
188    pub fn br15(&mut self) -> BR_W<BSRRrs> {
189        BR_W::new(self, 31)
190    }
191}
192/**LPGPIO port bit set/reset register
193
194You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bsrr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
195
196See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U545.html#LPGPIO1:BSRR)*/
197pub struct BSRRrs;
198impl crate::RegisterSpec for BSRRrs {
199    type Ux = u32;
200}
201///`write(|w| ..)` method takes [`bsrr::W`](W) writer structure
202impl crate::Writable for BSRRrs {
203    type Safety = crate::Unsafe;
204}
205///`reset()` method sets BSRR to value 0
206impl crate::Resettable for BSRRrs {}
stm32u5/stm32u545/lpgpio1/bsrr.rs

stm32u5/stm32u545/lpgpio1/
bsrr.rs
