stm32u5/stm32u595/gtzc2_tzic/
fcr1.rs

1///Register `FCR1` writer
2pub type W = crate::W<FCR1rs>;
3///Field `CSPI3F` writer - clear the illegal access flag for SPI3
4pub type CSPI3F_W<'a, REG> = crate::BitWriter<'a, REG>;
5///Field `CLPUART1F` writer - clear the illegal access flag for LPUART1
6pub type CLPUART1F_W<'a, REG> = crate::BitWriter<'a, REG>;
7///Field `CI2C3F` writer - clear the illegal access flag for I2C3
8pub type CI2C3F_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `CLPTIM1F` writer - clear the illegal access flag for LPTIM1
10pub type CLPTIM1F_W<'a, REG> = crate::BitWriter<'a, REG>;
11///Field `CLPTIM3F` writer - clear the illegal access flag for LPTIM3
12pub type CLPTIM3F_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `CLPTIM4F` writer - clear the illegal access flag for LPTIM4
14pub type CLPTIM4F_W<'a, REG> = crate::BitWriter<'a, REG>;
15///Field `COPAMPF` writer - clear the illegal access flag for OPAMP
16pub type COPAMPF_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `CCOMPF` writer - clear the illegal access flag for COMP
18pub type CCOMPF_W<'a, REG> = crate::BitWriter<'a, REG>;
19///Field `CADC2F` writer - clear the illegal access flag for ADC2
20pub type CADC2F_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `CVREFBUFF` writer - clear the illegal access flag for VREFBUF
22pub type CVREFBUFF_W<'a, REG> = crate::BitWriter<'a, REG>;
23///Field `CDAC1F` writer - clear the illegal access flag for DAC1
24pub type CDAC1F_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `CADF1F` writer - clear the illegal access flag for ADF1
26pub type CADF1F_W<'a, REG> = crate::BitWriter<'a, REG>;
27impl core::fmt::Debug for crate::generic::Reg<FCR1rs> {
28    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
29        write!(f, "(not readable)")
30    }
31}
32impl W {
33    ///Bit 0 - clear the illegal access flag for SPI3
34    #[inline(always)]
35    pub fn cspi3f(&mut self) -> CSPI3F_W<FCR1rs> {
36        CSPI3F_W::new(self, 0)
37    }
38    ///Bit 1 - clear the illegal access flag for LPUART1
39    #[inline(always)]
40    pub fn clpuart1f(&mut self) -> CLPUART1F_W<FCR1rs> {
41        CLPUART1F_W::new(self, 1)
42    }
43    ///Bit 2 - clear the illegal access flag for I2C3
44    #[inline(always)]
45    pub fn ci2c3f(&mut self) -> CI2C3F_W<FCR1rs> {
46        CI2C3F_W::new(self, 2)
47    }
48    ///Bit 3 - clear the illegal access flag for LPTIM1
49    #[inline(always)]
50    pub fn clptim1f(&mut self) -> CLPTIM1F_W<FCR1rs> {
51        CLPTIM1F_W::new(self, 3)
52    }
53    ///Bit 4 - clear the illegal access flag for LPTIM3
54    #[inline(always)]
55    pub fn clptim3f(&mut self) -> CLPTIM3F_W<FCR1rs> {
56        CLPTIM3F_W::new(self, 4)
57    }
58    ///Bit 5 - clear the illegal access flag for LPTIM4
59    #[inline(always)]
60    pub fn clptim4f(&mut self) -> CLPTIM4F_W<FCR1rs> {
61        CLPTIM4F_W::new(self, 5)
62    }
63    ///Bit 6 - clear the illegal access flag for OPAMP
64    #[inline(always)]
65    pub fn copampf(&mut self) -> COPAMPF_W<FCR1rs> {
66        COPAMPF_W::new(self, 6)
67    }
68    ///Bit 7 - clear the illegal access flag for COMP
69    #[inline(always)]
70    pub fn ccompf(&mut self) -> CCOMPF_W<FCR1rs> {
71        CCOMPF_W::new(self, 7)
72    }
73    ///Bit 8 - clear the illegal access flag for ADC2
74    #[inline(always)]
75    pub fn cadc2f(&mut self) -> CADC2F_W<FCR1rs> {
76        CADC2F_W::new(self, 8)
77    }
78    ///Bit 9 - clear the illegal access flag for VREFBUF
79    #[inline(always)]
80    pub fn cvrefbuff(&mut self) -> CVREFBUFF_W<FCR1rs> {
81        CVREFBUFF_W::new(self, 9)
82    }
83    ///Bit 11 - clear the illegal access flag for DAC1
84    #[inline(always)]
85    pub fn cdac1f(&mut self) -> CDAC1F_W<FCR1rs> {
86        CDAC1F_W::new(self, 11)
87    }
88    ///Bit 12 - clear the illegal access flag for ADF1
89    #[inline(always)]
90    pub fn cadf1f(&mut self) -> CADF1F_W<FCR1rs> {
91        CADF1F_W::new(self, 12)
92    }
93}
94/**TZIC flag clear register 1
95
96You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
97
98See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U595.html#GTZC2_TZIC:FCR1)*/
99pub struct FCR1rs;
100impl crate::RegisterSpec for FCR1rs {
101    type Ux = u32;
102}
103///`write(|w| ..)` method takes [`fcr1::W`](W) writer structure
104impl crate::Writable for FCR1rs {
105    type Safety = crate::Unsafe;
106}
107///`reset()` method sets FCR1 to value 0
108impl crate::Resettable for FCR1rs {}
stm32u5/stm32u595/gtzc2_tzic/fcr1.rs

stm32u5/stm32u595/gtzc2_tzic/
fcr1.rs
