stm32u5/stm32u585/
tamp.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    cr3: CR3,
8    fltcr: FLTCR,
9    atcr1: ATCR1,
10    atseedr: ATSEEDR,
11    ator: ATOR,
12    atcr2: ATCR2,
13    seccfgr: SECCFGR,
14    privcr: PRIVCR,
15    _reserved10: [u8; 0x04],
16    ier: IER,
17    sr: SR,
18    misr: MISR,
19    smisr: SMISR,
20    scr: SCR,
21    count1r: COUNT1R,
22    _reserved16: [u8; 0x10],
23    ercfgr: ERCFGR,
24    _reserved17: [u8; 0xa8],
25    bkpr: [BKPR; 32],
26}
27impl RegisterBlock {
28    ///0x00 - TAMP control register 1
29    #[inline(always)]
30    pub const fn cr1(&self) -> &CR1 {
31        &self.cr1
32    }
33    ///0x04 - TAMP control register 2
34    #[inline(always)]
35    pub const fn cr2(&self) -> &CR2 {
36        &self.cr2
37    }
38    ///0x08 - TAMP control register 3
39    #[inline(always)]
40    pub const fn cr3(&self) -> &CR3 {
41        &self.cr3
42    }
43    ///0x0c - TAMP filter control register
44    #[inline(always)]
45    pub const fn fltcr(&self) -> &FLTCR {
46        &self.fltcr
47    }
48    ///0x10 - TAMP active tamper control register 1
49    #[inline(always)]
50    pub const fn atcr1(&self) -> &ATCR1 {
51        &self.atcr1
52    }
53    ///0x14 - TAMP active tamper seed register
54    #[inline(always)]
55    pub const fn atseedr(&self) -> &ATSEEDR {
56        &self.atseedr
57    }
58    ///0x18 - TAMP active tamper output register
59    #[inline(always)]
60    pub const fn ator(&self) -> &ATOR {
61        &self.ator
62    }
63    ///0x1c - TAMP active tamper control register 2
64    #[inline(always)]
65    pub const fn atcr2(&self) -> &ATCR2 {
66        &self.atcr2
67    }
68    ///0x20 - TAMP secure mode register
69    #[inline(always)]
70    pub const fn seccfgr(&self) -> &SECCFGR {
71        &self.seccfgr
72    }
73    ///0x24 - TAMP privilege mode control register
74    #[inline(always)]
75    pub const fn privcr(&self) -> &PRIVCR {
76        &self.privcr
77    }
78    ///0x2c - TAMP interrupt enable register
79    #[inline(always)]
80    pub const fn ier(&self) -> &IER {
81        &self.ier
82    }
83    ///0x30 - TAMP status register
84    #[inline(always)]
85    pub const fn sr(&self) -> &SR {
86        &self.sr
87    }
88    ///0x34 - TAMP non-secure masked interrupt status register
89    #[inline(always)]
90    pub const fn misr(&self) -> &MISR {
91        &self.misr
92    }
93    ///0x38 - TAMP secure masked interrupt status register
94    #[inline(always)]
95    pub const fn smisr(&self) -> &SMISR {
96        &self.smisr
97    }
98    ///0x3c - TAMP status clear register
99    #[inline(always)]
100    pub const fn scr(&self) -> &SCR {
101        &self.scr
102    }
103    ///0x40 - TAMP monotonic counter 1 register
104    #[inline(always)]
105    pub const fn count1r(&self) -> &COUNT1R {
106        &self.count1r
107    }
108    ///0x54 - TAMP erase configuration register
109    #[inline(always)]
110    pub const fn ercfgr(&self) -> &ERCFGR {
111        &self.ercfgr
112    }
113    ///0x100..0x180 - TAMP backup %s register
114    #[inline(always)]
115    pub const fn bkpr(&self, n: usize) -> &BKPR {
116        &self.bkpr[n]
117    }
118    ///Iterator for array of:
119    ///0x100..0x180 - TAMP backup %s register
120    #[inline(always)]
121    pub fn bkpr_iter(&self) -> impl Iterator<Item = &BKPR> {
122        self.bkpr.iter()
123    }
124    ///0x100 - TAMP backup 0 register
125    #[inline(always)]
126    pub const fn bkp0r(&self) -> &BKPR {
127        self.bkpr(0)
128    }
129    ///0x104 - TAMP backup 1 register
130    #[inline(always)]
131    pub const fn bkp1r(&self) -> &BKPR {
132        self.bkpr(1)
133    }
134    ///0x108 - TAMP backup 2 register
135    #[inline(always)]
136    pub const fn bkp2r(&self) -> &BKPR {
137        self.bkpr(2)
138    }
139    ///0x10c - TAMP backup 3 register
140    #[inline(always)]
141    pub const fn bkp3r(&self) -> &BKPR {
142        self.bkpr(3)
143    }
144    ///0x110 - TAMP backup 4 register
145    #[inline(always)]
146    pub const fn bkp4r(&self) -> &BKPR {
147        self.bkpr(4)
148    }
149    ///0x114 - TAMP backup 5 register
150    #[inline(always)]
151    pub const fn bkp5r(&self) -> &BKPR {
152        self.bkpr(5)
153    }
154    ///0x118 - TAMP backup 6 register
155    #[inline(always)]
156    pub const fn bkp6r(&self) -> &BKPR {
157        self.bkpr(6)
158    }
159    ///0x11c - TAMP backup 7 register
160    #[inline(always)]
161    pub const fn bkp7r(&self) -> &BKPR {
162        self.bkpr(7)
163    }
164    ///0x120 - TAMP backup 8 register
165    #[inline(always)]
166    pub const fn bkp8r(&self) -> &BKPR {
167        self.bkpr(8)
168    }
169    ///0x124 - TAMP backup 9 register
170    #[inline(always)]
171    pub const fn bkp9r(&self) -> &BKPR {
172        self.bkpr(9)
173    }
174    ///0x128 - TAMP backup 10 register
175    #[inline(always)]
176    pub const fn bkp10r(&self) -> &BKPR {
177        self.bkpr(10)
178    }
179    ///0x12c - TAMP backup 11 register
180    #[inline(always)]
181    pub const fn bkp11r(&self) -> &BKPR {
182        self.bkpr(11)
183    }
184    ///0x130 - TAMP backup 12 register
185    #[inline(always)]
186    pub const fn bkp12r(&self) -> &BKPR {
187        self.bkpr(12)
188    }
189    ///0x134 - TAMP backup 13 register
190    #[inline(always)]
191    pub const fn bkp13r(&self) -> &BKPR {
192        self.bkpr(13)
193    }
194    ///0x138 - TAMP backup 14 register
195    #[inline(always)]
196    pub const fn bkp14r(&self) -> &BKPR {
197        self.bkpr(14)
198    }
199    ///0x13c - TAMP backup 15 register
200    #[inline(always)]
201    pub const fn bkp15r(&self) -> &BKPR {
202        self.bkpr(15)
203    }
204    ///0x140 - TAMP backup 16 register
205    #[inline(always)]
206    pub const fn bkp16r(&self) -> &BKPR {
207        self.bkpr(16)
208    }
209    ///0x144 - TAMP backup 17 register
210    #[inline(always)]
211    pub const fn bkp17r(&self) -> &BKPR {
212        self.bkpr(17)
213    }
214    ///0x148 - TAMP backup 18 register
215    #[inline(always)]
216    pub const fn bkp18r(&self) -> &BKPR {
217        self.bkpr(18)
218    }
219    ///0x14c - TAMP backup 19 register
220    #[inline(always)]
221    pub const fn bkp19r(&self) -> &BKPR {
222        self.bkpr(19)
223    }
224    ///0x150 - TAMP backup 20 register
225    #[inline(always)]
226    pub const fn bkp20r(&self) -> &BKPR {
227        self.bkpr(20)
228    }
229    ///0x154 - TAMP backup 21 register
230    #[inline(always)]
231    pub const fn bkp21r(&self) -> &BKPR {
232        self.bkpr(21)
233    }
234    ///0x158 - TAMP backup 22 register
235    #[inline(always)]
236    pub const fn bkp22r(&self) -> &BKPR {
237        self.bkpr(22)
238    }
239    ///0x15c - TAMP backup 23 register
240    #[inline(always)]
241    pub const fn bkp23r(&self) -> &BKPR {
242        self.bkpr(23)
243    }
244    ///0x160 - TAMP backup 24 register
245    #[inline(always)]
246    pub const fn bkp24r(&self) -> &BKPR {
247        self.bkpr(24)
248    }
249    ///0x164 - TAMP backup 25 register
250    #[inline(always)]
251    pub const fn bkp25r(&self) -> &BKPR {
252        self.bkpr(25)
253    }
254    ///0x168 - TAMP backup 26 register
255    #[inline(always)]
256    pub const fn bkp26r(&self) -> &BKPR {
257        self.bkpr(26)
258    }
259    ///0x16c - TAMP backup 27 register
260    #[inline(always)]
261    pub const fn bkp27r(&self) -> &BKPR {
262        self.bkpr(27)
263    }
264    ///0x170 - TAMP backup 28 register
265    #[inline(always)]
266    pub const fn bkp28r(&self) -> &BKPR {
267        self.bkpr(28)
268    }
269    ///0x174 - TAMP backup 29 register
270    #[inline(always)]
271    pub const fn bkp29r(&self) -> &BKPR {
272        self.bkpr(29)
273    }
274    ///0x178 - TAMP backup 30 register
275    #[inline(always)]
276    pub const fn bkp30r(&self) -> &BKPR {
277        self.bkpr(30)
278    }
279    ///0x17c - TAMP backup 31 register
280    #[inline(always)]
281    pub const fn bkp31r(&self) -> &BKPR {
282        self.bkpr(31)
283    }
284}
285/**CR1 (rw) register accessor: TAMP control register 1
286
287You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
288
289See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:CR1)
290
291For information about available fields see [`mod@cr1`] module*/
292pub type CR1 = crate::Reg<cr1::CR1rs>;
293///TAMP control register 1
294pub mod cr1;
295/**CR2 (rw) register accessor: TAMP control register 2
296
297You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
298
299See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:CR2)
300
301For information about available fields see [`mod@cr2`] module*/
302pub type CR2 = crate::Reg<cr2::CR2rs>;
303///TAMP control register 2
304pub mod cr2;
305/**CR3 (rw) register accessor: TAMP control register 3
306
307You can [`read`](crate::Reg::read) this register and get [`cr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
308
309See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:CR3)
310
311For information about available fields see [`mod@cr3`] module*/
312pub type CR3 = crate::Reg<cr3::CR3rs>;
313///TAMP control register 3
314pub mod cr3;
315/**FLTCR (rw) register accessor: TAMP filter control register
316
317You can [`read`](crate::Reg::read) this register and get [`fltcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fltcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
318
319See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:FLTCR)
320
321For information about available fields see [`mod@fltcr`] module*/
322pub type FLTCR = crate::Reg<fltcr::FLTCRrs>;
323///TAMP filter control register
324pub mod fltcr;
325/**ATCR1 (rw) register accessor: TAMP active tamper control register 1
326
327You can [`read`](crate::Reg::read) this register and get [`atcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
328
329See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:ATCR1)
330
331For information about available fields see [`mod@atcr1`] module*/
332pub type ATCR1 = crate::Reg<atcr1::ATCR1rs>;
333///TAMP active tamper control register 1
334pub mod atcr1;
335/**ATSEEDR (w) register accessor: TAMP active tamper seed register
336
337You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atseedr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
338
339See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:ATSEEDR)
340
341For information about available fields see [`mod@atseedr`] module*/
342pub type ATSEEDR = crate::Reg<atseedr::ATSEEDRrs>;
343///TAMP active tamper seed register
344pub mod atseedr;
345/**ATOR (r) register accessor: TAMP active tamper output register
346
347You can [`read`](crate::Reg::read) this register and get [`ator::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
348
349See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:ATOR)
350
351For information about available fields see [`mod@ator`] module*/
352pub type ATOR = crate::Reg<ator::ATORrs>;
353///TAMP active tamper output register
354pub mod ator;
355/**ATCR2 (rw) register accessor: TAMP active tamper control register 2
356
357You can [`read`](crate::Reg::read) this register and get [`atcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
358
359See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:ATCR2)
360
361For information about available fields see [`mod@atcr2`] module*/
362pub type ATCR2 = crate::Reg<atcr2::ATCR2rs>;
363///TAMP active tamper control register 2
364pub mod atcr2;
365/**SECCFGR (rw) register accessor: TAMP secure mode register
366
367You can [`read`](crate::Reg::read) this register and get [`seccfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
368
369See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:SECCFGR)
370
371For information about available fields see [`mod@seccfgr`] module*/
372pub type SECCFGR = crate::Reg<seccfgr::SECCFGRrs>;
373///TAMP secure mode register
374pub mod seccfgr;
375/**PRIVCR (rw) register accessor: TAMP privilege mode control register
376
377You can [`read`](crate::Reg::read) this register and get [`privcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`privcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
378
379See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:PRIVCR)
380
381For information about available fields see [`mod@privcr`] module*/
382pub type PRIVCR = crate::Reg<privcr::PRIVCRrs>;
383///TAMP privilege mode control register
384pub mod privcr;
385/**IER (rw) register accessor: TAMP interrupt enable register
386
387You can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
388
389See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:IER)
390
391For information about available fields see [`mod@ier`] module*/
392pub type IER = crate::Reg<ier::IERrs>;
393///TAMP interrupt enable register
394pub mod ier;
395/**SR (r) register accessor: TAMP status register
396
397You can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
398
399See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:SR)
400
401For information about available fields see [`mod@sr`] module*/
402pub type SR = crate::Reg<sr::SRrs>;
403///TAMP status register
404pub mod sr;
405/**MISR (r) register accessor: TAMP non-secure masked interrupt status register
406
407You can [`read`](crate::Reg::read) this register and get [`misr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
408
409See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:MISR)
410
411For information about available fields see [`mod@misr`] module*/
412pub type MISR = crate::Reg<misr::MISRrs>;
413///TAMP non-secure masked interrupt status register
414pub mod misr;
415/**SMISR (r) register accessor: TAMP secure masked interrupt status register
416
417You can [`read`](crate::Reg::read) this register and get [`smisr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
418
419See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:SMISR)
420
421For information about available fields see [`mod@smisr`] module*/
422pub type SMISR = crate::Reg<smisr::SMISRrs>;
423///TAMP secure masked interrupt status register
424pub mod smisr;
425/**SCR (w) register accessor: TAMP status clear register
426
427You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
428
429See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:SCR)
430
431For information about available fields see [`mod@scr`] module*/
432pub type SCR = crate::Reg<scr::SCRrs>;
433///TAMP status clear register
434pub mod scr;
435/**COUNT1R (r) register accessor: TAMP monotonic counter 1 register
436
437You can [`read`](crate::Reg::read) this register and get [`count1r::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
438
439See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:COUNT1R)
440
441For information about available fields see [`mod@count1r`] module*/
442pub type COUNT1R = crate::Reg<count1r::COUNT1Rrs>;
443///TAMP monotonic counter 1 register
444pub mod count1r;
445/**ERCFGR (rw) register accessor: TAMP erase configuration register
446
447You can [`read`](crate::Reg::read) this register and get [`ercfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ercfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
448
449See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:ERCFGR)
450
451For information about available fields see [`mod@ercfgr`] module*/
452pub type ERCFGR = crate::Reg<ercfgr::ERCFGRrs>;
453///TAMP erase configuration register
454pub mod ercfgr;
455/**BKPR (rw) register accessor: TAMP backup %s register
456
457You can [`read`](crate::Reg::read) this register and get [`bkpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
458
459See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#TAMP:BKP[0]R)
460
461For information about available fields see [`mod@bkpr`] module*/
462pub type BKPR = crate::Reg<bkpr::BKPRrs>;
463///TAMP backup %s register
464pub mod bkpr;
stm32u5/stm32u585/tamp.rs

stm32u5/stm32u585/
tamp.rs
