stm32u5/stm32u585/lptim1/
icr_output.rs

1///Register `ICR_output` writer
2pub type W = crate::W<ICR_OUTPUTrs>;
3///Field `CC1IF` writer - Capture/compare 1 clear flag
4pub type CC1IF_W<'a, REG> = crate::BitWriter<'a, REG>;
5///Field `ARRMCF` writer - Autoreload match Clear Flag
6pub type ARRMCF_W<'a, REG> = crate::BitWriter<'a, REG>;
7///Field `EXTTRIGCF` writer - External trigger valid edge Clear Flag
8pub type EXTTRIGCF_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `CMP1OKCF` writer - Compare register 1 update OK Clear Flag
10pub type CMP1OKCF_W<'a, REG> = crate::BitWriter<'a, REG>;
11///Field `ARROKCF` writer - Autoreload register update OK Clear Flag
12pub type ARROKCF_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `UPCF` writer - Direction change to UP Clear Flag
14pub type UPCF_W<'a, REG> = crate::BitWriter<'a, REG>;
15///Field `DOWNCF` writer - Direction change to down Clear Flag
16pub type DOWNCF_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `UECF` writer - Update event clear flag
18pub type UECF_W<'a, REG> = crate::BitWriter<'a, REG>;
19///Field `REPOKCF` writer - Repetition register update OK clear flag
20pub type REPOKCF_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `CC2CF` writer - Capture/compare 2 clear flag
22pub type CC2CF_W<'a, REG> = crate::BitWriter<'a, REG>;
23///Field `CMP2OKCF` writer - Compare register 2 update OK clear flag
24pub type CMP2OKCF_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `DIEROKCF` writer - Interrupt enable register update OK clear flag
26pub type DIEROKCF_W<'a, REG> = crate::BitWriter<'a, REG>;
27impl core::fmt::Debug for crate::generic::Reg<ICR_OUTPUTrs> {
28    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
29        write!(f, "(not readable)")
30    }
31}
32impl W {
33    ///Bit 0 - Capture/compare 1 clear flag
34    #[inline(always)]
35    pub fn cc1if(&mut self) -> CC1IF_W<ICR_OUTPUTrs> {
36        CC1IF_W::new(self, 0)
37    }
38    ///Bit 1 - Autoreload match Clear Flag
39    #[inline(always)]
40    pub fn arrmcf(&mut self) -> ARRMCF_W<ICR_OUTPUTrs> {
41        ARRMCF_W::new(self, 1)
42    }
43    ///Bit 2 - External trigger valid edge Clear Flag
44    #[inline(always)]
45    pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<ICR_OUTPUTrs> {
46        EXTTRIGCF_W::new(self, 2)
47    }
48    ///Bit 3 - Compare register 1 update OK Clear Flag
49    #[inline(always)]
50    pub fn cmp1okcf(&mut self) -> CMP1OKCF_W<ICR_OUTPUTrs> {
51        CMP1OKCF_W::new(self, 3)
52    }
53    ///Bit 4 - Autoreload register update OK Clear Flag
54    #[inline(always)]
55    pub fn arrokcf(&mut self) -> ARROKCF_W<ICR_OUTPUTrs> {
56        ARROKCF_W::new(self, 4)
57    }
58    ///Bit 5 - Direction change to UP Clear Flag
59    #[inline(always)]
60    pub fn upcf(&mut self) -> UPCF_W<ICR_OUTPUTrs> {
61        UPCF_W::new(self, 5)
62    }
63    ///Bit 6 - Direction change to down Clear Flag
64    #[inline(always)]
65    pub fn downcf(&mut self) -> DOWNCF_W<ICR_OUTPUTrs> {
66        DOWNCF_W::new(self, 6)
67    }
68    ///Bit 7 - Update event clear flag
69    #[inline(always)]
70    pub fn uecf(&mut self) -> UECF_W<ICR_OUTPUTrs> {
71        UECF_W::new(self, 7)
72    }
73    ///Bit 8 - Repetition register update OK clear flag
74    #[inline(always)]
75    pub fn repokcf(&mut self) -> REPOKCF_W<ICR_OUTPUTrs> {
76        REPOKCF_W::new(self, 8)
77    }
78    ///Bit 9 - Capture/compare 2 clear flag
79    #[inline(always)]
80    pub fn cc2cf(&mut self) -> CC2CF_W<ICR_OUTPUTrs> {
81        CC2CF_W::new(self, 9)
82    }
83    ///Bit 19 - Compare register 2 update OK clear flag
84    #[inline(always)]
85    pub fn cmp2okcf(&mut self) -> CMP2OKCF_W<ICR_OUTPUTrs> {
86        CMP2OKCF_W::new(self, 19)
87    }
88    ///Bit 24 - Interrupt enable register update OK clear flag
89    #[inline(always)]
90    pub fn dierokcf(&mut self) -> DIEROKCF_W<ICR_OUTPUTrs> {
91        DIEROKCF_W::new(self, 24)
92    }
93}
94/**Interrupt Clear Register (output mode)
95
96You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr_output::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
97
98See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U585.html#LPTIM1:ICR_output)*/
99pub struct ICR_OUTPUTrs;
100impl crate::RegisterSpec for ICR_OUTPUTrs {
101    type Ux = u32;
102}
103///`write(|w| ..)` method takes [`icr_output::W`](W) writer structure
104impl crate::Writable for ICR_OUTPUTrs {
105    type Safety = crate::Unsafe;
106}
107///`reset()` method sets ICR_output to value 0
108impl crate::Resettable for ICR_OUTPUTrs {}
stm32u5/stm32u585/lptim1/icr_output.rs

stm32u5/stm32u585/lptim1/
icr_output.rs
