Module rcc

Reset and clock control

Used by: stm32wl5x_cm0p, stm32wl5x_cm4

Modules

AHB1ENR

AHB1 peripheral clock enable register

AHB1RSTR

AHB1 peripheral reset register

AHB1SMENR

AHB1 peripheral clocks enable in Sleep modes register

AHB2ENR

AHB2 peripheral clock enable register

AHB2RSTR

AHB2 peripheral reset register

AHB2SMENR

AHB2 peripheral clocks enable in Sleep modes register

AHB3ENR

AHB3 peripheral clock enable register

AHB3RSTR

AHB3 peripheral reset register

AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register

APB1ENR1

APB1 peripheral clock enable register 1

APB1ENR2

APB1 peripheral clock enable register 2

APB1RSTR1

APB1 peripheral reset register 1

APB1RSTR2

APB1 peripheral reset register 2

APB1SMENR1

APB1 peripheral clocks enable in Sleep mode register 1

APB1SMENR2

APB1 peripheral clocks enable in Sleep mode register 2

APB2ENR

APB2 peripheral clock enable register

APB2RSTR

APB2 peripheral reset register

APB2SMENR

APB2 peripheral clocks enable in Sleep mode register

APB3ENR

APB3 peripheral clock enable register

APB3RSTR

APB3 peripheral reset register

APB3SMENR

APB3 peripheral clock enable in Sleep mode register

BDCR

Backup domain control register

C2AHB1ENR

CPU2 AHB1 peripheral clock enable register

C2AHB1SMENR

CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]

C2AHB2ENR

CPU2 AHB2 peripheral clock enable register

C2AHB2SMENR

CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]

C2AHB3ENR

CPU2 AHB3 peripheral clock enable register [dual core device only]

C2AHB3SMENR

CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]

C2APB1ENR1

CPU2 APB1 peripheral clock enable register 1 [dual core device only]

C2APB1ENR2

CPU2 APB1 peripheral clock enable register 2 [dual core device only]

C2APB1SMENR1

CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]

C2APB1SMENR2

CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]

C2APB2ENR

CPU2 APB2 peripheral clock enable register [dual core device only]

C2APB2SMENR

CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]

C2APB3ENR

CPU2 APB3 peripheral clock enable register [dual core device only]

C2APB3SMENR

CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]

CCIPR

Peripherals independent clock configuration register

CFGR

Clock configuration register

CICR

Clock interrupt clear register

CIER

Clock interrupt enable register

CIFR

Clock interrupt flag register

CR

Clock control register

CSR

Control/status register

EXTCFGR

Extended clock recovery register

ICSCR

Internal clock sources calibration register

PLLCFGR

PLL configuration register

Structs

Instance

RegisterBlock

ResetValues