Expand description
FMC register block
Used by: stm32mp153, stm32mp157
Modules§
- FMC_
BCHDS R0 - This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer. .
- FMC_
BCHDS R1 - The maximum error correction capability of the BCH block embedded in the FMC is 8 errors
- FMC_
BCHDS R2 - The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively.
- FMC_
BCHDS R3 - The maximum error correction capability of the BCH block embedded in the FMC is 8 errors.
- FMC_
BCHDS R4 - The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively. .
- FMC_
BCHICR - FMC BCH Interrupt Clear Register
- FMC_
BCHIER - FMC BCH Interrupt enable register
- FMC_
BCHISR - This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared.
- FMC_
BCHPB R1 - These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant.
- FMC_
BCHPB R2 - FMC BCH Parity Bits Register 2
- FMC_
BCHPB R3 - FMC BCH Parity Bits Register 3
- FMC_
BCHPB R4 - FMC BCH Parity Bits Register 4
- FMC_
BCR1 - This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
- FMC_
BCR2 - This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
- FMC_
BCR3 - This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
- FMC_
BCR4 - This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
- FMC_
BTR1 - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
- FMC_
BTR2 - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
- FMC_
BTR3 - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
- FMC_
BTR4 - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
- FMC_
BWTR1 - This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
- FMC_
BWTR2 - This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
- FMC_
BWTR3 - This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
- FMC_
BWTR4 - This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
- FMC_
CSQA R1 - This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer.
- FMC_
CSQA R2 - This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable.
- FMC_
CSQCFG R1 - FMC NAND Command Sequencer Configuration Register 1
- FMC_
CSQCFG R2 - This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written. .
- FMC_
CSQCFG R3 - FMC NAND sequencer configuration register 3
- FMC_
CSQCR - FMC NAND Command Sequencer Control Register
- FMC_
CSQEMSR - This register holds a sector error mapping status when the whole transfer is complete.
- FMC_
CSQICR - FMC NAND Command Sequencer Interrupt Clear Register
- FMC_
CSQIER - FMC NAND Command Sequencer Interrupt Enable Register
- FMC_
CSQISR - FMC NAND Command Sequencer Interrupt Status Register
- FMC_
HECCR - This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
- FMC_HPR
- This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
- FMC_
HWCFG R1 - FMC Hardware configuration register 1
- FMC_
HWCFG R2 - FMC Hardware configuration register 2
- FMC_
IPIDR - FMC Identification register
- FMC_
PATT - The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function).
- FMC_PCR
- NAND Flash Programmable control register
- FMC_
PCSCNTR - This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h
- FMC_
PMEM - The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses.
- FMC_
SIDR - FMC Size Identification register
- FMC_SR
- This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits.
- FMC_
VERR - FMC Version register