Expand description
Advanced-timers
Modules§
- AF1
- DMA address for full transfer
- AF2
- DMA address for full transfer
- ARR
- auto-reload register
- BDTR
- break and dead-time register
- CCER
- capture/compare enable register
- CCMR1
- CCMR1_Output and CCMR1_Input CCMR1_Output: capture/compare mode register 1 (output mode) CCMR1_Input: capture/compare mode register 1 (output mode)
- CCMR2
- CCMR2_Output and CCMR2_Input CCMR2_Output: capture/compare mode register 2 (output mode) CCMR2_Input: capture/compare mode register 2 (output mode)
- CCMR3_
Output - capture/compare mode register 2 (output mode)
- CCR1
- capture/compare register 1
- CCR2
- capture/compare register 2
- CCR3
- capture/compare register 3
- CCR4
- capture/compare register 4
- CCR5
- capture/compare register 4
- CCR6
- capture/compare register 4
- CNT
- counter
- CR1
- control register 1
- CR2
- control register 2
- DCR
- DMA control register
- DIER
- DMA/Interrupt enable register
- DMAR
- DMA address for full transfer
- EGR
- event generation register
- OR1
- option register 1
- PSC
- prescaler
- RCR
- repetition counter register
- SMCR
- slave mode control register
- SR
- status register
- TIM1
- Access functions for the TIM1 peripheral instance
Structs§
Constants§
- TIM1
- Raw pointer to TIM1