Module CCMR1

CCMR1_Output and CCMR1_Input CCMR1_Output: capture/compare mode register 1 (output mode) CCMR1_Input: capture/compare mode register 1 (input mode)

Modules

CC1S

Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

CC2S

Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

IC1F

Input capture 1 filter

IC1PSC

Input capture 1 prescaler

IC2F

Input capture 2 filter

IC2PSC

Input capture 2 prescaler

OC1CE

Output compare 1 clear enable

OC1FE

Output compare 1 fast enable

OC1M

Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.

OC1M_3

Output Compare 1 mode - bit 3

OC1PE

Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

OC2CE

Output compare 2 clear enable

OC2FE

Output compare 2 fast enable

OC2M

Output compare 2 mode

OC2M_3

Output Compare 2 mode - bit 3

OC2PE

Output compare 2 preload enable