stm32ral/stm32wl/peripherals/tim16.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General-purpose timers
4//!
5//! Used by: stm32wl5x_cm0p, stm32wl5x_cm4, stm32wle5
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// TIM16/TIM17 control register 1
12pub mod CR1 {
13
14 /// UIF status bit remapping
15 pub mod UIFREMAP {
16 /// Offset (11 bits)
17 pub const offset: u32 = 11;
18 /// Mask (1 bit: 1 << 11)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31
28 pub const Disabled: u32 = 0b0;
29
30 /// 0b1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31
31 pub const Enabled: u32 = 0b1;
32 }
33 }
34
35 /// Clock division
36 pub mod CKD {
37 /// Offset (8 bits)
38 pub const offset: u32 = 8;
39 /// Mask (2 bits: 0b11 << 8)
40 pub const mask: u32 = 0b11 << offset;
41 /// Read-only values (empty)
42 pub mod R {}
43 /// Write-only values (empty)
44 pub mod W {}
45 /// Read-write values
46 pub mod RW {
47
48 /// 0b00: t_DTS = t_CK_INT
49 pub const Div1: u32 = 0b00;
50
51 /// 0b01: t_DTS = 2 × t_CK_INT
52 pub const Div2: u32 = 0b01;
53
54 /// 0b10: t_DTS = 4 × t_CK_INT
55 pub const Div4: u32 = 0b10;
56 }
57 }
58
59 /// Auto-reload preload enable
60 pub mod ARPE {
61 /// Offset (7 bits)
62 pub const offset: u32 = 7;
63 /// Mask (1 bit: 1 << 7)
64 pub const mask: u32 = 1 << offset;
65 /// Read-only values (empty)
66 pub mod R {}
67 /// Write-only values (empty)
68 pub mod W {}
69 /// Read-write values
70 pub mod RW {
71
72 /// 0b0: TIMx_APRR register is not buffered
73 pub const Disabled: u32 = 0b0;
74
75 /// 0b1: TIMx_APRR register is buffered
76 pub const Enabled: u32 = 0b1;
77 }
78 }
79
80 /// One pulse mode
81 pub mod OPM {
82 /// Offset (3 bits)
83 pub const offset: u32 = 3;
84 /// Mask (1 bit: 1 << 3)
85 pub const mask: u32 = 1 << offset;
86 /// Read-only values (empty)
87 pub mod R {}
88 /// Write-only values (empty)
89 pub mod W {}
90 /// Read-write values
91 pub mod RW {
92
93 /// 0b0: Counter is not stopped at update event
94 pub const Disabled: u32 = 0b0;
95
96 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
97 pub const Enabled: u32 = 0b1;
98 }
99 }
100
101 /// Update request source
102 pub mod URS {
103 /// Offset (2 bits)
104 pub const offset: u32 = 2;
105 /// Mask (1 bit: 1 << 2)
106 pub const mask: u32 = 1 << offset;
107 /// Read-only values (empty)
108 pub mod R {}
109 /// Write-only values (empty)
110 pub mod W {}
111 /// Read-write values
112 pub mod RW {
113
114 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
115 pub const AnyEvent: u32 = 0b0;
116
117 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
118 pub const CounterOnly: u32 = 0b1;
119 }
120 }
121
122 /// Update disable
123 pub mod UDIS {
124 /// Offset (1 bits)
125 pub const offset: u32 = 1;
126 /// Mask (1 bit: 1 << 1)
127 pub const mask: u32 = 1 << offset;
128 /// Read-only values (empty)
129 pub mod R {}
130 /// Write-only values (empty)
131 pub mod W {}
132 /// Read-write values
133 pub mod RW {
134
135 /// 0b0: Update event enabled
136 pub const Enabled: u32 = 0b0;
137
138 /// 0b1: Update event disabled
139 pub const Disabled: u32 = 0b1;
140 }
141 }
142
143 /// Counter enable
144 pub mod CEN {
145 /// Offset (0 bits)
146 pub const offset: u32 = 0;
147 /// Mask (1 bit: 1 << 0)
148 pub const mask: u32 = 1 << offset;
149 /// Read-only values (empty)
150 pub mod R {}
151 /// Write-only values (empty)
152 pub mod W {}
153 /// Read-write values
154 pub mod RW {
155
156 /// 0b0: Counter disabled
157 pub const Disabled: u32 = 0b0;
158
159 /// 0b1: Counter enabled
160 pub const Enabled: u32 = 0b1;
161 }
162 }
163}
164
165/// TIM16/TIM17 control register 2
166pub mod CR2 {
167
168 /// OIS1N
169 pub mod OIS1N {
170 /// Offset (9 bits)
171 pub const offset: u32 = 9;
172 /// Mask (1 bit: 1 << 9)
173 pub const mask: u32 = 1 << offset;
174 /// Read-only values (empty)
175 pub mod R {}
176 /// Write-only values (empty)
177 pub mod W {}
178 /// Read-write values
179 pub mod RW {
180
181 /// 0b0: OC1N=0 after a dead-time when MOE=0
182 pub const Low: u32 = 0b0;
183
184 /// 0b1: OC1N=1 after a dead-time when MOE=0
185 pub const High: u32 = 0b1;
186 }
187 }
188
189 /// OIS1
190 pub mod OIS1 {
191 /// Offset (8 bits)
192 pub const offset: u32 = 8;
193 /// Mask (1 bit: 1 << 8)
194 pub const mask: u32 = 1 << offset;
195 /// Read-only values (empty)
196 pub mod R {}
197 /// Write-only values (empty)
198 pub mod W {}
199 /// Read-write values
200 pub mod RW {
201
202 /// 0b0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
203 pub const Low: u32 = 0b0;
204
205 /// 0b1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
206 pub const High: u32 = 0b1;
207 }
208 }
209
210 /// CCDS
211 pub mod CCDS {
212 /// Offset (3 bits)
213 pub const offset: u32 = 3;
214 /// Mask (1 bit: 1 << 3)
215 pub const mask: u32 = 1 << offset;
216 /// Read-only values (empty)
217 pub mod R {}
218 /// Write-only values (empty)
219 pub mod W {}
220 /// Read-write values
221 pub mod RW {
222
223 /// 0b0: CCx DMA request sent when CCx event occurs
224 pub const OnCompare: u32 = 0b0;
225
226 /// 0b1: CCx DMA request sent when update event occurs
227 pub const OnUpdate: u32 = 0b1;
228 }
229 }
230
231 /// CCUS
232 pub mod CCUS {
233 /// Offset (2 bits)
234 pub const offset: u32 = 2;
235 /// Mask (1 bit: 1 << 2)
236 pub const mask: u32 = 1 << offset;
237 /// Read-only values (empty)
238 pub mod R {}
239 /// Write-only values (empty)
240 pub mod W {}
241 /// Read-write values
242 pub mod RW {
243
244 /// 0b0: Capture/compare are updated only by setting the COMG bit
245 pub const Default: u32 = 0b0;
246
247 /// 0b1: Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI
248 pub const WithRisingEdge: u32 = 0b1;
249 }
250 }
251
252 /// CCPC
253 pub mod CCPC {
254 /// Offset (0 bits)
255 pub const offset: u32 = 0;
256 /// Mask (1 bit: 1 << 0)
257 pub const mask: u32 = 1 << offset;
258 /// Read-only values (empty)
259 pub mod R {}
260 /// Write-only values (empty)
261 pub mod W {}
262 /// Read-write values
263 pub mod RW {
264
265 /// 0b0: CCxE, CCxNE and OCxM bits are not preloaded
266 pub const NotPreloaded: u32 = 0b0;
267
268 /// 0b1: CCxE, CCxNE and OCxM bits are preloaded
269 pub const Preloaded: u32 = 0b1;
270 }
271 }
272}
273
274/// TIM16/TIM17 DMA/interrupt enable register
275pub mod DIER {
276
277 /// Capture/Compare 1 DMA request enable
278 pub mod CC1DE {
279 /// Offset (9 bits)
280 pub const offset: u32 = 9;
281 /// Mask (1 bit: 1 << 9)
282 pub const mask: u32 = 1 << offset;
283 /// Read-only values (empty)
284 pub mod R {}
285 /// Write-only values (empty)
286 pub mod W {}
287 /// Read-write values
288 pub mod RW {
289
290 /// 0b0: CC1 DMA request disabled
291 pub const Disabled: u32 = 0b0;
292
293 /// 0b1: CC1 DMA request enabled
294 pub const Enabled: u32 = 0b1;
295 }
296 }
297
298 /// Update DMA request enable
299 pub mod UDE {
300 /// Offset (8 bits)
301 pub const offset: u32 = 8;
302 /// Mask (1 bit: 1 << 8)
303 pub const mask: u32 = 1 << offset;
304 /// Read-only values (empty)
305 pub mod R {}
306 /// Write-only values (empty)
307 pub mod W {}
308 /// Read-write values
309 pub mod RW {
310
311 /// 0b0: Update DMA request disabled
312 pub const Disabled: u32 = 0b0;
313
314 /// 0b1: Update DMA request enabled
315 pub const Enabled: u32 = 0b1;
316 }
317 }
318
319 /// Break interrupt enable
320 pub mod BIE {
321 /// Offset (7 bits)
322 pub const offset: u32 = 7;
323 /// Mask (1 bit: 1 << 7)
324 pub const mask: u32 = 1 << offset;
325 /// Read-only values (empty)
326 pub mod R {}
327 /// Write-only values (empty)
328 pub mod W {}
329 /// Read-write values
330 pub mod RW {
331
332 /// 0b0: Break interrupt disabled
333 pub const Disabled: u32 = 0b0;
334
335 /// 0b1: Break interrupt enabled
336 pub const Enabled: u32 = 0b1;
337 }
338 }
339
340 /// COM interrupt enable
341 pub mod COMIE {
342 /// Offset (5 bits)
343 pub const offset: u32 = 5;
344 /// Mask (1 bit: 1 << 5)
345 pub const mask: u32 = 1 << offset;
346 /// Read-only values (empty)
347 pub mod R {}
348 /// Write-only values (empty)
349 pub mod W {}
350 /// Read-write values
351 pub mod RW {
352
353 /// 0b0: COM interrupt disabled
354 pub const Disabled: u32 = 0b0;
355
356 /// 0b1: COM interrupt enabled
357 pub const Enabled: u32 = 0b1;
358 }
359 }
360
361 /// Capture/Compare 1 interrupt enable
362 pub mod CC1IE {
363 /// Offset (1 bits)
364 pub const offset: u32 = 1;
365 /// Mask (1 bit: 1 << 1)
366 pub const mask: u32 = 1 << offset;
367 /// Read-only values (empty)
368 pub mod R {}
369 /// Write-only values (empty)
370 pub mod W {}
371 /// Read-write values
372 pub mod RW {
373
374 /// 0b0: CC1 interrupt disabled
375 pub const Disabled: u32 = 0b0;
376
377 /// 0b1: CC1 interrupt enabled
378 pub const Enabled: u32 = 0b1;
379 }
380 }
381
382 /// Update interrupt enable
383 pub mod UIE {
384 /// Offset (0 bits)
385 pub const offset: u32 = 0;
386 /// Mask (1 bit: 1 << 0)
387 pub const mask: u32 = 1 << offset;
388 /// Read-only values (empty)
389 pub mod R {}
390 /// Write-only values (empty)
391 pub mod W {}
392 /// Read-write values
393 pub mod RW {
394
395 /// 0b0: Update interrupt disabled
396 pub const Disabled: u32 = 0b0;
397
398 /// 0b1: Update interrupt enabled
399 pub const Enabled: u32 = 0b1;
400 }
401 }
402}
403
404/// TIM16/TIM17 status register
405pub mod SR {
406
407 /// Capture/Compare 1 overcapture flag
408 pub mod CC1OF {
409 /// Offset (9 bits)
410 pub const offset: u32 = 9;
411 /// Mask (1 bit: 1 << 9)
412 pub const mask: u32 = 1 << offset;
413 /// Read-only values
414 pub mod R {
415
416 /// 0b0: No overcapture has been detected
417 pub const NoOvercapture: u32 = 0b0;
418
419 /// 0b1: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
420 pub const Overcapture: u32 = 0b1;
421 }
422 /// Write-only values
423 pub mod W {
424
425 /// 0b0: Clear flag
426 pub const Clear: u32 = 0b0;
427 }
428 /// Read-write values (empty)
429 pub mod RW {}
430 }
431
432 /// Break interrupt flag
433 pub mod BIF {
434 /// Offset (7 bits)
435 pub const offset: u32 = 7;
436 /// Mask (1 bit: 1 << 7)
437 pub const mask: u32 = 1 << offset;
438 /// Read-only values
439 pub mod R {
440
441 /// 0b0: No break event occurred
442 pub const NoBreak: u32 = 0b0;
443
444 /// 0b1: Break interrupt pending
445 pub const Break: u32 = 0b1;
446 }
447 pub use super::CC1OF::W;
448 /// Read-write values (empty)
449 pub mod RW {}
450 }
451
452 /// COM interrupt flag
453 pub mod COMIF {
454 /// Offset (5 bits)
455 pub const offset: u32 = 5;
456 /// Mask (1 bit: 1 << 5)
457 pub const mask: u32 = 1 << offset;
458 /// Read-only values
459 pub mod R {
460
461 /// 0b0: No COM event occurred
462 pub const NoCOM: u32 = 0b0;
463
464 /// 0b1: COM interrupt pending
465 pub const COM: u32 = 0b1;
466 }
467 pub use super::CC1OF::W;
468 /// Read-write values (empty)
469 pub mod RW {}
470 }
471
472 /// Capture/Compare 1 interrupt flag
473 pub mod CC1IF {
474 /// Offset (1 bits)
475 pub const offset: u32 = 1;
476 /// Mask (1 bit: 1 << 1)
477 pub const mask: u32 = 1 << offset;
478 /// Read-only values
479 pub mod R {
480
481 /// 0b0: No campture/compare has been detected
482 pub const NoMatch: u32 = 0b0;
483
484 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register
485 pub const Match: u32 = 0b1;
486 }
487 pub use super::CC1OF::W;
488 /// Read-write values (empty)
489 pub mod RW {}
490 }
491
492 /// Update interrupt flag
493 pub mod UIF {
494 /// Offset (0 bits)
495 pub const offset: u32 = 0;
496 /// Mask (1 bit: 1 << 0)
497 pub const mask: u32 = 1 << offset;
498 /// Read-only values (empty)
499 pub mod R {}
500 /// Write-only values (empty)
501 pub mod W {}
502 /// Read-write values
503 pub mod RW {
504
505 /// 0b0: No update occurred
506 pub const Clear: u32 = 0b0;
507
508 /// 0b1: Update interrupt pending.
509 pub const UpdatePending: u32 = 0b1;
510 }
511 }
512}
513
514/// TIM16/TIM17 event generation register
515pub mod EGR {
516
517 /// Break generation
518 pub mod BG {
519 /// Offset (7 bits)
520 pub const offset: u32 = 7;
521 /// Mask (1 bit: 1 << 7)
522 pub const mask: u32 = 1 << offset;
523 /// Read-only values (empty)
524 pub mod R {}
525 /// Write-only values
526 pub mod W {
527
528 /// 0b1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
529 pub const Trigger: u32 = 0b1;
530 }
531 /// Read-write values (empty)
532 pub mod RW {}
533 }
534
535 /// Capture/Compare control update generation
536 pub mod COMG {
537 /// Offset (5 bits)
538 pub const offset: u32 = 5;
539 /// Mask (1 bit: 1 << 5)
540 pub const mask: u32 = 1 << offset;
541 /// Read-only values (empty)
542 pub mod R {}
543 /// Write-only values
544 pub mod W {
545
546 /// 0b1: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
547 pub const Trigger: u32 = 0b1;
548 }
549 /// Read-write values (empty)
550 pub mod RW {}
551 }
552
553 /// Capture/Compare 1 generation
554 pub mod CC1G {
555 /// Offset (1 bits)
556 pub const offset: u32 = 1;
557 /// Mask (1 bit: 1 << 1)
558 pub const mask: u32 = 1 << offset;
559 /// Read-only values (empty)
560 pub mod R {}
561 /// Write-only values
562 pub mod W {
563
564 /// 0b1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register
565 pub const Trigger: u32 = 0b1;
566 }
567 /// Read-write values (empty)
568 pub mod RW {}
569 }
570
571 /// Update generation
572 pub mod UG {
573 /// Offset (0 bits)
574 pub const offset: u32 = 0;
575 /// Mask (1 bit: 1 << 0)
576 pub const mask: u32 = 1 << offset;
577 /// Read-only values (empty)
578 pub mod R {}
579 /// Write-only values
580 pub mod W {
581
582 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
583 pub const Update: u32 = 0b1;
584 }
585 /// Read-write values (empty)
586 pub mod RW {}
587 }
588}
589
590/// CCMR1_Output and CCMR1_Input
591/// CCMR1_Output: TIM16/TIM17 capture/compare mode register 1
592/// CCMR1_Input: TIM16/TIM17 capture/compare mode register 1
593pub mod CCMR1 {
594
595 /// OC1M
596 pub mod OC1M_3 {
597 /// Offset (16 bits)
598 pub const offset: u32 = 16;
599 /// Mask (1 bit: 1 << 16)
600 pub const mask: u32 = 1 << offset;
601 /// Read-only values (empty)
602 pub mod R {}
603 /// Write-only values (empty)
604 pub mod W {}
605 /// Read-write values (empty)
606 pub mod RW {}
607 }
608
609 /// OC1M
610 pub mod OC1M {
611 /// Offset (4 bits)
612 pub const offset: u32 = 4;
613 /// Mask (3 bits: 0b111 << 4)
614 pub const mask: u32 = 0b111 << offset;
615 /// Read-only values (empty)
616 pub mod R {}
617 /// Write-only values (empty)
618 pub mod W {}
619 /// Read-write values
620 pub mod RW {
621
622 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
623 pub const Frozen: u32 = 0b000;
624
625 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
626 pub const ActiveOnMatch: u32 = 0b001;
627
628 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
629 pub const InactiveOnMatch: u32 = 0b010;
630
631 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
632 pub const Toggle: u32 = 0b011;
633
634 /// 0b100: OCyREF is forced low
635 pub const ForceInactive: u32 = 0b100;
636
637 /// 0b101: OCyREF is forced high
638 pub const ForceActive: u32 = 0b101;
639
640 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
641 pub const PwmMode1: u32 = 0b110;
642
643 /// 0b111: Inversely to PwmMode1
644 pub const PwmMode2: u32 = 0b111;
645 }
646 }
647
648 /// OC1PE
649 pub mod OC1PE {
650 /// Offset (3 bits)
651 pub const offset: u32 = 3;
652 /// Mask (1 bit: 1 << 3)
653 pub const mask: u32 = 1 << offset;
654 /// Read-only values (empty)
655 pub mod R {}
656 /// Write-only values (empty)
657 pub mod W {}
658 /// Read-write values
659 pub mod RW {
660
661 /// 0b0: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
662 pub const Disabled: u32 = 0b0;
663
664 /// 0b1: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
665 pub const Enabled: u32 = 0b1;
666 }
667 }
668
669 /// OC1FE
670 pub mod OC1FE {
671 /// Offset (2 bits)
672 pub const offset: u32 = 2;
673 /// Mask (1 bit: 1 << 2)
674 pub const mask: u32 = 1 << offset;
675 /// Read-only values (empty)
676 pub mod R {}
677 /// Write-only values (empty)
678 pub mod W {}
679 /// Read-write values
680 pub mod RW {
681
682 /// 0b0: Fast output disabled
683 pub const Disabled: u32 = 0b0;
684
685 /// 0b1: Fast output enabled
686 pub const Enabled: u32 = 0b1;
687 }
688 }
689
690 /// CC1S
691 pub mod CC1S {
692 /// Offset (0 bits)
693 pub const offset: u32 = 0;
694 /// Mask (2 bits: 0b11 << 0)
695 pub const mask: u32 = 0b11 << offset;
696 /// Read-only values (empty)
697 pub mod R {}
698 /// Write-only values (empty)
699 pub mod W {}
700 /// Read-write values
701 pub mod RW {
702
703 /// 0b00: CCx channel is configured as output
704 pub const Output: u32 = 0b00;
705
706 /// 0b01: CCx channel is configured as input, ICx is mapped on TI1
707 pub const TI1: u32 = 0b01;
708 }
709 }
710
711 /// IC1F
712 pub mod IC1F {
713 /// Offset (4 bits)
714 pub const offset: u32 = 4;
715 /// Mask (4 bits: 0b1111 << 4)
716 pub const mask: u32 = 0b1111 << offset;
717 /// Read-only values (empty)
718 pub mod R {}
719 /// Write-only values (empty)
720 pub mod W {}
721 /// Read-write values
722 pub mod RW {
723
724 /// 0b0000: No filter, sampling is done at fDTS
725 pub const NoFilter: u32 = 0b0000;
726
727 /// 0b0001: fSAMPLING=fCK_INT, N=2
728 pub const FCK_INT_N2: u32 = 0b0001;
729
730 /// 0b0010: fSAMPLING=fCK_INT, N=4
731 pub const FCK_INT_N4: u32 = 0b0010;
732
733 /// 0b0011: fSAMPLING=fCK_INT, N=8
734 pub const FCK_INT_N8: u32 = 0b0011;
735
736 /// 0b0100: fSAMPLING=fDTS/2, N=6
737 pub const FDTS_Div2_N6: u32 = 0b0100;
738
739 /// 0b0101: fSAMPLING=fDTS/2, N=8
740 pub const FDTS_Div2_N8: u32 = 0b0101;
741
742 /// 0b0110: fSAMPLING=fDTS/4, N=6
743 pub const FDTS_Div4_N6: u32 = 0b0110;
744
745 /// 0b0111: fSAMPLING=fDTS/4, N=8
746 pub const FDTS_Div4_N8: u32 = 0b0111;
747
748 /// 0b1000: fSAMPLING=fDTS/8, N=6
749 pub const FDTS_Div8_N6: u32 = 0b1000;
750
751 /// 0b1001: fSAMPLING=fDTS/8, N=8
752 pub const FDTS_Div8_N8: u32 = 0b1001;
753
754 /// 0b1010: fSAMPLING=fDTS/16, N=5
755 pub const FDTS_Div16_N5: u32 = 0b1010;
756
757 /// 0b1011: fSAMPLING=fDTS/16, N=6
758 pub const FDTS_Div16_N6: u32 = 0b1011;
759
760 /// 0b1100: fSAMPLING=fDTS/16, N=8
761 pub const FDTS_Div16_N8: u32 = 0b1100;
762
763 /// 0b1101: fSAMPLING=fDTS/32, N=5
764 pub const FDTS_Div32_N5: u32 = 0b1101;
765
766 /// 0b1110: fSAMPLING=fDTS/32, N=6
767 pub const FDTS_Div32_N6: u32 = 0b1110;
768
769 /// 0b1111: fSAMPLING=fDTS/32, N=8
770 pub const FDTS_Div32_N8: u32 = 0b1111;
771 }
772 }
773
774 /// IC1PSC
775 pub mod IC1PSC {
776 /// Offset (2 bits)
777 pub const offset: u32 = 2;
778 /// Mask (2 bits: 0b11 << 2)
779 pub const mask: u32 = 0b11 << offset;
780 /// Read-only values (empty)
781 pub mod R {}
782 /// Write-only values (empty)
783 pub mod W {}
784 /// Read-write values
785 pub mod RW {
786
787 /// 0b00: CCx channel is configured as output
788 pub const Output: u32 = 0b00;
789
790 /// 0b01: Capture is done once every 2 events
791 pub const Capture_2: u32 = 0b01;
792
793 /// 0b10: Capture is done once every 4 events
794 pub const Capture_4: u32 = 0b10;
795
796 /// 0b11: Capture is done once every 8 events
797 pub const Capture_8: u32 = 0b11;
798 }
799 }
800}
801
802/// TIM16/TIM17 capture/compare enable register
803pub mod CCER {
804
805 /// Capture/Compare 1 complementary output polarity
806 pub mod CC1NP {
807 /// Offset (3 bits)
808 pub const offset: u32 = 3;
809 /// Mask (1 bit: 1 << 3)
810 pub const mask: u32 = 1 << offset;
811 /// Read-only values (empty)
812 pub mod R {}
813 /// Write-only values (empty)
814 pub mod W {}
815 /// Read-write values
816 pub mod RW {
817
818 /// 0b0: OCxN active high
819 pub const ActiveHigh: u32 = 0b0;
820
821 /// 0b1: OCxN active low
822 pub const ActiveLow: u32 = 0b1;
823 }
824 }
825
826 /// Capture/Compare 1 complementary output enable
827 pub mod CC1NE {
828 /// Offset (2 bits)
829 pub const offset: u32 = 2;
830 /// Mask (1 bit: 1 << 2)
831 pub const mask: u32 = 1 << offset;
832 /// Read-only values (empty)
833 pub mod R {}
834 /// Write-only values (empty)
835 pub mod W {}
836 /// Read-write values
837 pub mod RW {
838
839 /// 0b0: Complementary output disabled
840 pub const Disabled: u32 = 0b0;
841
842 /// 0b1: Complementary output enabled
843 pub const Enabled: u32 = 0b1;
844 }
845 }
846
847 /// Capture/Compare 1 output polarity
848 pub mod CC1P {
849 /// Offset (1 bits)
850 pub const offset: u32 = 1;
851 /// Mask (1 bit: 1 << 1)
852 pub const mask: u32 = 1 << offset;
853 /// Read-only values (empty)
854 pub mod R {}
855 /// Write-only values (empty)
856 pub mod W {}
857 /// Read-write values
858 pub mod RW {
859
860 /// 0b0: Noninverted/rising edge
861 pub const RisingEdge: u32 = 0b0;
862
863 /// 0b1: Inverted/falling edge
864 pub const FallingEdge: u32 = 0b1;
865 }
866 }
867
868 /// Capture/Compare 1 output enable
869 pub mod CC1E {
870 /// Offset (0 bits)
871 pub const offset: u32 = 0;
872 /// Mask (1 bit: 1 << 0)
873 pub const mask: u32 = 1 << offset;
874 /// Read-only values (empty)
875 pub mod R {}
876 /// Write-only values (empty)
877 pub mod W {}
878 /// Read-write values
879 pub mod RW {
880
881 /// 0b0: Capture disabled
882 pub const Disabled: u32 = 0b0;
883
884 /// 0b1: Capture enabled
885 pub const Enabled: u32 = 0b1;
886 }
887 }
888}
889
890/// TIM16/TIM17 counter
891pub mod CNT {
892
893 /// UIF Copy
894 pub mod UIFCPYorRes {
895 /// Offset (31 bits)
896 pub const offset: u32 = 31;
897 /// Mask (1 bit: 1 << 31)
898 pub const mask: u32 = 1 << offset;
899 /// Read-only values (empty)
900 pub mod R {}
901 /// Write-only values (empty)
902 pub mod W {}
903 /// Read-write values (empty)
904 pub mod RW {}
905 }
906
907 /// CNT
908 pub mod CNT {
909 /// Offset (0 bits)
910 pub const offset: u32 = 0;
911 /// Mask (16 bits: 0xffff << 0)
912 pub const mask: u32 = 0xffff << offset;
913 /// Read-only values (empty)
914 pub mod R {}
915 /// Write-only values (empty)
916 pub mod W {}
917 /// Read-write values (empty)
918 pub mod RW {}
919 }
920}
921
922/// TIM16/TIM17 prescaler
923pub mod PSC {
924
925 /// Prescaler value
926 pub mod PSC {
927 /// Offset (0 bits)
928 pub const offset: u32 = 0;
929 /// Mask (16 bits: 0xffff << 0)
930 pub const mask: u32 = 0xffff << offset;
931 /// Read-only values (empty)
932 pub mod R {}
933 /// Write-only values (empty)
934 pub mod W {}
935 /// Read-write values (empty)
936 pub mod RW {}
937 }
938}
939
940/// TIM16/TIM17 auto-reload register
941pub mod ARR {
942
943 /// Auto-reload value
944 pub mod ARR {
945 /// Offset (0 bits)
946 pub const offset: u32 = 0;
947 /// Mask (16 bits: 0xffff << 0)
948 pub const mask: u32 = 0xffff << offset;
949 /// Read-only values (empty)
950 pub mod R {}
951 /// Write-only values (empty)
952 pub mod W {}
953 /// Read-write values (empty)
954 pub mod RW {}
955 }
956}
957
958/// TIM16/TIM17 repetition counter register
959pub mod RCR {
960
961 /// Repetition counter value
962 pub mod REP {
963 /// Offset (0 bits)
964 pub const offset: u32 = 0;
965 /// Mask (8 bits: 0xff << 0)
966 pub const mask: u32 = 0xff << offset;
967 /// Read-only values (empty)
968 pub mod R {}
969 /// Write-only values (empty)
970 pub mod W {}
971 /// Read-write values (empty)
972 pub mod RW {}
973 }
974}
975
976/// TIM16/TIM17 capture/compare register 1
977pub mod CCR1 {
978
979 /// Capture/Compare 1 value
980 pub mod CCR1 {
981 /// Offset (0 bits)
982 pub const offset: u32 = 0;
983 /// Mask (16 bits: 0xffff << 0)
984 pub const mask: u32 = 0xffff << offset;
985 /// Read-only values (empty)
986 pub mod R {}
987 /// Write-only values (empty)
988 pub mod W {}
989 /// Read-write values (empty)
990 pub mod RW {}
991 }
992}
993
994/// TIM16/TIM17 break and dead-time register
995pub mod BDTR {
996
997 /// Break Bidirectional
998 pub mod BKBID {
999 /// Offset (28 bits)
1000 pub const offset: u32 = 28;
1001 /// Mask (1 bit: 1 << 28)
1002 pub const mask: u32 = 1 << offset;
1003 /// Read-only values (empty)
1004 pub mod R {}
1005 /// Write-only values (empty)
1006 pub mod W {}
1007 /// Read-write values
1008 pub mod RW {
1009
1010 /// 0b0: Break input BRK in input mode
1011 pub const Input: u32 = 0b0;
1012
1013 /// 0b1: Break input BRK in bidirectional mode
1014 pub const Bidirectional: u32 = 0b1;
1015 }
1016 }
1017
1018 /// Break Disarm
1019 pub mod BKDSRM {
1020 /// Offset (26 bits)
1021 pub const offset: u32 = 26;
1022 /// Mask (1 bit: 1 << 26)
1023 pub const mask: u32 = 1 << offset;
1024 /// Read-only values (empty)
1025 pub mod R {}
1026 /// Write-only values (empty)
1027 pub mod W {}
1028 /// Read-write values
1029 pub mod RW {
1030
1031 /// 0b0: Break input BRK is armed
1032 pub const Armed: u32 = 0b0;
1033
1034 /// 0b1: Break input BRK is disarmed
1035 pub const Disarmed: u32 = 0b1;
1036 }
1037 }
1038
1039 /// Main output enable
1040 pub mod MOE {
1041 /// Offset (15 bits)
1042 pub const offset: u32 = 15;
1043 /// Mask (1 bit: 1 << 15)
1044 pub const mask: u32 = 1 << offset;
1045 /// Read-only values (empty)
1046 pub mod R {}
1047 /// Write-only values (empty)
1048 pub mod W {}
1049 /// Read-write values
1050 pub mod RW {
1051
1052 /// 0b0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit
1053 pub const Disabled: u32 = 0b0;
1054
1055 /// 0b1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)
1056 pub const Enabled: u32 = 0b1;
1057 }
1058 }
1059
1060 /// Automatic output enable
1061 pub mod AOE {
1062 /// Offset (14 bits)
1063 pub const offset: u32 = 14;
1064 /// Mask (1 bit: 1 << 14)
1065 pub const mask: u32 = 1 << offset;
1066 /// Read-only values (empty)
1067 pub mod R {}
1068 /// Write-only values (empty)
1069 pub mod W {}
1070 /// Read-write values
1071 pub mod RW {
1072
1073 /// 0b0: MOE can be set only by software
1074 pub const Disabled: u32 = 0b0;
1075
1076 /// 0b1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
1077 pub const Enabled: u32 = 0b1;
1078 }
1079 }
1080
1081 /// Break polarity
1082 pub mod BKP {
1083 /// Offset (13 bits)
1084 pub const offset: u32 = 13;
1085 /// Mask (1 bit: 1 << 13)
1086 pub const mask: u32 = 1 << offset;
1087 /// Read-only values (empty)
1088 pub mod R {}
1089 /// Write-only values (empty)
1090 pub mod W {}
1091 /// Read-write values
1092 pub mod RW {
1093
1094 /// 0b0: Break input BRK is active low
1095 pub const ActiveLow: u32 = 0b0;
1096
1097 /// 0b1: Break input BRK is active high
1098 pub const ActiveHigh: u32 = 0b1;
1099 }
1100 }
1101
1102 /// Break enable
1103 pub mod BKE {
1104 /// Offset (12 bits)
1105 pub const offset: u32 = 12;
1106 /// Mask (1 bit: 1 << 12)
1107 pub const mask: u32 = 1 << offset;
1108 /// Read-only values (empty)
1109 pub mod R {}
1110 /// Write-only values (empty)
1111 pub mod W {}
1112 /// Read-write values
1113 pub mod RW {
1114
1115 /// 0b0: Break inputs (BRK and CCS clock failure event) disabled
1116 pub const Disabled: u32 = 0b0;
1117
1118 /// 0b1: Break inputs (BRK and CCS clock failure event) enabled
1119 pub const Enabled: u32 = 0b1;
1120 }
1121 }
1122
1123 /// Off-state selection for Run mode
1124 pub mod OSSR {
1125 /// Offset (11 bits)
1126 pub const offset: u32 = 11;
1127 /// Mask (1 bit: 1 << 11)
1128 pub const mask: u32 = 1 << offset;
1129 /// Read-only values (empty)
1130 pub mod R {}
1131 /// Write-only values (empty)
1132 pub mod W {}
1133 /// Read-write values
1134 pub mod RW {
1135
1136 /// 0b0: OC/OCN outputs are disabled when inactive
1137 pub const Disabled: u32 = 0b0;
1138
1139 /// 0b1: OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1
1140 pub const Enabled: u32 = 0b1;
1141 }
1142 }
1143
1144 /// Off-state selection for Idle mode
1145 pub mod OSSI {
1146 /// Offset (10 bits)
1147 pub const offset: u32 = 10;
1148 /// Mask (1 bit: 1 << 10)
1149 pub const mask: u32 = 1 << offset;
1150 /// Read-only values (empty)
1151 pub mod R {}
1152 /// Write-only values (empty)
1153 pub mod W {}
1154 /// Read-write values
1155 pub mod RW {
1156
1157 /// 0b0: OC/OCN outputs are disabled when inactive
1158 pub const Disabled: u32 = 0b0;
1159
1160 /// 0b1: OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime
1161 pub const Enabled: u32 = 0b1;
1162 }
1163 }
1164
1165 /// Lock configuration
1166 pub mod LOCK {
1167 /// Offset (8 bits)
1168 pub const offset: u32 = 8;
1169 /// Mask (2 bits: 0b11 << 8)
1170 pub const mask: u32 = 0b11 << offset;
1171 /// Read-only values (empty)
1172 pub mod R {}
1173 /// Write-only values (empty)
1174 pub mod W {}
1175 /// Read-write values
1176 pub mod RW {
1177
1178 /// 0b00: No write protection
1179 pub const Off: u32 = 0b00;
1180
1181 /// 0b01: Level 1 write protection
1182 pub const Level1: u32 = 0b01;
1183
1184 /// 0b10: Level 2 write protection
1185 pub const Level2: u32 = 0b10;
1186
1187 /// 0b11: Level 3 write protection
1188 pub const Level3: u32 = 0b11;
1189 }
1190 }
1191
1192 /// Dead-time generator setup
1193 pub mod DTG {
1194 /// Offset (0 bits)
1195 pub const offset: u32 = 0;
1196 /// Mask (8 bits: 0xff << 0)
1197 pub const mask: u32 = 0xff << offset;
1198 /// Read-only values (empty)
1199 pub mod R {}
1200 /// Write-only values (empty)
1201 pub mod W {}
1202 /// Read-write values (empty)
1203 pub mod RW {}
1204 }
1205}
1206
1207/// TIM16/TIM17 DMA control register
1208pub mod DCR {
1209
1210 /// DMA burst length
1211 pub mod DBL {
1212 /// Offset (8 bits)
1213 pub const offset: u32 = 8;
1214 /// Mask (5 bits: 0b11111 << 8)
1215 pub const mask: u32 = 0b11111 << offset;
1216 /// Read-only values (empty)
1217 pub mod R {}
1218 /// Write-only values (empty)
1219 pub mod W {}
1220 /// Read-write values (empty)
1221 pub mod RW {}
1222 }
1223
1224 /// DMA base address
1225 pub mod DBA {
1226 /// Offset (0 bits)
1227 pub const offset: u32 = 0;
1228 /// Mask (5 bits: 0b11111 << 0)
1229 pub const mask: u32 = 0b11111 << offset;
1230 /// Read-only values (empty)
1231 pub mod R {}
1232 /// Write-only values (empty)
1233 pub mod W {}
1234 /// Read-write values (empty)
1235 pub mod RW {}
1236 }
1237}
1238
1239/// TIM16/TIM17 DMA address for full transfer
1240pub mod DMAR {
1241
1242 /// DMA register for burst accesses
1243 pub mod DMAB {
1244 /// Offset (0 bits)
1245 pub const offset: u32 = 0;
1246 /// Mask (16 bits: 0xffff << 0)
1247 pub const mask: u32 = 0xffff << offset;
1248 /// Read-only values (empty)
1249 pub mod R {}
1250 /// Write-only values (empty)
1251 pub mod W {}
1252 /// Read-write values (empty)
1253 pub mod RW {}
1254 }
1255}
1256
1257/// TIM16 option register 1
1258pub mod OR1 {
1259
1260 /// Timer 17 input 1 connection
1261 pub mod TI1_RMP {
1262 /// Offset (0 bits)
1263 pub const offset: u32 = 0;
1264 /// Mask (2 bits: 0b11 << 0)
1265 pub const mask: u32 = 0b11 << offset;
1266 /// Read-only values (empty)
1267 pub mod R {}
1268 /// Write-only values (empty)
1269 pub mod W {}
1270 /// Read-write values
1271 pub mod RW {
1272
1273 /// 0b00: TI1 is connected to GPIO
1274 pub const GPIO: u32 = 0b00;
1275
1276 /// 0b01: TI1 is connected to LSI
1277 pub const LSI: u32 = 0b01;
1278
1279 /// 0b10: TI1 is connected to LSE
1280 pub const LSE: u32 = 0b10;
1281
1282 /// 0b11: TI1 is connected to RTC wake-up interrupt
1283 pub const RTC: u32 = 0b11;
1284 }
1285 }
1286}
1287
1288/// TIM16 alternate function register 1
1289pub mod AF1 {
1290
1291 /// BRK COMP2 input polarity
1292 pub mod BKCMP2P {
1293 /// Offset (11 bits)
1294 pub const offset: u32 = 11;
1295 /// Mask (1 bit: 1 << 11)
1296 pub const mask: u32 = 1 << offset;
1297 /// Read-only values (empty)
1298 pub mod R {}
1299 /// Write-only values (empty)
1300 pub mod W {}
1301 /// Read-write values
1302 pub mod RW {
1303
1304 /// 0b0: Input polarity not inverted
1305 pub const NotInverted: u32 = 0b0;
1306
1307 /// 0b1: Input polarity inverted
1308 pub const Inverted: u32 = 0b1;
1309 }
1310 }
1311
1312 /// BRK COMP1 input polarity
1313 pub mod BKCMP1P {
1314 /// Offset (10 bits)
1315 pub const offset: u32 = 10;
1316 /// Mask (1 bit: 1 << 10)
1317 pub const mask: u32 = 1 << offset;
1318 /// Read-only values (empty)
1319 pub mod R {}
1320 /// Write-only values (empty)
1321 pub mod W {}
1322 pub use super::BKCMP2P::RW;
1323 }
1324
1325 /// BRK BKIN input polarity
1326 pub mod BKINP {
1327 /// Offset (9 bits)
1328 pub const offset: u32 = 9;
1329 /// Mask (1 bit: 1 << 9)
1330 pub const mask: u32 = 1 << offset;
1331 /// Read-only values (empty)
1332 pub mod R {}
1333 /// Write-only values (empty)
1334 pub mod W {}
1335 pub use super::BKCMP2P::RW;
1336 }
1337
1338 /// BRK COMP2 enable
1339 pub mod BKCMP2E {
1340 /// Offset (2 bits)
1341 pub const offset: u32 = 2;
1342 /// Mask (1 bit: 1 << 2)
1343 pub const mask: u32 = 1 << offset;
1344 /// Read-only values (empty)
1345 pub mod R {}
1346 /// Write-only values (empty)
1347 pub mod W {}
1348 /// Read-write values
1349 pub mod RW {
1350
1351 /// 0b0: COMP2 input disabled
1352 pub const Disabled: u32 = 0b0;
1353
1354 /// 0b1: COMP2 input enabled
1355 pub const Enabled: u32 = 0b1;
1356 }
1357 }
1358
1359 /// BRK COMP1 enable
1360 pub mod BKCMP1E {
1361 /// Offset (1 bits)
1362 pub const offset: u32 = 1;
1363 /// Mask (1 bit: 1 << 1)
1364 pub const mask: u32 = 1 << offset;
1365 /// Read-only values (empty)
1366 pub mod R {}
1367 /// Write-only values (empty)
1368 pub mod W {}
1369 /// Read-write values
1370 pub mod RW {
1371
1372 /// 0b0: COMP1 input disabled
1373 pub const Disabled: u32 = 0b0;
1374
1375 /// 0b1: COMP1 input enabled
1376 pub const Enabled: u32 = 0b1;
1377 }
1378 }
1379
1380 /// BRK BKIN input enable
1381 pub mod BKINE {
1382 /// Offset (0 bits)
1383 pub const offset: u32 = 0;
1384 /// Mask (1 bit: 1 << 0)
1385 pub const mask: u32 = 1 << offset;
1386 /// Read-only values (empty)
1387 pub mod R {}
1388 /// Write-only values (empty)
1389 pub mod W {}
1390 /// Read-write values
1391 pub mod RW {
1392
1393 /// 0b0: BKIN input disabled
1394 pub const Disabled: u32 = 0b0;
1395
1396 /// 0b1: BKIN input enabled
1397 pub const Enabled: u32 = 0b1;
1398 }
1399 }
1400}
1401
1402/// TIM16 input selection register
1403pub mod TISEL {
1404
1405 /// TISEL
1406 pub mod TISEL {
1407 /// Offset (0 bits)
1408 pub const offset: u32 = 0;
1409 /// Mask (4 bits: 0b1111 << 0)
1410 pub const mask: u32 = 0b1111 << offset;
1411 /// Read-only values (empty)
1412 pub mod R {}
1413 /// Write-only values (empty)
1414 pub mod W {}
1415 /// Read-write values
1416 pub mod RW {
1417
1418 /// 0b0000: TIM1_CH1 input selected
1419 pub const Selected: u32 = 0b0000;
1420 }
1421 }
1422}
1423#[repr(C)]
1424pub struct RegisterBlock {
1425 /// TIM16/TIM17 control register 1
1426 pub CR1: RWRegister<u32>,
1427
1428 /// TIM16/TIM17 control register 2
1429 pub CR2: RWRegister<u32>,
1430
1431 _reserved1: [u8; 4],
1432
1433 /// TIM16/TIM17 DMA/interrupt enable register
1434 pub DIER: RWRegister<u32>,
1435
1436 /// TIM16/TIM17 status register
1437 pub SR: RWRegister<u32>,
1438
1439 /// TIM16/TIM17 event generation register
1440 pub EGR: WORegister<u32>,
1441
1442 /// CCMR1_Output and CCMR1_Input
1443 /// CCMR1_Output: TIM16/TIM17 capture/compare mode register 1
1444 /// CCMR1_Input: TIM16/TIM17 capture/compare mode register 1
1445 pub CCMR1: RWRegister<u32>,
1446
1447 _reserved2: [u8; 4],
1448
1449 /// TIM16/TIM17 capture/compare enable register
1450 pub CCER: RWRegister<u32>,
1451
1452 /// TIM16/TIM17 counter
1453 pub CNT: RWRegister<u32>,
1454
1455 /// TIM16/TIM17 prescaler
1456 pub PSC: RWRegister<u32>,
1457
1458 /// TIM16/TIM17 auto-reload register
1459 pub ARR: RWRegister<u32>,
1460
1461 /// TIM16/TIM17 repetition counter register
1462 pub RCR: RWRegister<u32>,
1463
1464 /// TIM16/TIM17 capture/compare register 1
1465 pub CCR1: RWRegister<u32>,
1466
1467 _reserved3: [u8; 12],
1468
1469 /// TIM16/TIM17 break and dead-time register
1470 pub BDTR: RWRegister<u32>,
1471
1472 /// TIM16/TIM17 DMA control register
1473 pub DCR: RWRegister<u32>,
1474
1475 /// TIM16/TIM17 DMA address for full transfer
1476 pub DMAR: RWRegister<u32>,
1477
1478 /// TIM16 option register 1
1479 pub OR1: RWRegister<u32>,
1480
1481 _reserved4: [u8; 12],
1482
1483 /// TIM16 alternate function register 1
1484 pub AF1: RWRegister<u32>,
1485
1486 _reserved5: [u8; 4],
1487
1488 /// TIM16 input selection register
1489 pub TISEL: RWRegister<u32>,
1490}
1491pub struct ResetValues {
1492 pub CR1: u32,
1493 pub CR2: u32,
1494 pub DIER: u32,
1495 pub SR: u32,
1496 pub EGR: u32,
1497 pub CCMR1: u32,
1498 pub CCER: u32,
1499 pub CNT: u32,
1500 pub PSC: u32,
1501 pub ARR: u32,
1502 pub RCR: u32,
1503 pub CCR1: u32,
1504 pub BDTR: u32,
1505 pub DCR: u32,
1506 pub DMAR: u32,
1507 pub OR1: u32,
1508 pub AF1: u32,
1509 pub TISEL: u32,
1510}
1511#[cfg(not(feature = "nosync"))]
1512pub struct Instance {
1513 pub(crate) addr: u32,
1514 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1515}
1516#[cfg(not(feature = "nosync"))]
1517impl ::core::ops::Deref for Instance {
1518 type Target = RegisterBlock;
1519 #[inline(always)]
1520 fn deref(&self) -> &RegisterBlock {
1521 unsafe { &*(self.addr as *const _) }
1522 }
1523}
1524#[cfg(feature = "rtic")]
1525unsafe impl Send for Instance {}