stm32ral/stm32wl/peripherals/gpioh.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General-purpose I/Os
4//!
5//! Used by: stm32wl5x_cm0p, stm32wl5x_cm4, stm32wle5
6
7use crate::{RORegister, RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// GPIO port mode register
12pub mod MODER {
13
14 /// Port x configuration bits (y = 0..15)
15 pub mod MODER3 {
16 /// Offset (6 bits)
17 pub const offset: u32 = 6;
18 /// Mask (2 bits: 0b11 << 6)
19 pub const mask: u32 = 0b11 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b00: Input mode (reset state)
28 pub const Input: u32 = 0b00;
29
30 /// 0b01: General purpose output mode
31 pub const Output: u32 = 0b01;
32
33 /// 0b10: Alternate function mode
34 pub const Alternate: u32 = 0b10;
35
36 /// 0b11: Analog mode
37 pub const Analog: u32 = 0b11;
38 }
39 }
40}
41
42/// GPIO port output type register
43pub mod OTYPER {
44
45 /// Port x configuration bits (y = 0..15)
46 pub mod OT3 {
47 /// Offset (3 bits)
48 pub const offset: u32 = 3;
49 /// Mask (1 bit: 1 << 3)
50 pub const mask: u32 = 1 << offset;
51 /// Read-only values (empty)
52 pub mod R {}
53 /// Write-only values (empty)
54 pub mod W {}
55 /// Read-write values
56 pub mod RW {
57
58 /// 0b0: Output push-pull (reset state)
59 pub const PushPull: u32 = 0b0;
60
61 /// 0b1: Output open-drain
62 pub const OpenDrain: u32 = 0b1;
63 }
64 }
65}
66
67/// GPIO port output speed register
68pub mod OSPEEDR {
69
70 /// Port x configuration bits (y = 0..15)
71 pub mod OSPEEDR3 {
72 /// Offset (6 bits)
73 pub const offset: u32 = 6;
74 /// Mask (2 bits: 0b11 << 6)
75 pub const mask: u32 = 0b11 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values
81 pub mod RW {
82
83 /// 0b00: Low speed
84 pub const LowSpeed: u32 = 0b00;
85
86 /// 0b01: Medium speed
87 pub const MediumSpeed: u32 = 0b01;
88
89 /// 0b10: High speed
90 pub const HighSpeed: u32 = 0b10;
91
92 /// 0b11: Very high speed
93 pub const VeryHighSpeed: u32 = 0b11;
94 }
95 }
96}
97
98/// GPIO port pull-up/pull-down register
99pub mod PUPDR {
100
101 /// Port x configuration bits (y = 0..15)
102 pub mod PUPDR3 {
103 /// Offset (6 bits)
104 pub const offset: u32 = 6;
105 /// Mask (2 bits: 0b11 << 6)
106 pub const mask: u32 = 0b11 << offset;
107 /// Read-only values (empty)
108 pub mod R {}
109 /// Write-only values (empty)
110 pub mod W {}
111 /// Read-write values
112 pub mod RW {
113
114 /// 0b00: No pull-up, pull-down
115 pub const Floating: u32 = 0b00;
116
117 /// 0b01: Pull-up
118 pub const PullUp: u32 = 0b01;
119
120 /// 0b10: Pull-down
121 pub const PullDown: u32 = 0b10;
122 }
123 }
124}
125
126/// GPIO port input data register
127pub mod IDR {
128
129 /// Port input data (y = 0..15)
130 pub mod IDR3 {
131 /// Offset (3 bits)
132 pub const offset: u32 = 3;
133 /// Mask (1 bit: 1 << 3)
134 pub const mask: u32 = 1 << offset;
135 /// Read-only values
136 pub mod R {
137
138 /// 0b0: Input is logic low
139 pub const Low: u32 = 0b0;
140
141 /// 0b1: Input is logic high
142 pub const High: u32 = 0b1;
143 }
144 /// Write-only values (empty)
145 pub mod W {}
146 /// Read-write values (empty)
147 pub mod RW {}
148 }
149}
150
151/// GPIO port output data register
152pub mod ODR {
153
154 /// Port output data (y = 0..15)
155 pub mod ODR3 {
156 /// Offset (3 bits)
157 pub const offset: u32 = 3;
158 /// Mask (1 bit: 1 << 3)
159 pub const mask: u32 = 1 << offset;
160 /// Read-only values (empty)
161 pub mod R {}
162 /// Write-only values (empty)
163 pub mod W {}
164 /// Read-write values
165 pub mod RW {
166
167 /// 0b0: Set output to logic low
168 pub const Low: u32 = 0b0;
169
170 /// 0b1: Set output to logic high
171 pub const High: u32 = 0b1;
172 }
173 }
174}
175
176/// GPIO port bit set/reset register
177pub mod BSRR {
178
179 /// Port x reset bit y (y = 0..15)
180 pub mod BR3 {
181 /// Offset (19 bits)
182 pub const offset: u32 = 19;
183 /// Mask (1 bit: 1 << 19)
184 pub const mask: u32 = 1 << offset;
185 /// Read-only values (empty)
186 pub mod R {}
187 /// Write-only values
188 pub mod W {
189
190 /// 0b1: Resets the corresponding ODRx bit
191 pub const Reset: u32 = 0b1;
192 }
193 /// Read-write values (empty)
194 pub mod RW {}
195 }
196
197 /// Port x set bit y (y= 0..15)
198 pub mod BS3 {
199 /// Offset (3 bits)
200 pub const offset: u32 = 3;
201 /// Mask (1 bit: 1 << 3)
202 pub const mask: u32 = 1 << offset;
203 /// Read-only values (empty)
204 pub mod R {}
205 /// Write-only values
206 pub mod W {
207
208 /// 0b1: Sets the corresponding ODRx bit
209 pub const Set: u32 = 0b1;
210 }
211 /// Read-write values (empty)
212 pub mod RW {}
213 }
214}
215
216/// GPIO port configuration lock register
217pub mod LCKR {
218
219 /// Port x lock bit y (y= 0..15)
220 pub mod LCKK {
221 /// Offset (16 bits)
222 pub const offset: u32 = 16;
223 /// Mask (1 bit: 1 << 16)
224 pub const mask: u32 = 1 << offset;
225 /// Read-only values (empty)
226 pub mod R {}
227 /// Write-only values (empty)
228 pub mod W {}
229 /// Read-write values
230 pub mod RW {
231
232 /// 0b0: Port configuration lock key not active
233 pub const NotActive: u32 = 0b0;
234
235 /// 0b1: Port configuration lock key active
236 pub const Active: u32 = 0b1;
237 }
238 }
239
240 /// Port x lock bit y (y= 0..15)
241 pub mod LCK3 {
242 /// Offset (3 bits)
243 pub const offset: u32 = 3;
244 /// Mask (1 bit: 1 << 3)
245 pub const mask: u32 = 1 << offset;
246 /// Read-only values (empty)
247 pub mod R {}
248 /// Write-only values (empty)
249 pub mod W {}
250 /// Read-write values
251 pub mod RW {
252
253 /// 0b0: Port configuration not locked
254 pub const Unlocked: u32 = 0b0;
255
256 /// 0b1: Port configuration locked
257 pub const Locked: u32 = 0b1;
258 }
259 }
260}
261
262/// GPIO alternate function low register
263pub mod AFRL {
264
265 /// Alternate function selection for port x bit y (y = 0..7)
266 pub mod AFRL3 {
267 /// Offset (12 bits)
268 pub const offset: u32 = 12;
269 /// Mask (4 bits: 0b1111 << 12)
270 pub const mask: u32 = 0b1111 << offset;
271 /// Read-only values (empty)
272 pub mod R {}
273 /// Write-only values (empty)
274 pub mod W {}
275 /// Read-write values
276 pub mod RW {
277
278 /// 0b0000: AF0
279 pub const AF0: u32 = 0b0000;
280
281 /// 0b0001: AF1
282 pub const AF1: u32 = 0b0001;
283
284 /// 0b0010: AF2
285 pub const AF2: u32 = 0b0010;
286
287 /// 0b0011: AF3
288 pub const AF3: u32 = 0b0011;
289
290 /// 0b0100: AF4
291 pub const AF4: u32 = 0b0100;
292
293 /// 0b0101: AF5
294 pub const AF5: u32 = 0b0101;
295
296 /// 0b0110: AF6
297 pub const AF6: u32 = 0b0110;
298
299 /// 0b0111: AF7
300 pub const AF7: u32 = 0b0111;
301
302 /// 0b1000: AF8
303 pub const AF8: u32 = 0b1000;
304
305 /// 0b1001: AF9
306 pub const AF9: u32 = 0b1001;
307
308 /// 0b1010: AF10
309 pub const AF10: u32 = 0b1010;
310
311 /// 0b1011: AF11
312 pub const AF11: u32 = 0b1011;
313
314 /// 0b1100: AF12
315 pub const AF12: u32 = 0b1100;
316
317 /// 0b1101: AF13
318 pub const AF13: u32 = 0b1101;
319
320 /// 0b1110: AF14
321 pub const AF14: u32 = 0b1110;
322
323 /// 0b1111: AF15
324 pub const AF15: u32 = 0b1111;
325 }
326 }
327}
328
329/// GPIO alternate function high register
330pub mod AFRH {
331
332 /// Alternate function selection for port x bit y (y = 8..15)
333 pub mod AFRH15 {
334 /// Offset (28 bits)
335 pub const offset: u32 = 28;
336 /// Mask (4 bits: 0b1111 << 28)
337 pub const mask: u32 = 0b1111 << offset;
338 /// Read-only values (empty)
339 pub mod R {}
340 /// Write-only values (empty)
341 pub mod W {}
342 /// Read-write values
343 pub mod RW {
344
345 /// 0b0000: AF0
346 pub const AF0: u32 = 0b0000;
347
348 /// 0b0001: AF1
349 pub const AF1: u32 = 0b0001;
350
351 /// 0b0010: AF2
352 pub const AF2: u32 = 0b0010;
353
354 /// 0b0011: AF3
355 pub const AF3: u32 = 0b0011;
356
357 /// 0b0100: AF4
358 pub const AF4: u32 = 0b0100;
359
360 /// 0b0101: AF5
361 pub const AF5: u32 = 0b0101;
362
363 /// 0b0110: AF6
364 pub const AF6: u32 = 0b0110;
365
366 /// 0b0111: AF7
367 pub const AF7: u32 = 0b0111;
368
369 /// 0b1000: AF8
370 pub const AF8: u32 = 0b1000;
371
372 /// 0b1001: AF9
373 pub const AF9: u32 = 0b1001;
374
375 /// 0b1010: AF10
376 pub const AF10: u32 = 0b1010;
377
378 /// 0b1011: AF11
379 pub const AF11: u32 = 0b1011;
380
381 /// 0b1100: AF12
382 pub const AF12: u32 = 0b1100;
383
384 /// 0b1101: AF13
385 pub const AF13: u32 = 0b1101;
386
387 /// 0b1110: AF14
388 pub const AF14: u32 = 0b1110;
389
390 /// 0b1111: AF15
391 pub const AF15: u32 = 0b1111;
392 }
393 }
394
395 /// Alternate function selection for port x bit y (y = 8..15)
396 pub mod AFRH14 {
397 /// Offset (24 bits)
398 pub const offset: u32 = 24;
399 /// Mask (4 bits: 0b1111 << 24)
400 pub const mask: u32 = 0b1111 << offset;
401 /// Read-only values (empty)
402 pub mod R {}
403 /// Write-only values (empty)
404 pub mod W {}
405 pub use super::AFRH15::RW;
406 }
407
408 /// Alternate function selection for port x bit y (y = 8..15)
409 pub mod AFRH13 {
410 /// Offset (20 bits)
411 pub const offset: u32 = 20;
412 /// Mask (4 bits: 0b1111 << 20)
413 pub const mask: u32 = 0b1111 << offset;
414 /// Read-only values (empty)
415 pub mod R {}
416 /// Write-only values (empty)
417 pub mod W {}
418 pub use super::AFRH15::RW;
419 }
420
421 /// Alternate function selection for port x bit y (y = 8..15)
422 pub mod AFRH12 {
423 /// Offset (16 bits)
424 pub const offset: u32 = 16;
425 /// Mask (4 bits: 0b1111 << 16)
426 pub const mask: u32 = 0b1111 << offset;
427 /// Read-only values (empty)
428 pub mod R {}
429 /// Write-only values (empty)
430 pub mod W {}
431 pub use super::AFRH15::RW;
432 }
433
434 /// Alternate function selection for port x bit y (y = 8..15)
435 pub mod AFRH11 {
436 /// Offset (12 bits)
437 pub const offset: u32 = 12;
438 /// Mask (4 bits: 0b1111 << 12)
439 pub const mask: u32 = 0b1111 << offset;
440 /// Read-only values (empty)
441 pub mod R {}
442 /// Write-only values (empty)
443 pub mod W {}
444 pub use super::AFRH15::RW;
445 }
446
447 /// Alternate function selection for port x bit y (y = 8..15)
448 pub mod AFRH10 {
449 /// Offset (8 bits)
450 pub const offset: u32 = 8;
451 /// Mask (4 bits: 0b1111 << 8)
452 pub const mask: u32 = 0b1111 << offset;
453 /// Read-only values (empty)
454 pub mod R {}
455 /// Write-only values (empty)
456 pub mod W {}
457 pub use super::AFRH15::RW;
458 }
459
460 /// Alternate function selection for port x bit y (y = 8..15)
461 pub mod AFRH9 {
462 /// Offset (4 bits)
463 pub const offset: u32 = 4;
464 /// Mask (4 bits: 0b1111 << 4)
465 pub const mask: u32 = 0b1111 << offset;
466 /// Read-only values (empty)
467 pub mod R {}
468 /// Write-only values (empty)
469 pub mod W {}
470 pub use super::AFRH15::RW;
471 }
472
473 /// Alternate function selection for port x bit y (y = 8..15)
474 pub mod AFRH8 {
475 /// Offset (0 bits)
476 pub const offset: u32 = 0;
477 /// Mask (4 bits: 0b1111 << 0)
478 pub const mask: u32 = 0b1111 << offset;
479 /// Read-only values (empty)
480 pub mod R {}
481 /// Write-only values (empty)
482 pub mod W {}
483 pub use super::AFRH15::RW;
484 }
485}
486
487/// GPIO port bit reset register
488pub mod BRR {
489
490 /// Port Reset bit
491 pub mod BR3 {
492 /// Offset (3 bits)
493 pub const offset: u32 = 3;
494 /// Mask (1 bit: 1 << 3)
495 pub const mask: u32 = 1 << offset;
496 /// Read-only values (empty)
497 pub mod R {}
498 /// Write-only values
499 pub mod W {
500
501 /// 0b0: No action on the corresponding ODx bit
502 pub const NoAction: u32 = 0b0;
503
504 /// 0b1: Reset the ODx bit
505 pub const Reset: u32 = 0b1;
506 }
507 /// Read-write values (empty)
508 pub mod RW {}
509 }
510}
511#[repr(C)]
512pub struct RegisterBlock {
513 /// GPIO port mode register
514 pub MODER: RWRegister<u32>,
515
516 /// GPIO port output type register
517 pub OTYPER: RWRegister<u32>,
518
519 /// GPIO port output speed register
520 pub OSPEEDR: RWRegister<u32>,
521
522 /// GPIO port pull-up/pull-down register
523 pub PUPDR: RWRegister<u32>,
524
525 /// GPIO port input data register
526 pub IDR: RORegister<u32>,
527
528 /// GPIO port output data register
529 pub ODR: RWRegister<u32>,
530
531 /// GPIO port bit set/reset register
532 pub BSRR: WORegister<u32>,
533
534 /// GPIO port configuration lock register
535 pub LCKR: RWRegister<u32>,
536
537 /// GPIO alternate function low register
538 pub AFRL: RWRegister<u32>,
539
540 /// GPIO alternate function high register
541 pub AFRH: RWRegister<u32>,
542
543 /// GPIO port bit reset register
544 pub BRR: RWRegister<u32>,
545}
546pub struct ResetValues {
547 pub MODER: u32,
548 pub OTYPER: u32,
549 pub OSPEEDR: u32,
550 pub PUPDR: u32,
551 pub IDR: u32,
552 pub ODR: u32,
553 pub BSRR: u32,
554 pub LCKR: u32,
555 pub AFRL: u32,
556 pub AFRH: u32,
557 pub BRR: u32,
558}
559#[cfg(not(feature = "nosync"))]
560pub struct Instance {
561 pub(crate) addr: u32,
562 pub(crate) _marker: PhantomData<*const RegisterBlock>,
563}
564#[cfg(not(feature = "nosync"))]
565impl ::core::ops::Deref for Instance {
566 type Target = RegisterBlock;
567 #[inline(always)]
568 fn deref(&self) -> &RegisterBlock {
569 unsafe { &*(self.addr as *const _) }
570 }
571}
572#[cfg(feature = "rtic")]
573unsafe impl Send for Instance {}