stm32ral/stm32wb/stm32wb55/tim2.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General-purpose-timers
4
5use crate::{RWRegister, WORegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// control register 1
10pub mod CR1 {
11
12 /// UIF status bit remapping
13 pub mod UIFREMAP {
14 /// Offset (11 bits)
15 pub const offset: u32 = 11;
16 /// Mask (1 bit: 1 << 11)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25
26 /// Clock division
27 pub mod CKD {
28 /// Offset (8 bits)
29 pub const offset: u32 = 8;
30 /// Mask (2 bits: 0b11 << 8)
31 pub const mask: u32 = 0b11 << offset;
32 /// Read-only values (empty)
33 pub mod R {}
34 /// Write-only values (empty)
35 pub mod W {}
36 /// Read-write values (empty)
37 pub mod RW {}
38 }
39
40 /// Auto-reload preload enable
41 pub mod ARPE {
42 /// Offset (7 bits)
43 pub const offset: u32 = 7;
44 /// Mask (1 bit: 1 << 7)
45 pub const mask: u32 = 1 << offset;
46 /// Read-only values (empty)
47 pub mod R {}
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53
54 /// Center-aligned mode selection
55 pub mod CMS {
56 /// Offset (5 bits)
57 pub const offset: u32 = 5;
58 /// Mask (2 bits: 0b11 << 5)
59 pub const mask: u32 = 0b11 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// Direction
69 pub mod DIR {
70 /// Offset (4 bits)
71 pub const offset: u32 = 4;
72 /// Mask (1 bit: 1 << 4)
73 pub const mask: u32 = 1 << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// One-pulse mode
83 pub mod OPM {
84 /// Offset (3 bits)
85 pub const offset: u32 = 3;
86 /// Mask (1 bit: 1 << 3)
87 pub const mask: u32 = 1 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 /// Read-write values (empty)
93 pub mod RW {}
94 }
95
96 /// Update request source
97 pub mod URS {
98 /// Offset (2 bits)
99 pub const offset: u32 = 2;
100 /// Mask (1 bit: 1 << 2)
101 pub const mask: u32 = 1 << offset;
102 /// Read-only values (empty)
103 pub mod R {}
104 /// Write-only values (empty)
105 pub mod W {}
106 /// Read-write values (empty)
107 pub mod RW {}
108 }
109
110 /// Update disable
111 pub mod UDIS {
112 /// Offset (1 bits)
113 pub const offset: u32 = 1;
114 /// Mask (1 bit: 1 << 1)
115 pub const mask: u32 = 1 << offset;
116 /// Read-only values (empty)
117 pub mod R {}
118 /// Write-only values (empty)
119 pub mod W {}
120 /// Read-write values (empty)
121 pub mod RW {}
122 }
123
124 /// Counter enable
125 pub mod CEN {
126 /// Offset (0 bits)
127 pub const offset: u32 = 0;
128 /// Mask (1 bit: 1 << 0)
129 pub const mask: u32 = 1 << offset;
130 /// Read-only values (empty)
131 pub mod R {}
132 /// Write-only values (empty)
133 pub mod W {}
134 /// Read-write values (empty)
135 pub mod RW {}
136 }
137}
138
139/// control register 2
140pub mod CR2 {
141
142 /// TI1 selection
143 pub mod TI1S {
144 /// Offset (7 bits)
145 pub const offset: u32 = 7;
146 /// Mask (1 bit: 1 << 7)
147 pub const mask: u32 = 1 << offset;
148 /// Read-only values (empty)
149 pub mod R {}
150 /// Write-only values (empty)
151 pub mod W {}
152 /// Read-write values (empty)
153 pub mod RW {}
154 }
155
156 /// Master mode selection
157 pub mod MMS {
158 /// Offset (4 bits)
159 pub const offset: u32 = 4;
160 /// Mask (3 bits: 0b111 << 4)
161 pub const mask: u32 = 0b111 << offset;
162 /// Read-only values (empty)
163 pub mod R {}
164 /// Write-only values (empty)
165 pub mod W {}
166 /// Read-write values (empty)
167 pub mod RW {}
168 }
169
170 /// Capture/compare DMA selection
171 pub mod CCDS {
172 /// Offset (3 bits)
173 pub const offset: u32 = 3;
174 /// Mask (1 bit: 1 << 3)
175 pub const mask: u32 = 1 << offset;
176 /// Read-only values (empty)
177 pub mod R {}
178 /// Write-only values (empty)
179 pub mod W {}
180 /// Read-write values (empty)
181 pub mod RW {}
182 }
183}
184
185/// slave mode control register
186pub mod SMCR {
187
188 /// Slave mode selection - bit 3
189 pub mod SMS_3 {
190 /// Offset (16 bits)
191 pub const offset: u32 = 16;
192 /// Mask (1 bit: 1 << 16)
193 pub const mask: u32 = 1 << offset;
194 /// Read-only values (empty)
195 pub mod R {}
196 /// Write-only values (empty)
197 pub mod W {}
198 /// Read-write values (empty)
199 pub mod RW {}
200 }
201
202 /// External trigger polarity
203 pub mod ETP {
204 /// Offset (15 bits)
205 pub const offset: u32 = 15;
206 /// Mask (1 bit: 1 << 15)
207 pub const mask: u32 = 1 << offset;
208 /// Read-only values (empty)
209 pub mod R {}
210 /// Write-only values (empty)
211 pub mod W {}
212 /// Read-write values (empty)
213 pub mod RW {}
214 }
215
216 /// External clock enable
217 pub mod ECE {
218 /// Offset (14 bits)
219 pub const offset: u32 = 14;
220 /// Mask (1 bit: 1 << 14)
221 pub const mask: u32 = 1 << offset;
222 /// Read-only values (empty)
223 pub mod R {}
224 /// Write-only values (empty)
225 pub mod W {}
226 /// Read-write values (empty)
227 pub mod RW {}
228 }
229
230 /// External trigger prescaler
231 pub mod ETPS {
232 /// Offset (12 bits)
233 pub const offset: u32 = 12;
234 /// Mask (2 bits: 0b11 << 12)
235 pub const mask: u32 = 0b11 << offset;
236 /// Read-only values (empty)
237 pub mod R {}
238 /// Write-only values (empty)
239 pub mod W {}
240 /// Read-write values (empty)
241 pub mod RW {}
242 }
243
244 /// External trigger filter
245 pub mod ETF {
246 /// Offset (8 bits)
247 pub const offset: u32 = 8;
248 /// Mask (4 bits: 0b1111 << 8)
249 pub const mask: u32 = 0b1111 << offset;
250 /// Read-only values (empty)
251 pub mod R {}
252 /// Write-only values (empty)
253 pub mod W {}
254 /// Read-write values (empty)
255 pub mod RW {}
256 }
257
258 /// Master/Slave mode
259 pub mod MSM {
260 /// Offset (7 bits)
261 pub const offset: u32 = 7;
262 /// Mask (1 bit: 1 << 7)
263 pub const mask: u32 = 1 << offset;
264 /// Read-only values (empty)
265 pub mod R {}
266 /// Write-only values (empty)
267 pub mod W {}
268 /// Read-write values (empty)
269 pub mod RW {}
270 }
271
272 /// Trigger selection
273 pub mod TS {
274 /// Offset (4 bits)
275 pub const offset: u32 = 4;
276 /// Mask (3 bits: 0b111 << 4)
277 pub const mask: u32 = 0b111 << offset;
278 /// Read-only values (empty)
279 pub mod R {}
280 /// Write-only values (empty)
281 pub mod W {}
282 /// Read-write values (empty)
283 pub mod RW {}
284 }
285
286 /// OCREF clear selection
287 pub mod OCCS {
288 /// Offset (3 bits)
289 pub const offset: u32 = 3;
290 /// Mask (1 bit: 1 << 3)
291 pub const mask: u32 = 1 << offset;
292 /// Read-only values (empty)
293 pub mod R {}
294 /// Write-only values (empty)
295 pub mod W {}
296 /// Read-write values (empty)
297 pub mod RW {}
298 }
299
300 /// Slave mode selection
301 pub mod SMS {
302 /// Offset (0 bits)
303 pub const offset: u32 = 0;
304 /// Mask (3 bits: 0b111 << 0)
305 pub const mask: u32 = 0b111 << offset;
306 /// Read-only values (empty)
307 pub mod R {}
308 /// Write-only values (empty)
309 pub mod W {}
310 /// Read-write values (empty)
311 pub mod RW {}
312 }
313}
314
315/// DMA/Interrupt enable register
316pub mod DIER {
317
318 /// Capture/Compare 4 DMA request enable
319 pub mod CC4DE {
320 /// Offset (12 bits)
321 pub const offset: u32 = 12;
322 /// Mask (1 bit: 1 << 12)
323 pub const mask: u32 = 1 << offset;
324 /// Read-only values (empty)
325 pub mod R {}
326 /// Write-only values (empty)
327 pub mod W {}
328 /// Read-write values (empty)
329 pub mod RW {}
330 }
331
332 /// Capture/Compare 3 DMA request enable
333 pub mod CC3DE {
334 /// Offset (11 bits)
335 pub const offset: u32 = 11;
336 /// Mask (1 bit: 1 << 11)
337 pub const mask: u32 = 1 << offset;
338 /// Read-only values (empty)
339 pub mod R {}
340 /// Write-only values (empty)
341 pub mod W {}
342 /// Read-write values (empty)
343 pub mod RW {}
344 }
345
346 /// Capture/Compare 2 DMA request enable
347 pub mod CC2DE {
348 /// Offset (10 bits)
349 pub const offset: u32 = 10;
350 /// Mask (1 bit: 1 << 10)
351 pub const mask: u32 = 1 << offset;
352 /// Read-only values (empty)
353 pub mod R {}
354 /// Write-only values (empty)
355 pub mod W {}
356 /// Read-write values (empty)
357 pub mod RW {}
358 }
359
360 /// Capture/Compare 1 DMA request enable
361 pub mod CC1DE {
362 /// Offset (9 bits)
363 pub const offset: u32 = 9;
364 /// Mask (1 bit: 1 << 9)
365 pub const mask: u32 = 1 << offset;
366 /// Read-only values (empty)
367 pub mod R {}
368 /// Write-only values (empty)
369 pub mod W {}
370 /// Read-write values (empty)
371 pub mod RW {}
372 }
373
374 /// Update DMA request enable
375 pub mod UDE {
376 /// Offset (8 bits)
377 pub const offset: u32 = 8;
378 /// Mask (1 bit: 1 << 8)
379 pub const mask: u32 = 1 << offset;
380 /// Read-only values (empty)
381 pub mod R {}
382 /// Write-only values (empty)
383 pub mod W {}
384 /// Read-write values (empty)
385 pub mod RW {}
386 }
387
388 /// Trigger interrupt enable
389 pub mod TIE {
390 /// Offset (6 bits)
391 pub const offset: u32 = 6;
392 /// Mask (1 bit: 1 << 6)
393 pub const mask: u32 = 1 << offset;
394 /// Read-only values (empty)
395 pub mod R {}
396 /// Write-only values (empty)
397 pub mod W {}
398 /// Read-write values (empty)
399 pub mod RW {}
400 }
401
402 /// Capture/Compare 4 interrupt enable
403 pub mod CC4IE {
404 /// Offset (4 bits)
405 pub const offset: u32 = 4;
406 /// Mask (1 bit: 1 << 4)
407 pub const mask: u32 = 1 << offset;
408 /// Read-only values (empty)
409 pub mod R {}
410 /// Write-only values (empty)
411 pub mod W {}
412 /// Read-write values (empty)
413 pub mod RW {}
414 }
415
416 /// Capture/Compare 3 interrupt enable
417 pub mod CC3IE {
418 /// Offset (3 bits)
419 pub const offset: u32 = 3;
420 /// Mask (1 bit: 1 << 3)
421 pub const mask: u32 = 1 << offset;
422 /// Read-only values (empty)
423 pub mod R {}
424 /// Write-only values (empty)
425 pub mod W {}
426 /// Read-write values (empty)
427 pub mod RW {}
428 }
429
430 /// Capture/Compare 2 interrupt enable
431 pub mod CC2IE {
432 /// Offset (2 bits)
433 pub const offset: u32 = 2;
434 /// Mask (1 bit: 1 << 2)
435 pub const mask: u32 = 1 << offset;
436 /// Read-only values (empty)
437 pub mod R {}
438 /// Write-only values (empty)
439 pub mod W {}
440 /// Read-write values (empty)
441 pub mod RW {}
442 }
443
444 /// Capture/Compare 1 interrupt enable
445 pub mod CC1IE {
446 /// Offset (1 bits)
447 pub const offset: u32 = 1;
448 /// Mask (1 bit: 1 << 1)
449 pub const mask: u32 = 1 << offset;
450 /// Read-only values (empty)
451 pub mod R {}
452 /// Write-only values (empty)
453 pub mod W {}
454 /// Read-write values (empty)
455 pub mod RW {}
456 }
457
458 /// Update interrupt enable
459 pub mod UIE {
460 /// Offset (0 bits)
461 pub const offset: u32 = 0;
462 /// Mask (1 bit: 1 << 0)
463 pub const mask: u32 = 1 << offset;
464 /// Read-only values (empty)
465 pub mod R {}
466 /// Write-only values (empty)
467 pub mod W {}
468 /// Read-write values (empty)
469 pub mod RW {}
470 }
471}
472
473/// status register
474pub mod SR {
475
476 /// Capture/Compare 4 overcapture flag
477 pub mod CC4OF {
478 /// Offset (12 bits)
479 pub const offset: u32 = 12;
480 /// Mask (1 bit: 1 << 12)
481 pub const mask: u32 = 1 << offset;
482 /// Read-only values (empty)
483 pub mod R {}
484 /// Write-only values (empty)
485 pub mod W {}
486 /// Read-write values (empty)
487 pub mod RW {}
488 }
489
490 /// Capture/Compare 3 overcapture flag
491 pub mod CC3OF {
492 /// Offset (11 bits)
493 pub const offset: u32 = 11;
494 /// Mask (1 bit: 1 << 11)
495 pub const mask: u32 = 1 << offset;
496 /// Read-only values (empty)
497 pub mod R {}
498 /// Write-only values (empty)
499 pub mod W {}
500 /// Read-write values (empty)
501 pub mod RW {}
502 }
503
504 /// Capture/compare 2 overcapture flag
505 pub mod CC2OF {
506 /// Offset (10 bits)
507 pub const offset: u32 = 10;
508 /// Mask (1 bit: 1 << 10)
509 pub const mask: u32 = 1 << offset;
510 /// Read-only values (empty)
511 pub mod R {}
512 /// Write-only values (empty)
513 pub mod W {}
514 /// Read-write values (empty)
515 pub mod RW {}
516 }
517
518 /// Capture/Compare 1 overcapture flag
519 pub mod CC1OF {
520 /// Offset (9 bits)
521 pub const offset: u32 = 9;
522 /// Mask (1 bit: 1 << 9)
523 pub const mask: u32 = 1 << offset;
524 /// Read-only values (empty)
525 pub mod R {}
526 /// Write-only values (empty)
527 pub mod W {}
528 /// Read-write values (empty)
529 pub mod RW {}
530 }
531
532 /// Trigger interrupt flag
533 pub mod TIF {
534 /// Offset (6 bits)
535 pub const offset: u32 = 6;
536 /// Mask (1 bit: 1 << 6)
537 pub const mask: u32 = 1 << offset;
538 /// Read-only values (empty)
539 pub mod R {}
540 /// Write-only values (empty)
541 pub mod W {}
542 /// Read-write values (empty)
543 pub mod RW {}
544 }
545
546 /// Capture/Compare 4 interrupt flag
547 pub mod CC4IF {
548 /// Offset (4 bits)
549 pub const offset: u32 = 4;
550 /// Mask (1 bit: 1 << 4)
551 pub const mask: u32 = 1 << offset;
552 /// Read-only values (empty)
553 pub mod R {}
554 /// Write-only values (empty)
555 pub mod W {}
556 /// Read-write values (empty)
557 pub mod RW {}
558 }
559
560 /// Capture/Compare 3 interrupt flag
561 pub mod CC3IF {
562 /// Offset (3 bits)
563 pub const offset: u32 = 3;
564 /// Mask (1 bit: 1 << 3)
565 pub const mask: u32 = 1 << offset;
566 /// Read-only values (empty)
567 pub mod R {}
568 /// Write-only values (empty)
569 pub mod W {}
570 /// Read-write values (empty)
571 pub mod RW {}
572 }
573
574 /// Capture/Compare 2 interrupt flag
575 pub mod CC2IF {
576 /// Offset (2 bits)
577 pub const offset: u32 = 2;
578 /// Mask (1 bit: 1 << 2)
579 pub const mask: u32 = 1 << offset;
580 /// Read-only values (empty)
581 pub mod R {}
582 /// Write-only values (empty)
583 pub mod W {}
584 /// Read-write values (empty)
585 pub mod RW {}
586 }
587
588 /// Capture/compare 1 interrupt flag
589 pub mod CC1IF {
590 /// Offset (1 bits)
591 pub const offset: u32 = 1;
592 /// Mask (1 bit: 1 << 1)
593 pub const mask: u32 = 1 << offset;
594 /// Read-only values (empty)
595 pub mod R {}
596 /// Write-only values (empty)
597 pub mod W {}
598 /// Read-write values (empty)
599 pub mod RW {}
600 }
601
602 /// Update interrupt flag
603 pub mod UIF {
604 /// Offset (0 bits)
605 pub const offset: u32 = 0;
606 /// Mask (1 bit: 1 << 0)
607 pub const mask: u32 = 1 << offset;
608 /// Read-only values (empty)
609 pub mod R {}
610 /// Write-only values (empty)
611 pub mod W {}
612 /// Read-write values (empty)
613 pub mod RW {}
614 }
615}
616
617/// event generation register
618pub mod EGR {
619
620 /// Trigger generation
621 pub mod TG {
622 /// Offset (6 bits)
623 pub const offset: u32 = 6;
624 /// Mask (1 bit: 1 << 6)
625 pub const mask: u32 = 1 << offset;
626 /// Read-only values (empty)
627 pub mod R {}
628 /// Write-only values (empty)
629 pub mod W {}
630 /// Read-write values (empty)
631 pub mod RW {}
632 }
633
634 /// Capture/compare 4 generation
635 pub mod CC4G {
636 /// Offset (4 bits)
637 pub const offset: u32 = 4;
638 /// Mask (1 bit: 1 << 4)
639 pub const mask: u32 = 1 << offset;
640 /// Read-only values (empty)
641 pub mod R {}
642 /// Write-only values (empty)
643 pub mod W {}
644 /// Read-write values (empty)
645 pub mod RW {}
646 }
647
648 /// Capture/compare 3 generation
649 pub mod CC3G {
650 /// Offset (3 bits)
651 pub const offset: u32 = 3;
652 /// Mask (1 bit: 1 << 3)
653 pub const mask: u32 = 1 << offset;
654 /// Read-only values (empty)
655 pub mod R {}
656 /// Write-only values (empty)
657 pub mod W {}
658 /// Read-write values (empty)
659 pub mod RW {}
660 }
661
662 /// Capture/compare 2 generation
663 pub mod CC2G {
664 /// Offset (2 bits)
665 pub const offset: u32 = 2;
666 /// Mask (1 bit: 1 << 2)
667 pub const mask: u32 = 1 << offset;
668 /// Read-only values (empty)
669 pub mod R {}
670 /// Write-only values (empty)
671 pub mod W {}
672 /// Read-write values (empty)
673 pub mod RW {}
674 }
675
676 /// Capture/compare 1 generation
677 pub mod CC1G {
678 /// Offset (1 bits)
679 pub const offset: u32 = 1;
680 /// Mask (1 bit: 1 << 1)
681 pub const mask: u32 = 1 << offset;
682 /// Read-only values (empty)
683 pub mod R {}
684 /// Write-only values (empty)
685 pub mod W {}
686 /// Read-write values (empty)
687 pub mod RW {}
688 }
689
690 /// Update generation
691 pub mod UG {
692 /// Offset (0 bits)
693 pub const offset: u32 = 0;
694 /// Mask (1 bit: 1 << 0)
695 pub const mask: u32 = 1 << offset;
696 /// Read-only values (empty)
697 pub mod R {}
698 /// Write-only values (empty)
699 pub mod W {}
700 /// Read-write values (empty)
701 pub mod RW {}
702 }
703}
704
705/// CCMR1_Output and CCMR1_Input
706/// CCMR1_Output: capture/compare mode register 1 (output mode)
707/// CCMR1_Input: capture/compare mode register 1 (input mode)
708pub mod CCMR1 {
709
710 /// Output Compare 2 mode - bit 3
711 pub mod OC2M_3 {
712 /// Offset (24 bits)
713 pub const offset: u32 = 24;
714 /// Mask (1 bit: 1 << 24)
715 pub const mask: u32 = 1 << offset;
716 /// Read-only values (empty)
717 pub mod R {}
718 /// Write-only values (empty)
719 pub mod W {}
720 /// Read-write values
721 pub mod RW {
722
723 /// 0b0: Normal output compare mode (modes 0-7)
724 pub const Normal: u32 = 0b0;
725
726 /// 0b1: Extended output compare mode (modes 7-15)
727 pub const Extended: u32 = 0b1;
728 }
729 }
730
731 /// Output Compare 1 mode - bit 3
732 pub mod OC1M_3 {
733 /// Offset (16 bits)
734 pub const offset: u32 = 16;
735 /// Mask (1 bit: 1 << 16)
736 pub const mask: u32 = 1 << offset;
737 /// Read-only values (empty)
738 pub mod R {}
739 /// Write-only values (empty)
740 pub mod W {}
741 pub use super::OC2M_3::RW;
742 }
743
744 /// Output compare 2 clear enable
745 pub mod OC2CE {
746 /// Offset (15 bits)
747 pub const offset: u32 = 15;
748 /// Mask (1 bit: 1 << 15)
749 pub const mask: u32 = 1 << offset;
750 /// Read-only values (empty)
751 pub mod R {}
752 /// Write-only values (empty)
753 pub mod W {}
754 /// Read-write values (empty)
755 pub mod RW {}
756 }
757
758 /// Output compare 2 mode
759 pub mod OC2M {
760 /// Offset (12 bits)
761 pub const offset: u32 = 12;
762 /// Mask (3 bits: 0b111 << 12)
763 pub const mask: u32 = 0b111 << offset;
764 /// Read-only values (empty)
765 pub mod R {}
766 /// Write-only values (empty)
767 pub mod W {}
768 /// Read-write values
769 pub mod RW {
770
771 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
772 pub const Frozen: u32 = 0b000;
773
774 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
775 pub const ActiveOnMatch: u32 = 0b001;
776
777 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
778 pub const InactiveOnMatch: u32 = 0b010;
779
780 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
781 pub const Toggle: u32 = 0b011;
782
783 /// 0b100: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
784 pub const ForceInactive: u32 = 0b100;
785
786 /// 0b101: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
787 pub const ForceActive: u32 = 0b101;
788
789 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
790 pub const PwmMode1: u32 = 0b110;
791
792 /// 0b111: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
793 pub const PwmMode2: u32 = 0b111;
794 }
795 }
796
797 /// Output compare 2 preload enable
798 pub mod OC2PE {
799 /// Offset (11 bits)
800 pub const offset: u32 = 11;
801 /// Mask (1 bit: 1 << 11)
802 pub const mask: u32 = 1 << offset;
803 /// Read-only values (empty)
804 pub mod R {}
805 /// Write-only values (empty)
806 pub mod W {}
807 /// Read-write values (empty)
808 pub mod RW {}
809 }
810
811 /// Output compare 2 fast enable
812 pub mod OC2FE {
813 /// Offset (10 bits)
814 pub const offset: u32 = 10;
815 /// Mask (1 bit: 1 << 10)
816 pub const mask: u32 = 1 << offset;
817 /// Read-only values (empty)
818 pub mod R {}
819 /// Write-only values (empty)
820 pub mod W {}
821 /// Read-write values (empty)
822 pub mod RW {}
823 }
824
825 /// Capture/Compare 2 selection
826 pub mod CC2S {
827 /// Offset (8 bits)
828 pub const offset: u32 = 8;
829 /// Mask (2 bits: 0b11 << 8)
830 pub const mask: u32 = 0b11 << offset;
831 /// Read-only values (empty)
832 pub mod R {}
833 /// Write-only values (empty)
834 pub mod W {}
835 /// Read-write values (empty)
836 pub mod RW {}
837 }
838
839 /// Output compare 1 clear enable
840 pub mod OC1CE {
841 /// Offset (7 bits)
842 pub const offset: u32 = 7;
843 /// Mask (1 bit: 1 << 7)
844 pub const mask: u32 = 1 << offset;
845 /// Read-only values (empty)
846 pub mod R {}
847 /// Write-only values (empty)
848 pub mod W {}
849 /// Read-write values (empty)
850 pub mod RW {}
851 }
852
853 /// Output compare 1 mode
854 pub mod OC1M {
855 /// Offset (4 bits)
856 pub const offset: u32 = 4;
857 /// Mask (3 bits: 0b111 << 4)
858 pub const mask: u32 = 0b111 << offset;
859 /// Read-only values (empty)
860 pub mod R {}
861 /// Write-only values (empty)
862 pub mod W {}
863 pub use super::OC2M::RW;
864 }
865
866 /// Output compare 1 preload enable
867 pub mod OC1PE {
868 /// Offset (3 bits)
869 pub const offset: u32 = 3;
870 /// Mask (1 bit: 1 << 3)
871 pub const mask: u32 = 1 << offset;
872 /// Read-only values (empty)
873 pub mod R {}
874 /// Write-only values (empty)
875 pub mod W {}
876 /// Read-write values (empty)
877 pub mod RW {}
878 }
879
880 /// Output compare 1 fast enable
881 pub mod OC1FE {
882 /// Offset (2 bits)
883 pub const offset: u32 = 2;
884 /// Mask (1 bit: 1 << 2)
885 pub const mask: u32 = 1 << offset;
886 /// Read-only values (empty)
887 pub mod R {}
888 /// Write-only values (empty)
889 pub mod W {}
890 /// Read-write values (empty)
891 pub mod RW {}
892 }
893
894 /// Capture/Compare 1 selection
895 pub mod CC1S {
896 /// Offset (0 bits)
897 pub const offset: u32 = 0;
898 /// Mask (2 bits: 0b11 << 0)
899 pub const mask: u32 = 0b11 << offset;
900 /// Read-only values (empty)
901 pub mod R {}
902 /// Write-only values (empty)
903 pub mod W {}
904 /// Read-write values (empty)
905 pub mod RW {}
906 }
907
908 /// Input capture 2 filter
909 pub mod IC2F {
910 /// Offset (12 bits)
911 pub const offset: u32 = 12;
912 /// Mask (4 bits: 0b1111 << 12)
913 pub const mask: u32 = 0b1111 << offset;
914 /// Read-only values (empty)
915 pub mod R {}
916 /// Write-only values (empty)
917 pub mod W {}
918 /// Read-write values (empty)
919 pub mod RW {}
920 }
921
922 /// Input capture 2 prescaler
923 pub mod IC2PSC {
924 /// Offset (10 bits)
925 pub const offset: u32 = 10;
926 /// Mask (2 bits: 0b11 << 10)
927 pub const mask: u32 = 0b11 << offset;
928 /// Read-only values (empty)
929 pub mod R {}
930 /// Write-only values (empty)
931 pub mod W {}
932 /// Read-write values (empty)
933 pub mod RW {}
934 }
935
936 /// Input capture 1 filter
937 pub mod IC1F {
938 /// Offset (4 bits)
939 pub const offset: u32 = 4;
940 /// Mask (4 bits: 0b1111 << 4)
941 pub const mask: u32 = 0b1111 << offset;
942 /// Read-only values (empty)
943 pub mod R {}
944 /// Write-only values (empty)
945 pub mod W {}
946 /// Read-write values (empty)
947 pub mod RW {}
948 }
949
950 /// Input capture 1 prescaler
951 pub mod IC1PSC {
952 /// Offset (2 bits)
953 pub const offset: u32 = 2;
954 /// Mask (2 bits: 0b11 << 2)
955 pub const mask: u32 = 0b11 << offset;
956 /// Read-only values (empty)
957 pub mod R {}
958 /// Write-only values (empty)
959 pub mod W {}
960 /// Read-write values (empty)
961 pub mod RW {}
962 }
963}
964
965/// CCMR2_Output and CCMR2_Input
966/// CCMR2_Output: capture/compare mode register 2 (output mode)
967/// CCMR2_Input: capture/compare mode register 2 (input mode)
968pub mod CCMR2 {
969
970 /// Output Compare 4 mode - bit 3
971 pub mod OC4M_3 {
972 /// Offset (24 bits)
973 pub const offset: u32 = 24;
974 /// Mask (1 bit: 1 << 24)
975 pub const mask: u32 = 1 << offset;
976 /// Read-only values (empty)
977 pub mod R {}
978 /// Write-only values (empty)
979 pub mod W {}
980 /// Read-write values
981 pub mod RW {
982
983 /// 0b0: Normal output compare mode (modes 0-7)
984 pub const Normal: u32 = 0b0;
985
986 /// 0b1: Extended output compare mode (modes 7-15)
987 pub const Extended: u32 = 0b1;
988 }
989 }
990
991 /// Output Compare 3 mode - bit 3
992 pub mod OC3M_3 {
993 /// Offset (16 bits)
994 pub const offset: u32 = 16;
995 /// Mask (1 bit: 1 << 16)
996 pub const mask: u32 = 1 << offset;
997 /// Read-only values (empty)
998 pub mod R {}
999 /// Write-only values (empty)
1000 pub mod W {}
1001 pub use super::OC4M_3::RW;
1002 }
1003
1004 /// Output compare 4 clear enable
1005 pub mod OC4CE {
1006 /// Offset (15 bits)
1007 pub const offset: u32 = 15;
1008 /// Mask (1 bit: 1 << 15)
1009 pub const mask: u32 = 1 << offset;
1010 /// Read-only values (empty)
1011 pub mod R {}
1012 /// Write-only values (empty)
1013 pub mod W {}
1014 /// Read-write values (empty)
1015 pub mod RW {}
1016 }
1017
1018 /// Output compare 4 mode
1019 pub mod OC4M {
1020 /// Offset (12 bits)
1021 pub const offset: u32 = 12;
1022 /// Mask (3 bits: 0b111 << 12)
1023 pub const mask: u32 = 0b111 << offset;
1024 /// Read-only values (empty)
1025 pub mod R {}
1026 /// Write-only values (empty)
1027 pub mod W {}
1028 /// Read-write values
1029 pub mod RW {
1030
1031 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1032 pub const Frozen: u32 = 0b000;
1033
1034 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1035 pub const ActiveOnMatch: u32 = 0b001;
1036
1037 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
1038 pub const InactiveOnMatch: u32 = 0b010;
1039
1040 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
1041 pub const Toggle: u32 = 0b011;
1042
1043 /// 0b100: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
1044 pub const ForceInactive: u32 = 0b100;
1045
1046 /// 0b101: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
1047 pub const ForceActive: u32 = 0b101;
1048
1049 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
1050 pub const PwmMode1: u32 = 0b110;
1051
1052 /// 0b111: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
1053 pub const PwmMode2: u32 = 0b111;
1054 }
1055 }
1056
1057 /// Output compare 4 preload enable
1058 pub mod OC4PE {
1059 /// Offset (11 bits)
1060 pub const offset: u32 = 11;
1061 /// Mask (1 bit: 1 << 11)
1062 pub const mask: u32 = 1 << offset;
1063 /// Read-only values (empty)
1064 pub mod R {}
1065 /// Write-only values (empty)
1066 pub mod W {}
1067 /// Read-write values (empty)
1068 pub mod RW {}
1069 }
1070
1071 /// Output compare 4 fast enable
1072 pub mod OC4FE {
1073 /// Offset (10 bits)
1074 pub const offset: u32 = 10;
1075 /// Mask (1 bit: 1 << 10)
1076 pub const mask: u32 = 1 << offset;
1077 /// Read-only values (empty)
1078 pub mod R {}
1079 /// Write-only values (empty)
1080 pub mod W {}
1081 /// Read-write values (empty)
1082 pub mod RW {}
1083 }
1084
1085 /// Capture/Compare 4 selection
1086 pub mod CC4S {
1087 /// Offset (8 bits)
1088 pub const offset: u32 = 8;
1089 /// Mask (2 bits: 0b11 << 8)
1090 pub const mask: u32 = 0b11 << offset;
1091 /// Read-only values (empty)
1092 pub mod R {}
1093 /// Write-only values (empty)
1094 pub mod W {}
1095 /// Read-write values (empty)
1096 pub mod RW {}
1097 }
1098
1099 /// Output compare 3 clear enable
1100 pub mod OC3CE {
1101 /// Offset (7 bits)
1102 pub const offset: u32 = 7;
1103 /// Mask (1 bit: 1 << 7)
1104 pub const mask: u32 = 1 << offset;
1105 /// Read-only values (empty)
1106 pub mod R {}
1107 /// Write-only values (empty)
1108 pub mod W {}
1109 /// Read-write values (empty)
1110 pub mod RW {}
1111 }
1112
1113 /// Output compare 3 mode
1114 pub mod OC3M {
1115 /// Offset (4 bits)
1116 pub const offset: u32 = 4;
1117 /// Mask (3 bits: 0b111 << 4)
1118 pub const mask: u32 = 0b111 << offset;
1119 /// Read-only values (empty)
1120 pub mod R {}
1121 /// Write-only values (empty)
1122 pub mod W {}
1123 pub use super::OC4M::RW;
1124 }
1125
1126 /// Output compare 3 preload enable
1127 pub mod OC3PE {
1128 /// Offset (3 bits)
1129 pub const offset: u32 = 3;
1130 /// Mask (1 bit: 1 << 3)
1131 pub const mask: u32 = 1 << offset;
1132 /// Read-only values (empty)
1133 pub mod R {}
1134 /// Write-only values (empty)
1135 pub mod W {}
1136 /// Read-write values (empty)
1137 pub mod RW {}
1138 }
1139
1140 /// Output compare 3 fast enable
1141 pub mod OC3FE {
1142 /// Offset (2 bits)
1143 pub const offset: u32 = 2;
1144 /// Mask (1 bit: 1 << 2)
1145 pub const mask: u32 = 1 << offset;
1146 /// Read-only values (empty)
1147 pub mod R {}
1148 /// Write-only values (empty)
1149 pub mod W {}
1150 /// Read-write values (empty)
1151 pub mod RW {}
1152 }
1153
1154 /// Capture/Compare 3 selection
1155 pub mod CC3S {
1156 /// Offset (0 bits)
1157 pub const offset: u32 = 0;
1158 /// Mask (2 bits: 0b11 << 0)
1159 pub const mask: u32 = 0b11 << offset;
1160 /// Read-only values (empty)
1161 pub mod R {}
1162 /// Write-only values (empty)
1163 pub mod W {}
1164 /// Read-write values (empty)
1165 pub mod RW {}
1166 }
1167
1168 /// Input capture 4 filter
1169 pub mod IC4F {
1170 /// Offset (12 bits)
1171 pub const offset: u32 = 12;
1172 /// Mask (4 bits: 0b1111 << 12)
1173 pub const mask: u32 = 0b1111 << offset;
1174 /// Read-only values (empty)
1175 pub mod R {}
1176 /// Write-only values (empty)
1177 pub mod W {}
1178 /// Read-write values (empty)
1179 pub mod RW {}
1180 }
1181
1182 /// Input capture 4 prescaler
1183 pub mod IC4PSC {
1184 /// Offset (10 bits)
1185 pub const offset: u32 = 10;
1186 /// Mask (2 bits: 0b11 << 10)
1187 pub const mask: u32 = 0b11 << offset;
1188 /// Read-only values (empty)
1189 pub mod R {}
1190 /// Write-only values (empty)
1191 pub mod W {}
1192 /// Read-write values (empty)
1193 pub mod RW {}
1194 }
1195
1196 /// Input capture 3 filter
1197 pub mod IC3F {
1198 /// Offset (4 bits)
1199 pub const offset: u32 = 4;
1200 /// Mask (4 bits: 0b1111 << 4)
1201 pub const mask: u32 = 0b1111 << offset;
1202 /// Read-only values (empty)
1203 pub mod R {}
1204 /// Write-only values (empty)
1205 pub mod W {}
1206 /// Read-write values (empty)
1207 pub mod RW {}
1208 }
1209
1210 /// Input capture 3 prescaler
1211 pub mod IC3PSC {
1212 /// Offset (2 bits)
1213 pub const offset: u32 = 2;
1214 /// Mask (2 bits: 0b11 << 2)
1215 pub const mask: u32 = 0b11 << offset;
1216 /// Read-only values (empty)
1217 pub mod R {}
1218 /// Write-only values (empty)
1219 pub mod W {}
1220 /// Read-write values (empty)
1221 pub mod RW {}
1222 }
1223}
1224
1225/// capture/compare enable register
1226pub mod CCER {
1227
1228 /// Capture/Compare 4 output Polarity
1229 pub mod CC4NP {
1230 /// Offset (15 bits)
1231 pub const offset: u32 = 15;
1232 /// Mask (1 bit: 1 << 15)
1233 pub const mask: u32 = 1 << offset;
1234 /// Read-only values (empty)
1235 pub mod R {}
1236 /// Write-only values (empty)
1237 pub mod W {}
1238 /// Read-write values (empty)
1239 pub mod RW {}
1240 }
1241
1242 /// Capture/Compare 3 output Polarity
1243 pub mod CC4P {
1244 /// Offset (13 bits)
1245 pub const offset: u32 = 13;
1246 /// Mask (1 bit: 1 << 13)
1247 pub const mask: u32 = 1 << offset;
1248 /// Read-only values (empty)
1249 pub mod R {}
1250 /// Write-only values (empty)
1251 pub mod W {}
1252 /// Read-write values (empty)
1253 pub mod RW {}
1254 }
1255
1256 /// Capture/Compare 4 output enable
1257 pub mod CC4E {
1258 /// Offset (12 bits)
1259 pub const offset: u32 = 12;
1260 /// Mask (1 bit: 1 << 12)
1261 pub const mask: u32 = 1 << offset;
1262 /// Read-only values (empty)
1263 pub mod R {}
1264 /// Write-only values (empty)
1265 pub mod W {}
1266 /// Read-write values (empty)
1267 pub mod RW {}
1268 }
1269
1270 /// Capture/Compare 3 output Polarity
1271 pub mod CC3NP {
1272 /// Offset (11 bits)
1273 pub const offset: u32 = 11;
1274 /// Mask (1 bit: 1 << 11)
1275 pub const mask: u32 = 1 << offset;
1276 /// Read-only values (empty)
1277 pub mod R {}
1278 /// Write-only values (empty)
1279 pub mod W {}
1280 /// Read-write values (empty)
1281 pub mod RW {}
1282 }
1283
1284 /// Capture/Compare 3 output Polarity
1285 pub mod CC3P {
1286 /// Offset (9 bits)
1287 pub const offset: u32 = 9;
1288 /// Mask (1 bit: 1 << 9)
1289 pub const mask: u32 = 1 << offset;
1290 /// Read-only values (empty)
1291 pub mod R {}
1292 /// Write-only values (empty)
1293 pub mod W {}
1294 /// Read-write values (empty)
1295 pub mod RW {}
1296 }
1297
1298 /// Capture/Compare 3 output enable
1299 pub mod CC3E {
1300 /// Offset (8 bits)
1301 pub const offset: u32 = 8;
1302 /// Mask (1 bit: 1 << 8)
1303 pub const mask: u32 = 1 << offset;
1304 /// Read-only values (empty)
1305 pub mod R {}
1306 /// Write-only values (empty)
1307 pub mod W {}
1308 /// Read-write values (empty)
1309 pub mod RW {}
1310 }
1311
1312 /// Capture/Compare 2 output Polarity
1313 pub mod CC2NP {
1314 /// Offset (7 bits)
1315 pub const offset: u32 = 7;
1316 /// Mask (1 bit: 1 << 7)
1317 pub const mask: u32 = 1 << offset;
1318 /// Read-only values (empty)
1319 pub mod R {}
1320 /// Write-only values (empty)
1321 pub mod W {}
1322 /// Read-write values (empty)
1323 pub mod RW {}
1324 }
1325
1326 /// Capture/Compare 2 output Polarity
1327 pub mod CC2P {
1328 /// Offset (5 bits)
1329 pub const offset: u32 = 5;
1330 /// Mask (1 bit: 1 << 5)
1331 pub const mask: u32 = 1 << offset;
1332 /// Read-only values (empty)
1333 pub mod R {}
1334 /// Write-only values (empty)
1335 pub mod W {}
1336 /// Read-write values (empty)
1337 pub mod RW {}
1338 }
1339
1340 /// Capture/Compare 2 output enable
1341 pub mod CC2E {
1342 /// Offset (4 bits)
1343 pub const offset: u32 = 4;
1344 /// Mask (1 bit: 1 << 4)
1345 pub const mask: u32 = 1 << offset;
1346 /// Read-only values (empty)
1347 pub mod R {}
1348 /// Write-only values (empty)
1349 pub mod W {}
1350 /// Read-write values (empty)
1351 pub mod RW {}
1352 }
1353
1354 /// Capture/Compare 1 output Polarity
1355 pub mod CC1NP {
1356 /// Offset (3 bits)
1357 pub const offset: u32 = 3;
1358 /// Mask (1 bit: 1 << 3)
1359 pub const mask: u32 = 1 << offset;
1360 /// Read-only values (empty)
1361 pub mod R {}
1362 /// Write-only values (empty)
1363 pub mod W {}
1364 /// Read-write values (empty)
1365 pub mod RW {}
1366 }
1367
1368 /// Capture/Compare 1 output Polarity
1369 pub mod CC1P {
1370 /// Offset (1 bits)
1371 pub const offset: u32 = 1;
1372 /// Mask (1 bit: 1 << 1)
1373 pub const mask: u32 = 1 << offset;
1374 /// Read-only values (empty)
1375 pub mod R {}
1376 /// Write-only values (empty)
1377 pub mod W {}
1378 /// Read-write values (empty)
1379 pub mod RW {}
1380 }
1381
1382 /// Capture/Compare 1 output enable
1383 pub mod CC1E {
1384 /// Offset (0 bits)
1385 pub const offset: u32 = 0;
1386 /// Mask (1 bit: 1 << 0)
1387 pub const mask: u32 = 1 << offset;
1388 /// Read-only values (empty)
1389 pub mod R {}
1390 /// Write-only values (empty)
1391 pub mod W {}
1392 /// Read-write values (empty)
1393 pub mod RW {}
1394 }
1395}
1396
1397/// counter
1398pub mod CNT {
1399
1400 /// Counter value
1401 pub mod CNT {
1402 /// Offset (0 bits)
1403 pub const offset: u32 = 0;
1404 /// Mask (32 bits: 0xffffffff << 0)
1405 pub const mask: u32 = 0xffffffff << offset;
1406 /// Read-only values (empty)
1407 pub mod R {}
1408 /// Write-only values (empty)
1409 pub mod W {}
1410 /// Read-write values (empty)
1411 pub mod RW {}
1412 }
1413
1414 /// Value depends on IUFREMAP in TIM2_CR1.
1415 pub mod UIFCPY {
1416 /// Offset (31 bits)
1417 pub const offset: u32 = 31;
1418 /// Mask (1 bit: 1 << 31)
1419 pub const mask: u32 = 1 << offset;
1420 /// Read-only values (empty)
1421 pub mod R {}
1422 /// Write-only values (empty)
1423 pub mod W {}
1424 /// Read-write values (empty)
1425 pub mod RW {}
1426 }
1427}
1428
1429/// prescaler
1430pub mod PSC {
1431
1432 /// Prescaler value
1433 pub mod PSC {
1434 /// Offset (0 bits)
1435 pub const offset: u32 = 0;
1436 /// Mask (16 bits: 0xffff << 0)
1437 pub const mask: u32 = 0xffff << offset;
1438 /// Read-only values (empty)
1439 pub mod R {}
1440 /// Write-only values (empty)
1441 pub mod W {}
1442 /// Read-write values (empty)
1443 pub mod RW {}
1444 }
1445}
1446
1447/// auto-reload register
1448pub mod ARR {
1449
1450 /// High Auto-reload value (TIM2 only)
1451 pub mod ARR_H {
1452 /// Offset (16 bits)
1453 pub const offset: u32 = 16;
1454 /// Mask (16 bits: 0xffff << 16)
1455 pub const mask: u32 = 0xffff << offset;
1456 /// Read-only values (empty)
1457 pub mod R {}
1458 /// Write-only values (empty)
1459 pub mod W {}
1460 /// Read-write values (empty)
1461 pub mod RW {}
1462 }
1463
1464 /// Low Auto-reload value
1465 pub mod ARR_L {
1466 /// Offset (0 bits)
1467 pub const offset: u32 = 0;
1468 /// Mask (16 bits: 0xffff << 0)
1469 pub const mask: u32 = 0xffff << offset;
1470 /// Read-only values (empty)
1471 pub mod R {}
1472 /// Write-only values (empty)
1473 pub mod W {}
1474 /// Read-write values (empty)
1475 pub mod RW {}
1476 }
1477}
1478
1479/// capture/compare register 1
1480pub mod CCR1 {
1481
1482 /// High Capture/Compare 1 value (TIM2 only)
1483 pub mod CCR1_H {
1484 /// Offset (16 bits)
1485 pub const offset: u32 = 16;
1486 /// Mask (16 bits: 0xffff << 16)
1487 pub const mask: u32 = 0xffff << offset;
1488 /// Read-only values (empty)
1489 pub mod R {}
1490 /// Write-only values (empty)
1491 pub mod W {}
1492 /// Read-write values (empty)
1493 pub mod RW {}
1494 }
1495
1496 /// Low Capture/Compare 1 value
1497 pub mod CCR1_L {
1498 /// Offset (0 bits)
1499 pub const offset: u32 = 0;
1500 /// Mask (16 bits: 0xffff << 0)
1501 pub const mask: u32 = 0xffff << offset;
1502 /// Read-only values (empty)
1503 pub mod R {}
1504 /// Write-only values (empty)
1505 pub mod W {}
1506 /// Read-write values (empty)
1507 pub mod RW {}
1508 }
1509}
1510
1511/// capture/compare register 2
1512pub mod CCR2 {
1513
1514 /// High Capture/Compare 2 value (TIM2 only)
1515 pub mod CCR2_H {
1516 /// Offset (16 bits)
1517 pub const offset: u32 = 16;
1518 /// Mask (16 bits: 0xffff << 16)
1519 pub const mask: u32 = 0xffff << offset;
1520 /// Read-only values (empty)
1521 pub mod R {}
1522 /// Write-only values (empty)
1523 pub mod W {}
1524 /// Read-write values (empty)
1525 pub mod RW {}
1526 }
1527
1528 /// Low Capture/Compare 2 value
1529 pub mod CCR2_L {
1530 /// Offset (0 bits)
1531 pub const offset: u32 = 0;
1532 /// Mask (16 bits: 0xffff << 0)
1533 pub const mask: u32 = 0xffff << offset;
1534 /// Read-only values (empty)
1535 pub mod R {}
1536 /// Write-only values (empty)
1537 pub mod W {}
1538 /// Read-write values (empty)
1539 pub mod RW {}
1540 }
1541}
1542
1543/// capture/compare register 3
1544pub mod CCR3 {
1545
1546 /// High Capture/Compare value (TIM2 only)
1547 pub mod CCR3_H {
1548 /// Offset (16 bits)
1549 pub const offset: u32 = 16;
1550 /// Mask (16 bits: 0xffff << 16)
1551 pub const mask: u32 = 0xffff << offset;
1552 /// Read-only values (empty)
1553 pub mod R {}
1554 /// Write-only values (empty)
1555 pub mod W {}
1556 /// Read-write values (empty)
1557 pub mod RW {}
1558 }
1559
1560 /// Low Capture/Compare value
1561 pub mod CCR3_L {
1562 /// Offset (0 bits)
1563 pub const offset: u32 = 0;
1564 /// Mask (16 bits: 0xffff << 0)
1565 pub const mask: u32 = 0xffff << offset;
1566 /// Read-only values (empty)
1567 pub mod R {}
1568 /// Write-only values (empty)
1569 pub mod W {}
1570 /// Read-write values (empty)
1571 pub mod RW {}
1572 }
1573}
1574
1575/// capture/compare register 4
1576pub mod CCR4 {
1577
1578 /// High Capture/Compare value (TIM2 only)
1579 pub mod CCR4_H {
1580 /// Offset (16 bits)
1581 pub const offset: u32 = 16;
1582 /// Mask (16 bits: 0xffff << 16)
1583 pub const mask: u32 = 0xffff << offset;
1584 /// Read-only values (empty)
1585 pub mod R {}
1586 /// Write-only values (empty)
1587 pub mod W {}
1588 /// Read-write values (empty)
1589 pub mod RW {}
1590 }
1591
1592 /// Low Capture/Compare value
1593 pub mod CCR4_L {
1594 /// Offset (0 bits)
1595 pub const offset: u32 = 0;
1596 /// Mask (16 bits: 0xffff << 0)
1597 pub const mask: u32 = 0xffff << offset;
1598 /// Read-only values (empty)
1599 pub mod R {}
1600 /// Write-only values (empty)
1601 pub mod W {}
1602 /// Read-write values (empty)
1603 pub mod RW {}
1604 }
1605}
1606
1607/// DMA control register
1608pub mod DCR {
1609
1610 /// DMA burst length
1611 pub mod DBL {
1612 /// Offset (8 bits)
1613 pub const offset: u32 = 8;
1614 /// Mask (5 bits: 0b11111 << 8)
1615 pub const mask: u32 = 0b11111 << offset;
1616 /// Read-only values (empty)
1617 pub mod R {}
1618 /// Write-only values (empty)
1619 pub mod W {}
1620 /// Read-write values (empty)
1621 pub mod RW {}
1622 }
1623
1624 /// DMA base address
1625 pub mod DBA {
1626 /// Offset (0 bits)
1627 pub const offset: u32 = 0;
1628 /// Mask (5 bits: 0b11111 << 0)
1629 pub const mask: u32 = 0b11111 << offset;
1630 /// Read-only values (empty)
1631 pub mod R {}
1632 /// Write-only values (empty)
1633 pub mod W {}
1634 /// Read-write values (empty)
1635 pub mod RW {}
1636 }
1637}
1638
1639/// DMA address for full transfer
1640pub mod DMAR {
1641
1642 /// DMA register for burst accesses
1643 pub mod DMAB {
1644 /// Offset (0 bits)
1645 pub const offset: u32 = 0;
1646 /// Mask (16 bits: 0xffff << 0)
1647 pub const mask: u32 = 0xffff << offset;
1648 /// Read-only values (empty)
1649 pub mod R {}
1650 /// Write-only values (empty)
1651 pub mod W {}
1652 /// Read-write values (empty)
1653 pub mod RW {}
1654 }
1655}
1656
1657/// TIM2 option register
1658pub mod OR {
1659
1660 /// Input capture 4 remap
1661 pub mod TI4_RMP {
1662 /// Offset (2 bits)
1663 pub const offset: u32 = 2;
1664 /// Mask (2 bits: 0b11 << 2)
1665 pub const mask: u32 = 0b11 << offset;
1666 /// Read-only values (empty)
1667 pub mod R {}
1668 /// Write-only values (empty)
1669 pub mod W {}
1670 /// Read-write values (empty)
1671 pub mod RW {}
1672 }
1673
1674 /// External trigger remap
1675 pub mod ETR_RMP {
1676 /// Offset (1 bits)
1677 pub const offset: u32 = 1;
1678 /// Mask (1 bit: 1 << 1)
1679 pub const mask: u32 = 1 << offset;
1680 /// Read-only values (empty)
1681 pub mod R {}
1682 /// Write-only values (empty)
1683 pub mod W {}
1684 /// Read-write values (empty)
1685 pub mod RW {}
1686 }
1687
1688 /// Internal trigger remap
1689 pub mod ITR_RMP {
1690 /// Offset (0 bits)
1691 pub const offset: u32 = 0;
1692 /// Mask (1 bit: 1 << 0)
1693 pub const mask: u32 = 1 << offset;
1694 /// Read-only values (empty)
1695 pub mod R {}
1696 /// Write-only values (empty)
1697 pub mod W {}
1698 /// Read-write values (empty)
1699 pub mod RW {}
1700 }
1701}
1702
1703/// TIM2 alternate function option register 1
1704pub mod AF {
1705
1706 /// External trigger source selection
1707 pub mod ETRSEL {
1708 /// Offset (14 bits)
1709 pub const offset: u32 = 14;
1710 /// Mask (3 bits: 0b111 << 14)
1711 pub const mask: u32 = 0b111 << offset;
1712 /// Read-only values (empty)
1713 pub mod R {}
1714 /// Write-only values (empty)
1715 pub mod W {}
1716 /// Read-write values (empty)
1717 pub mod RW {}
1718 }
1719}
1720#[repr(C)]
1721pub struct RegisterBlock {
1722 /// control register 1
1723 pub CR1: RWRegister<u32>,
1724
1725 /// control register 2
1726 pub CR2: RWRegister<u32>,
1727
1728 /// slave mode control register
1729 pub SMCR: RWRegister<u32>,
1730
1731 /// DMA/Interrupt enable register
1732 pub DIER: RWRegister<u32>,
1733
1734 /// status register
1735 pub SR: RWRegister<u32>,
1736
1737 /// event generation register
1738 pub EGR: WORegister<u32>,
1739
1740 /// CCMR1_Output and CCMR1_Input
1741 /// CCMR1_Output: capture/compare mode register 1 (output mode)
1742 /// CCMR1_Input: capture/compare mode register 1 (input mode)
1743 pub CCMR1: RWRegister<u32>,
1744
1745 /// CCMR2_Output and CCMR2_Input
1746 /// CCMR2_Output: capture/compare mode register 2 (output mode)
1747 /// CCMR2_Input: capture/compare mode register 2 (input mode)
1748 pub CCMR2: RWRegister<u32>,
1749
1750 /// capture/compare enable register
1751 pub CCER: RWRegister<u32>,
1752
1753 /// counter
1754 pub CNT: RWRegister<u32>,
1755
1756 /// prescaler
1757 pub PSC: RWRegister<u32>,
1758
1759 /// auto-reload register
1760 pub ARR: RWRegister<u32>,
1761
1762 _reserved1: [u8; 4],
1763
1764 /// capture/compare register 1
1765 pub CCR1: RWRegister<u32>,
1766
1767 /// capture/compare register 2
1768 pub CCR2: RWRegister<u32>,
1769
1770 /// capture/compare register 3
1771 pub CCR3: RWRegister<u32>,
1772
1773 /// capture/compare register 4
1774 pub CCR4: RWRegister<u32>,
1775
1776 _reserved2: [u8; 4],
1777
1778 /// DMA control register
1779 pub DCR: RWRegister<u32>,
1780
1781 /// DMA address for full transfer
1782 pub DMAR: RWRegister<u32>,
1783
1784 /// TIM2 option register
1785 pub OR: RWRegister<u32>,
1786
1787 _reserved3: [u8; 12],
1788
1789 /// TIM2 alternate function option register 1
1790 pub AF: RWRegister<u32>,
1791}
1792pub struct ResetValues {
1793 pub CR1: u32,
1794 pub CR2: u32,
1795 pub SMCR: u32,
1796 pub DIER: u32,
1797 pub SR: u32,
1798 pub EGR: u32,
1799 pub CCMR1: u32,
1800 pub CCMR2: u32,
1801 pub CCER: u32,
1802 pub CNT: u32,
1803 pub PSC: u32,
1804 pub ARR: u32,
1805 pub CCR1: u32,
1806 pub CCR2: u32,
1807 pub CCR3: u32,
1808 pub CCR4: u32,
1809 pub DCR: u32,
1810 pub DMAR: u32,
1811 pub OR: u32,
1812 pub AF: u32,
1813}
1814#[cfg(not(feature = "nosync"))]
1815pub struct Instance {
1816 pub(crate) addr: u32,
1817 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1818}
1819#[cfg(not(feature = "nosync"))]
1820impl ::core::ops::Deref for Instance {
1821 type Target = RegisterBlock;
1822 #[inline(always)]
1823 fn deref(&self) -> &RegisterBlock {
1824 unsafe { &*(self.addr as *const _) }
1825 }
1826}
1827#[cfg(feature = "rtic")]
1828unsafe impl Send for Instance {}
1829
1830/// Access functions for the TIM2 peripheral instance
1831pub mod TIM2 {
1832 use super::ResetValues;
1833
1834 #[cfg(not(feature = "nosync"))]
1835 use super::Instance;
1836
1837 #[cfg(not(feature = "nosync"))]
1838 const INSTANCE: Instance = Instance {
1839 addr: 0x40000000,
1840 _marker: ::core::marker::PhantomData,
1841 };
1842
1843 /// Reset values for each field in TIM2
1844 pub const reset: ResetValues = ResetValues {
1845 CR1: 0x00000000,
1846 CR2: 0x00000000,
1847 SMCR: 0x00000000,
1848 DIER: 0x00000000,
1849 SR: 0x00000000,
1850 EGR: 0x00000000,
1851 CCMR1: 0x00000000,
1852 CCMR2: 0x00000000,
1853 CCER: 0x00000000,
1854 CNT: 0x00000000,
1855 PSC: 0x00000000,
1856 ARR: 0x00000000,
1857 CCR1: 0x00000000,
1858 CCR2: 0x00000000,
1859 CCR3: 0x00000000,
1860 CCR4: 0x00000000,
1861 DCR: 0x00000000,
1862 DMAR: 0x00000000,
1863 OR: 0x00000000,
1864 AF: 0x00000000,
1865 };
1866
1867 #[cfg(not(feature = "nosync"))]
1868 #[allow(renamed_and_removed_lints)]
1869 #[allow(private_no_mangle_statics)]
1870 #[no_mangle]
1871 static mut TIM2_TAKEN: bool = false;
1872
1873 /// Safe access to TIM2
1874 ///
1875 /// This function returns `Some(Instance)` if this instance is not
1876 /// currently taken, and `None` if it is. This ensures that if you
1877 /// do get `Some(Instance)`, you are ensured unique access to
1878 /// the peripheral and there cannot be data races (unless other
1879 /// code uses `unsafe`, of course). You can then pass the
1880 /// `Instance` around to other functions as required. When you're
1881 /// done with it, you can call `release(instance)` to return it.
1882 ///
1883 /// `Instance` itself dereferences to a `RegisterBlock`, which
1884 /// provides access to the peripheral's registers.
1885 #[cfg(not(feature = "nosync"))]
1886 #[inline]
1887 pub fn take() -> Option<Instance> {
1888 external_cortex_m::interrupt::free(|_| unsafe {
1889 if TIM2_TAKEN {
1890 None
1891 } else {
1892 TIM2_TAKEN = true;
1893 Some(INSTANCE)
1894 }
1895 })
1896 }
1897
1898 /// Release exclusive access to TIM2
1899 ///
1900 /// This function allows you to return an `Instance` so that it
1901 /// is available to `take()` again. This function will panic if
1902 /// you return a different `Instance` or if this instance is not
1903 /// already taken.
1904 #[cfg(not(feature = "nosync"))]
1905 #[inline]
1906 pub fn release(inst: Instance) {
1907 external_cortex_m::interrupt::free(|_| unsafe {
1908 if TIM2_TAKEN && inst.addr == INSTANCE.addr {
1909 TIM2_TAKEN = false;
1910 } else {
1911 panic!("Released a peripheral which was not taken");
1912 }
1913 });
1914 }
1915
1916 /// Unsafely steal TIM2
1917 ///
1918 /// This function is similar to take() but forcibly takes the
1919 /// Instance, marking it as taken irregardless of its previous
1920 /// state.
1921 #[cfg(not(feature = "nosync"))]
1922 #[inline]
1923 pub unsafe fn steal() -> Instance {
1924 TIM2_TAKEN = true;
1925 INSTANCE
1926 }
1927}
1928
1929/// Raw pointer to TIM2
1930///
1931/// Dereferencing this is unsafe because you are not ensured unique
1932/// access to the peripheral, so you may encounter data races with
1933/// other users of this peripheral. It is up to you to ensure you
1934/// will not cause data races.
1935///
1936/// This constant is provided for ease of use in unsafe code: you can
1937/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
1938pub const TIM2: *const RegisterBlock = 0x40000000 as *const _;