stm32ral/stm32wb/stm32wb55/rcc.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Reset and clock control
4
5use crate::{RORegister, RWRegister, WORegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// Clock control register
10pub mod CR {
11
12 /// SAI1 PLL clock ready flag
13 pub mod PLLSAI1RDY {
14 /// Offset (27 bits)
15 pub const offset: u32 = 27;
16 /// Mask (1 bit: 1 << 27)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25
26 /// SAI1 PLL enable
27 pub mod PLLSAI1ON {
28 /// Offset (26 bits)
29 pub const offset: u32 = 26;
30 /// Mask (1 bit: 1 << 26)
31 pub const mask: u32 = 1 << offset;
32 /// Read-only values (empty)
33 pub mod R {}
34 /// Write-only values (empty)
35 pub mod W {}
36 /// Read-write values (empty)
37 pub mod RW {}
38 }
39
40 /// Main PLL clock ready flag
41 pub mod PLLRDY {
42 /// Offset (25 bits)
43 pub const offset: u32 = 25;
44 /// Mask (1 bit: 1 << 25)
45 pub const mask: u32 = 1 << offset;
46 /// Read-only values (empty)
47 pub mod R {}
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53
54 /// Main PLL enable
55 pub mod PLLON {
56 /// Offset (24 bits)
57 pub const offset: u32 = 24;
58 /// Mask (1 bit: 1 << 24)
59 pub const mask: u32 = 1 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// HSE sysclk and PLL M divider prescaler
69 pub mod HSEPRE {
70 /// Offset (20 bits)
71 pub const offset: u32 = 20;
72 /// Mask (1 bit: 1 << 20)
73 pub const mask: u32 = 1 << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// HSE Clock security system enable
83 pub mod CSSON {
84 /// Offset (19 bits)
85 pub const offset: u32 = 19;
86 /// Mask (1 bit: 1 << 19)
87 pub const mask: u32 = 1 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 /// Read-write values (empty)
93 pub mod RW {}
94 }
95
96 /// HSE crystal oscillator bypass
97 pub mod HSEBYP {
98 /// Offset (18 bits)
99 pub const offset: u32 = 18;
100 /// Mask (1 bit: 1 << 18)
101 pub const mask: u32 = 1 << offset;
102 /// Read-only values (empty)
103 pub mod R {}
104 /// Write-only values (empty)
105 pub mod W {}
106 /// Read-write values (empty)
107 pub mod RW {}
108 }
109
110 /// HSE clock ready flag
111 pub mod HSERDY {
112 /// Offset (17 bits)
113 pub const offset: u32 = 17;
114 /// Mask (1 bit: 1 << 17)
115 pub const mask: u32 = 1 << offset;
116 /// Read-only values (empty)
117 pub mod R {}
118 /// Write-only values (empty)
119 pub mod W {}
120 /// Read-write values (empty)
121 pub mod RW {}
122 }
123
124 /// HSE clock enabled
125 pub mod HSEON {
126 /// Offset (16 bits)
127 pub const offset: u32 = 16;
128 /// Mask (1 bit: 1 << 16)
129 pub const mask: u32 = 1 << offset;
130 /// Read-only values (empty)
131 pub mod R {}
132 /// Write-only values (empty)
133 pub mod W {}
134 /// Read-write values (empty)
135 pub mod RW {}
136 }
137
138 /// HSI kernel clock ready flag for peripherals requests
139 pub mod HSIKERDY {
140 /// Offset (12 bits)
141 pub const offset: u32 = 12;
142 /// Mask (1 bit: 1 << 12)
143 pub const mask: u32 = 1 << offset;
144 /// Read-only values (empty)
145 pub mod R {}
146 /// Write-only values (empty)
147 pub mod W {}
148 /// Read-write values (empty)
149 pub mod RW {}
150 }
151
152 /// HSI automatic start from Stop
153 pub mod HSIASFS {
154 /// Offset (11 bits)
155 pub const offset: u32 = 11;
156 /// Mask (1 bit: 1 << 11)
157 pub const mask: u32 = 1 << offset;
158 /// Read-only values (empty)
159 pub mod R {}
160 /// Write-only values (empty)
161 pub mod W {}
162 /// Read-write values (empty)
163 pub mod RW {}
164 }
165
166 /// HSI clock ready flag
167 pub mod HSIRDY {
168 /// Offset (10 bits)
169 pub const offset: u32 = 10;
170 /// Mask (1 bit: 1 << 10)
171 pub const mask: u32 = 1 << offset;
172 /// Read-only values (empty)
173 pub mod R {}
174 /// Write-only values (empty)
175 pub mod W {}
176 /// Read-write values (empty)
177 pub mod RW {}
178 }
179
180 /// HSI always enable for peripheral kernels
181 pub mod HSIKERON {
182 /// Offset (9 bits)
183 pub const offset: u32 = 9;
184 /// Mask (1 bit: 1 << 9)
185 pub const mask: u32 = 1 << offset;
186 /// Read-only values (empty)
187 pub mod R {}
188 /// Write-only values (empty)
189 pub mod W {}
190 /// Read-write values (empty)
191 pub mod RW {}
192 }
193
194 /// HSI clock enabled
195 pub mod HSION {
196 /// Offset (8 bits)
197 pub const offset: u32 = 8;
198 /// Mask (1 bit: 1 << 8)
199 pub const mask: u32 = 1 << offset;
200 /// Read-only values (empty)
201 pub mod R {}
202 /// Write-only values (empty)
203 pub mod W {}
204 /// Read-write values (empty)
205 pub mod RW {}
206 }
207
208 /// MSI clock ranges
209 pub mod MSIRANGE {
210 /// Offset (4 bits)
211 pub const offset: u32 = 4;
212 /// Mask (4 bits: 0b1111 << 4)
213 pub const mask: u32 = 0b1111 << offset;
214 /// Read-only values (empty)
215 pub mod R {}
216 /// Write-only values (empty)
217 pub mod W {}
218 /// Read-write values (empty)
219 pub mod RW {}
220 }
221
222 /// MSI clock PLL enable
223 pub mod MSIPLLEN {
224 /// Offset (2 bits)
225 pub const offset: u32 = 2;
226 /// Mask (1 bit: 1 << 2)
227 pub const mask: u32 = 1 << offset;
228 /// Read-only values (empty)
229 pub mod R {}
230 /// Write-only values (empty)
231 pub mod W {}
232 /// Read-write values (empty)
233 pub mod RW {}
234 }
235
236 /// MSI clock ready flag
237 pub mod MSIRDY {
238 /// Offset (1 bits)
239 pub const offset: u32 = 1;
240 /// Mask (1 bit: 1 << 1)
241 pub const mask: u32 = 1 << offset;
242 /// Read-only values (empty)
243 pub mod R {}
244 /// Write-only values (empty)
245 pub mod W {}
246 /// Read-write values (empty)
247 pub mod RW {}
248 }
249
250 /// MSI clock enable
251 pub mod MSION {
252 /// Offset (0 bits)
253 pub const offset: u32 = 0;
254 /// Mask (1 bit: 1 << 0)
255 pub const mask: u32 = 1 << offset;
256 /// Read-only values (empty)
257 pub mod R {}
258 /// Write-only values (empty)
259 pub mod W {}
260 /// Read-write values (empty)
261 pub mod RW {}
262 }
263}
264
265/// Internal clock sources calibration register
266pub mod ICSCR {
267
268 /// HSI clock trimming
269 pub mod HSITRIM {
270 /// Offset (24 bits)
271 pub const offset: u32 = 24;
272 /// Mask (7 bits: 0x7f << 24)
273 pub const mask: u32 = 0x7f << offset;
274 /// Read-only values (empty)
275 pub mod R {}
276 /// Write-only values (empty)
277 pub mod W {}
278 /// Read-write values (empty)
279 pub mod RW {}
280 }
281
282 /// HSI clock calibration
283 pub mod HSICAL {
284 /// Offset (16 bits)
285 pub const offset: u32 = 16;
286 /// Mask (8 bits: 0xff << 16)
287 pub const mask: u32 = 0xff << offset;
288 /// Read-only values (empty)
289 pub mod R {}
290 /// Write-only values (empty)
291 pub mod W {}
292 /// Read-write values (empty)
293 pub mod RW {}
294 }
295
296 /// MSI clock trimming
297 pub mod MSITRIM {
298 /// Offset (8 bits)
299 pub const offset: u32 = 8;
300 /// Mask (8 bits: 0xff << 8)
301 pub const mask: u32 = 0xff << offset;
302 /// Read-only values (empty)
303 pub mod R {}
304 /// Write-only values (empty)
305 pub mod W {}
306 /// Read-write values (empty)
307 pub mod RW {}
308 }
309
310 /// MSI clock calibration
311 pub mod MSICAL {
312 /// Offset (0 bits)
313 pub const offset: u32 = 0;
314 /// Mask (8 bits: 0xff << 0)
315 pub const mask: u32 = 0xff << offset;
316 /// Read-only values (empty)
317 pub mod R {}
318 /// Write-only values (empty)
319 pub mod W {}
320 /// Read-write values (empty)
321 pub mod RW {}
322 }
323}
324
325/// Clock configuration register
326pub mod CFGR {
327
328 /// Microcontroller clock output prescaler
329 pub mod MCOPRE {
330 /// Offset (28 bits)
331 pub const offset: u32 = 28;
332 /// Mask (3 bits: 0b111 << 28)
333 pub const mask: u32 = 0b111 << offset;
334 /// Read-only values (empty)
335 pub mod R {}
336 /// Write-only values (empty)
337 pub mod W {}
338 /// Read-write values (empty)
339 pub mod RW {}
340 }
341
342 /// Microcontroller clock output
343 pub mod MCOSEL {
344 /// Offset (24 bits)
345 pub const offset: u32 = 24;
346 /// Mask (4 bits: 0b1111 << 24)
347 pub const mask: u32 = 0b1111 << offset;
348 /// Read-only values (empty)
349 pub mod R {}
350 /// Write-only values (empty)
351 pub mod W {}
352 /// Read-write values (empty)
353 pub mod RW {}
354 }
355
356 /// APB2 prescaler flag
357 pub mod PPRE2F {
358 /// Offset (18 bits)
359 pub const offset: u32 = 18;
360 /// Mask (1 bit: 1 << 18)
361 pub const mask: u32 = 1 << offset;
362 /// Read-only values (empty)
363 pub mod R {}
364 /// Write-only values (empty)
365 pub mod W {}
366 /// Read-write values (empty)
367 pub mod RW {}
368 }
369
370 /// APB1 prescaler flag
371 pub mod PPRE1F {
372 /// Offset (17 bits)
373 pub const offset: u32 = 17;
374 /// Mask (1 bit: 1 << 17)
375 pub const mask: u32 = 1 << offset;
376 /// Read-only values (empty)
377 pub mod R {}
378 /// Write-only values (empty)
379 pub mod W {}
380 /// Read-write values (empty)
381 pub mod RW {}
382 }
383
384 /// AHB prescaler flag
385 pub mod HPREF {
386 /// Offset (16 bits)
387 pub const offset: u32 = 16;
388 /// Mask (1 bit: 1 << 16)
389 pub const mask: u32 = 1 << offset;
390 /// Read-only values (empty)
391 pub mod R {}
392 /// Write-only values (empty)
393 pub mod W {}
394 /// Read-write values (empty)
395 pub mod RW {}
396 }
397
398 /// Wakeup from Stop and CSS backup clock selection
399 pub mod STOPWUCK {
400 /// Offset (15 bits)
401 pub const offset: u32 = 15;
402 /// Mask (1 bit: 1 << 15)
403 pub const mask: u32 = 1 << offset;
404 /// Read-only values (empty)
405 pub mod R {}
406 /// Write-only values (empty)
407 pub mod W {}
408 /// Read-write values (empty)
409 pub mod RW {}
410 }
411
412 /// APB high-speed prescaler (APB2)
413 pub mod PPRE2 {
414 /// Offset (11 bits)
415 pub const offset: u32 = 11;
416 /// Mask (3 bits: 0b111 << 11)
417 pub const mask: u32 = 0b111 << offset;
418 /// Read-only values (empty)
419 pub mod R {}
420 /// Write-only values (empty)
421 pub mod W {}
422 /// Read-write values (empty)
423 pub mod RW {}
424 }
425
426 /// PB low-speed prescaler (APB1)
427 pub mod PPRE1 {
428 /// Offset (8 bits)
429 pub const offset: u32 = 8;
430 /// Mask (3 bits: 0b111 << 8)
431 pub const mask: u32 = 0b111 << offset;
432 /// Read-only values (empty)
433 pub mod R {}
434 /// Write-only values (empty)
435 pub mod W {}
436 /// Read-write values (empty)
437 pub mod RW {}
438 }
439
440 /// AHB prescaler
441 pub mod HPRE {
442 /// Offset (4 bits)
443 pub const offset: u32 = 4;
444 /// Mask (4 bits: 0b1111 << 4)
445 pub const mask: u32 = 0b1111 << offset;
446 /// Read-only values (empty)
447 pub mod R {}
448 /// Write-only values (empty)
449 pub mod W {}
450 /// Read-write values (empty)
451 pub mod RW {}
452 }
453
454 /// System clock switch status
455 pub mod SWS {
456 /// Offset (2 bits)
457 pub const offset: u32 = 2;
458 /// Mask (2 bits: 0b11 << 2)
459 pub const mask: u32 = 0b11 << offset;
460 /// Read-only values (empty)
461 pub mod R {}
462 /// Write-only values (empty)
463 pub mod W {}
464 /// Read-write values (empty)
465 pub mod RW {}
466 }
467
468 /// System clock switch
469 pub mod SW {
470 /// Offset (0 bits)
471 pub const offset: u32 = 0;
472 /// Mask (2 bits: 0b11 << 0)
473 pub const mask: u32 = 0b11 << offset;
474 /// Read-only values (empty)
475 pub mod R {}
476 /// Write-only values (empty)
477 pub mod W {}
478 /// Read-write values (empty)
479 pub mod RW {}
480 }
481}
482
483/// PLLSYS configuration register
484pub mod PLLCFGR {
485
486 /// Main PLLSYS division factor R for SYSCLK (system clock)
487 pub mod PLLR {
488 /// Offset (29 bits)
489 pub const offset: u32 = 29;
490 /// Mask (3 bits: 0b111 << 29)
491 pub const mask: u32 = 0b111 << offset;
492 /// Read-only values (empty)
493 pub mod R {}
494 /// Write-only values (empty)
495 pub mod W {}
496 /// Read-write values (empty)
497 pub mod RW {}
498 }
499
500 /// Main PLLSYSR PLLCLK output enable
501 pub mod PLLREN {
502 /// Offset (28 bits)
503 pub const offset: u32 = 28;
504 /// Mask (1 bit: 1 << 28)
505 pub const mask: u32 = 1 << offset;
506 /// Read-only values (empty)
507 pub mod R {}
508 /// Write-only values (empty)
509 pub mod W {}
510 /// Read-write values (empty)
511 pub mod RW {}
512 }
513
514 /// Main PLLSYS division factor Q for PLLSYSUSBCLK
515 pub mod PLLQ {
516 /// Offset (25 bits)
517 pub const offset: u32 = 25;
518 /// Mask (3 bits: 0b111 << 25)
519 pub const mask: u32 = 0b111 << offset;
520 /// Read-only values (empty)
521 pub mod R {}
522 /// Write-only values (empty)
523 pub mod W {}
524 /// Read-write values (empty)
525 pub mod RW {}
526 }
527
528 /// Main PLLSYSQ output enable
529 pub mod PLLQEN {
530 /// Offset (24 bits)
531 pub const offset: u32 = 24;
532 /// Mask (1 bit: 1 << 24)
533 pub const mask: u32 = 1 << offset;
534 /// Read-only values (empty)
535 pub mod R {}
536 /// Write-only values (empty)
537 pub mod W {}
538 /// Read-write values (empty)
539 pub mod RW {}
540 }
541
542 /// Main PLL division factor P for PPLSYSSAICLK
543 pub mod PLLP {
544 /// Offset (17 bits)
545 pub const offset: u32 = 17;
546 /// Mask (5 bits: 0b11111 << 17)
547 pub const mask: u32 = 0b11111 << offset;
548 /// Read-only values (empty)
549 pub mod R {}
550 /// Write-only values (empty)
551 pub mod W {}
552 /// Read-write values (empty)
553 pub mod RW {}
554 }
555
556 /// Main PLLSYSP output enable
557 pub mod PLLPEN {
558 /// Offset (16 bits)
559 pub const offset: u32 = 16;
560 /// Mask (1 bit: 1 << 16)
561 pub const mask: u32 = 1 << offset;
562 /// Read-only values (empty)
563 pub mod R {}
564 /// Write-only values (empty)
565 pub mod W {}
566 /// Read-write values (empty)
567 pub mod RW {}
568 }
569
570 /// Main PLLSYS multiplication factor N
571 pub mod PLLN {
572 /// Offset (8 bits)
573 pub const offset: u32 = 8;
574 /// Mask (7 bits: 0x7f << 8)
575 pub const mask: u32 = 0x7f << offset;
576 /// Read-only values (empty)
577 pub mod R {}
578 /// Write-only values (empty)
579 pub mod W {}
580 /// Read-write values (empty)
581 pub mod RW {}
582 }
583
584 /// Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
585 pub mod PLLM {
586 /// Offset (4 bits)
587 pub const offset: u32 = 4;
588 /// Mask (3 bits: 0b111 << 4)
589 pub const mask: u32 = 0b111 << offset;
590 /// Read-only values (empty)
591 pub mod R {}
592 /// Write-only values (empty)
593 pub mod W {}
594 /// Read-write values (empty)
595 pub mod RW {}
596 }
597
598 /// Main PLL, PLLSAI1 and PLLSAI2 entry clock source
599 pub mod PLLSRC {
600 /// Offset (0 bits)
601 pub const offset: u32 = 0;
602 /// Mask (2 bits: 0b11 << 0)
603 pub const mask: u32 = 0b11 << offset;
604 /// Read-only values (empty)
605 pub mod R {}
606 /// Write-only values (empty)
607 pub mod W {}
608 /// Read-write values (empty)
609 pub mod RW {}
610 }
611}
612
613/// PLLSAI1 configuration register
614pub mod PLLSAI1CFGR {
615
616 /// PLLSAI division factor R for PLLADC1CLK (ADC clock)
617 pub mod PLLR {
618 /// Offset (29 bits)
619 pub const offset: u32 = 29;
620 /// Mask (3 bits: 0b111 << 29)
621 pub const mask: u32 = 0b111 << offset;
622 /// Read-only values (empty)
623 pub mod R {}
624 /// Write-only values (empty)
625 pub mod W {}
626 /// Read-write values (empty)
627 pub mod RW {}
628 }
629
630 /// PLLSAI PLLADC1CLK output enable
631 pub mod PLLREN {
632 /// Offset (28 bits)
633 pub const offset: u32 = 28;
634 /// Mask (1 bit: 1 << 28)
635 pub const mask: u32 = 1 << offset;
636 /// Read-only values (empty)
637 pub mod R {}
638 /// Write-only values (empty)
639 pub mod W {}
640 /// Read-write values (empty)
641 pub mod RW {}
642 }
643
644 /// SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)
645 pub mod PLLQ {
646 /// Offset (25 bits)
647 pub const offset: u32 = 25;
648 /// Mask (3 bits: 0b111 << 25)
649 pub const mask: u32 = 0b111 << offset;
650 /// Read-only values (empty)
651 pub mod R {}
652 /// Write-only values (empty)
653 pub mod W {}
654 /// Read-write values (empty)
655 pub mod RW {}
656 }
657
658 /// SAIPLL PLLSAIUSBCLK output enable
659 pub mod PLLQEN {
660 /// Offset (24 bits)
661 pub const offset: u32 = 24;
662 /// Mask (1 bit: 1 << 24)
663 pub const mask: u32 = 1 << offset;
664 /// Read-only values (empty)
665 pub mod R {}
666 /// Write-only values (empty)
667 pub mod W {}
668 /// Read-write values (empty)
669 pub mod RW {}
670 }
671
672 /// SAI1PLL division factor P for PLLSAICLK (SAI1clock)
673 pub mod PLLP {
674 /// Offset (17 bits)
675 pub const offset: u32 = 17;
676 /// Mask (5 bits: 0b11111 << 17)
677 pub const mask: u32 = 0b11111 << offset;
678 /// Read-only values (empty)
679 pub mod R {}
680 /// Write-only values (empty)
681 pub mod W {}
682 /// Read-write values (empty)
683 pub mod RW {}
684 }
685
686 /// SAIPLL PLLSAI1CLK output enable
687 pub mod PLLPEN {
688 /// Offset (16 bits)
689 pub const offset: u32 = 16;
690 /// Mask (1 bit: 1 << 16)
691 pub const mask: u32 = 1 << offset;
692 /// Read-only values (empty)
693 pub mod R {}
694 /// Write-only values (empty)
695 pub mod W {}
696 /// Read-write values (empty)
697 pub mod RW {}
698 }
699
700 /// SAIPLL multiplication factor for VCO
701 pub mod PLLN {
702 /// Offset (8 bits)
703 pub const offset: u32 = 8;
704 /// Mask (7 bits: 0x7f << 8)
705 pub const mask: u32 = 0x7f << offset;
706 /// Read-only values (empty)
707 pub mod R {}
708 /// Write-only values (empty)
709 pub mod W {}
710 /// Read-write values (empty)
711 pub mod RW {}
712 }
713}
714
715/// Clock interrupt enable register
716pub mod CIER {
717
718 /// LSI2 ready interrupt enable
719 pub mod LSI2RDYIE {
720 /// Offset (11 bits)
721 pub const offset: u32 = 11;
722 /// Mask (1 bit: 1 << 11)
723 pub const mask: u32 = 1 << offset;
724 /// Read-only values (empty)
725 pub mod R {}
726 /// Write-only values (empty)
727 pub mod W {}
728 /// Read-write values (empty)
729 pub mod RW {}
730 }
731
732 /// HSI48 ready interrupt enable
733 pub mod HSI48RDYIE {
734 /// Offset (10 bits)
735 pub const offset: u32 = 10;
736 /// Mask (1 bit: 1 << 10)
737 pub const mask: u32 = 1 << offset;
738 /// Read-only values (empty)
739 pub mod R {}
740 /// Write-only values (empty)
741 pub mod W {}
742 /// Read-write values (empty)
743 pub mod RW {}
744 }
745
746 /// LSE clock security system interrupt enable
747 pub mod LSECSSIE {
748 /// Offset (9 bits)
749 pub const offset: u32 = 9;
750 /// Mask (1 bit: 1 << 9)
751 pub const mask: u32 = 1 << offset;
752 /// Read-only values (empty)
753 pub mod R {}
754 /// Write-only values (empty)
755 pub mod W {}
756 /// Read-write values (empty)
757 pub mod RW {}
758 }
759
760 /// PLLSAI1 ready interrupt enable
761 pub mod PLLSAI1RDYIE {
762 /// Offset (6 bits)
763 pub const offset: u32 = 6;
764 /// Mask (1 bit: 1 << 6)
765 pub const mask: u32 = 1 << offset;
766 /// Read-only values (empty)
767 pub mod R {}
768 /// Write-only values (empty)
769 pub mod W {}
770 /// Read-write values (empty)
771 pub mod RW {}
772 }
773
774 /// PLLSYS ready interrupt enable
775 pub mod PLLRDYIE {
776 /// Offset (5 bits)
777 pub const offset: u32 = 5;
778 /// Mask (1 bit: 1 << 5)
779 pub const mask: u32 = 1 << offset;
780 /// Read-only values (empty)
781 pub mod R {}
782 /// Write-only values (empty)
783 pub mod W {}
784 /// Read-write values (empty)
785 pub mod RW {}
786 }
787
788 /// HSE ready interrupt enable
789 pub mod HSERDYIE {
790 /// Offset (4 bits)
791 pub const offset: u32 = 4;
792 /// Mask (1 bit: 1 << 4)
793 pub const mask: u32 = 1 << offset;
794 /// Read-only values (empty)
795 pub mod R {}
796 /// Write-only values (empty)
797 pub mod W {}
798 /// Read-write values (empty)
799 pub mod RW {}
800 }
801
802 /// HSI ready interrupt enable
803 pub mod HSIRDYIE {
804 /// Offset (3 bits)
805 pub const offset: u32 = 3;
806 /// Mask (1 bit: 1 << 3)
807 pub const mask: u32 = 1 << offset;
808 /// Read-only values (empty)
809 pub mod R {}
810 /// Write-only values (empty)
811 pub mod W {}
812 /// Read-write values (empty)
813 pub mod RW {}
814 }
815
816 /// MSI ready interrupt enable
817 pub mod MSIRDYIE {
818 /// Offset (2 bits)
819 pub const offset: u32 = 2;
820 /// Mask (1 bit: 1 << 2)
821 pub const mask: u32 = 1 << offset;
822 /// Read-only values (empty)
823 pub mod R {}
824 /// Write-only values (empty)
825 pub mod W {}
826 /// Read-write values (empty)
827 pub mod RW {}
828 }
829
830 /// LSE ready interrupt enable
831 pub mod LSERDYIE {
832 /// Offset (1 bits)
833 pub const offset: u32 = 1;
834 /// Mask (1 bit: 1 << 1)
835 pub const mask: u32 = 1 << offset;
836 /// Read-only values (empty)
837 pub mod R {}
838 /// Write-only values (empty)
839 pub mod W {}
840 /// Read-write values (empty)
841 pub mod RW {}
842 }
843
844 /// LSI1 ready interrupt enable
845 pub mod LSI1RDYIE {
846 /// Offset (0 bits)
847 pub const offset: u32 = 0;
848 /// Mask (1 bit: 1 << 0)
849 pub const mask: u32 = 1 << offset;
850 /// Read-only values (empty)
851 pub mod R {}
852 /// Write-only values (empty)
853 pub mod W {}
854 /// Read-write values (empty)
855 pub mod RW {}
856 }
857}
858
859/// Clock interrupt flag register
860pub mod CIFR {
861
862 /// LSI2 ready interrupt flag
863 pub mod LSI2RDYF {
864 /// Offset (11 bits)
865 pub const offset: u32 = 11;
866 /// Mask (1 bit: 1 << 11)
867 pub const mask: u32 = 1 << offset;
868 /// Read-only values (empty)
869 pub mod R {}
870 /// Write-only values (empty)
871 pub mod W {}
872 /// Read-write values (empty)
873 pub mod RW {}
874 }
875
876 /// HSI48 ready interrupt flag
877 pub mod HSI48RDYF {
878 /// Offset (10 bits)
879 pub const offset: u32 = 10;
880 /// Mask (1 bit: 1 << 10)
881 pub const mask: u32 = 1 << offset;
882 /// Read-only values (empty)
883 pub mod R {}
884 /// Write-only values (empty)
885 pub mod W {}
886 /// Read-write values (empty)
887 pub mod RW {}
888 }
889
890 /// LSE Clock security system interrupt flag
891 pub mod LSECSSF {
892 /// Offset (9 bits)
893 pub const offset: u32 = 9;
894 /// Mask (1 bit: 1 << 9)
895 pub const mask: u32 = 1 << offset;
896 /// Read-only values (empty)
897 pub mod R {}
898 /// Write-only values (empty)
899 pub mod W {}
900 /// Read-write values (empty)
901 pub mod RW {}
902 }
903
904 /// HSE Clock security system interrupt flag
905 pub mod HSECSSF {
906 /// Offset (8 bits)
907 pub const offset: u32 = 8;
908 /// Mask (1 bit: 1 << 8)
909 pub const mask: u32 = 1 << offset;
910 /// Read-only values (empty)
911 pub mod R {}
912 /// Write-only values (empty)
913 pub mod W {}
914 /// Read-write values (empty)
915 pub mod RW {}
916 }
917
918 /// PLLSAI1 ready interrupt flag
919 pub mod PLLSAI1RDYF {
920 /// Offset (6 bits)
921 pub const offset: u32 = 6;
922 /// Mask (1 bit: 1 << 6)
923 pub const mask: u32 = 1 << offset;
924 /// Read-only values (empty)
925 pub mod R {}
926 /// Write-only values (empty)
927 pub mod W {}
928 /// Read-write values (empty)
929 pub mod RW {}
930 }
931
932 /// PLL ready interrupt flag
933 pub mod PLLRDYF {
934 /// Offset (5 bits)
935 pub const offset: u32 = 5;
936 /// Mask (1 bit: 1 << 5)
937 pub const mask: u32 = 1 << offset;
938 /// Read-only values (empty)
939 pub mod R {}
940 /// Write-only values (empty)
941 pub mod W {}
942 /// Read-write values (empty)
943 pub mod RW {}
944 }
945
946 /// HSE ready interrupt flag
947 pub mod HSERDYF {
948 /// Offset (4 bits)
949 pub const offset: u32 = 4;
950 /// Mask (1 bit: 1 << 4)
951 pub const mask: u32 = 1 << offset;
952 /// Read-only values (empty)
953 pub mod R {}
954 /// Write-only values (empty)
955 pub mod W {}
956 /// Read-write values (empty)
957 pub mod RW {}
958 }
959
960 /// HSI ready interrupt flag
961 pub mod HSIRDYF {
962 /// Offset (3 bits)
963 pub const offset: u32 = 3;
964 /// Mask (1 bit: 1 << 3)
965 pub const mask: u32 = 1 << offset;
966 /// Read-only values (empty)
967 pub mod R {}
968 /// Write-only values (empty)
969 pub mod W {}
970 /// Read-write values (empty)
971 pub mod RW {}
972 }
973
974 /// MSI ready interrupt flag
975 pub mod MSIRDYF {
976 /// Offset (2 bits)
977 pub const offset: u32 = 2;
978 /// Mask (1 bit: 1 << 2)
979 pub const mask: u32 = 1 << offset;
980 /// Read-only values (empty)
981 pub mod R {}
982 /// Write-only values (empty)
983 pub mod W {}
984 /// Read-write values (empty)
985 pub mod RW {}
986 }
987
988 /// LSE ready interrupt flag
989 pub mod LSERDYF {
990 /// Offset (1 bits)
991 pub const offset: u32 = 1;
992 /// Mask (1 bit: 1 << 1)
993 pub const mask: u32 = 1 << offset;
994 /// Read-only values (empty)
995 pub mod R {}
996 /// Write-only values (empty)
997 pub mod W {}
998 /// Read-write values (empty)
999 pub mod RW {}
1000 }
1001
1002 /// LSI1 ready interrupt flag
1003 pub mod LSI1RDYF {
1004 /// Offset (0 bits)
1005 pub const offset: u32 = 0;
1006 /// Mask (1 bit: 1 << 0)
1007 pub const mask: u32 = 1 << offset;
1008 /// Read-only values (empty)
1009 pub mod R {}
1010 /// Write-only values (empty)
1011 pub mod W {}
1012 /// Read-write values (empty)
1013 pub mod RW {}
1014 }
1015}
1016
1017/// Clock interrupt clear register
1018pub mod CICR {
1019
1020 /// LSI2 ready interrupt clear
1021 pub mod LSI2RDYC {
1022 /// Offset (11 bits)
1023 pub const offset: u32 = 11;
1024 /// Mask (1 bit: 1 << 11)
1025 pub const mask: u32 = 1 << offset;
1026 /// Read-only values (empty)
1027 pub mod R {}
1028 /// Write-only values (empty)
1029 pub mod W {}
1030 /// Read-write values (empty)
1031 pub mod RW {}
1032 }
1033
1034 /// HSI48 ready interrupt clear
1035 pub mod HSI48RDYC {
1036 /// Offset (10 bits)
1037 pub const offset: u32 = 10;
1038 /// Mask (1 bit: 1 << 10)
1039 pub const mask: u32 = 1 << offset;
1040 /// Read-only values (empty)
1041 pub mod R {}
1042 /// Write-only values (empty)
1043 pub mod W {}
1044 /// Read-write values (empty)
1045 pub mod RW {}
1046 }
1047
1048 /// LSE Clock security system interrupt clear
1049 pub mod LSECSSC {
1050 /// Offset (9 bits)
1051 pub const offset: u32 = 9;
1052 /// Mask (1 bit: 1 << 9)
1053 pub const mask: u32 = 1 << offset;
1054 /// Read-only values (empty)
1055 pub mod R {}
1056 /// Write-only values (empty)
1057 pub mod W {}
1058 /// Read-write values (empty)
1059 pub mod RW {}
1060 }
1061
1062 /// HSE Clock security system interrupt clear
1063 pub mod HSECSSC {
1064 /// Offset (8 bits)
1065 pub const offset: u32 = 8;
1066 /// Mask (1 bit: 1 << 8)
1067 pub const mask: u32 = 1 << offset;
1068 /// Read-only values (empty)
1069 pub mod R {}
1070 /// Write-only values (empty)
1071 pub mod W {}
1072 /// Read-write values (empty)
1073 pub mod RW {}
1074 }
1075
1076 /// PLLSAI1 ready interrupt clear
1077 pub mod PLLSAI1RDYC {
1078 /// Offset (6 bits)
1079 pub const offset: u32 = 6;
1080 /// Mask (1 bit: 1 << 6)
1081 pub const mask: u32 = 1 << offset;
1082 /// Read-only values (empty)
1083 pub mod R {}
1084 /// Write-only values (empty)
1085 pub mod W {}
1086 /// Read-write values (empty)
1087 pub mod RW {}
1088 }
1089
1090 /// PLL ready interrupt clear
1091 pub mod PLLRDYC {
1092 /// Offset (5 bits)
1093 pub const offset: u32 = 5;
1094 /// Mask (1 bit: 1 << 5)
1095 pub const mask: u32 = 1 << offset;
1096 /// Read-only values (empty)
1097 pub mod R {}
1098 /// Write-only values (empty)
1099 pub mod W {}
1100 /// Read-write values (empty)
1101 pub mod RW {}
1102 }
1103
1104 /// HSE ready interrupt clear
1105 pub mod HSERDYC {
1106 /// Offset (4 bits)
1107 pub const offset: u32 = 4;
1108 /// Mask (1 bit: 1 << 4)
1109 pub const mask: u32 = 1 << offset;
1110 /// Read-only values (empty)
1111 pub mod R {}
1112 /// Write-only values (empty)
1113 pub mod W {}
1114 /// Read-write values (empty)
1115 pub mod RW {}
1116 }
1117
1118 /// HSI ready interrupt clear
1119 pub mod HSIRDYC {
1120 /// Offset (3 bits)
1121 pub const offset: u32 = 3;
1122 /// Mask (1 bit: 1 << 3)
1123 pub const mask: u32 = 1 << offset;
1124 /// Read-only values (empty)
1125 pub mod R {}
1126 /// Write-only values (empty)
1127 pub mod W {}
1128 /// Read-write values (empty)
1129 pub mod RW {}
1130 }
1131
1132 /// MSI ready interrupt clear
1133 pub mod MSIRDYC {
1134 /// Offset (2 bits)
1135 pub const offset: u32 = 2;
1136 /// Mask (1 bit: 1 << 2)
1137 pub const mask: u32 = 1 << offset;
1138 /// Read-only values (empty)
1139 pub mod R {}
1140 /// Write-only values (empty)
1141 pub mod W {}
1142 /// Read-write values (empty)
1143 pub mod RW {}
1144 }
1145
1146 /// LSE ready interrupt clear
1147 pub mod LSERDYC {
1148 /// Offset (1 bits)
1149 pub const offset: u32 = 1;
1150 /// Mask (1 bit: 1 << 1)
1151 pub const mask: u32 = 1 << offset;
1152 /// Read-only values (empty)
1153 pub mod R {}
1154 /// Write-only values (empty)
1155 pub mod W {}
1156 /// Read-write values (empty)
1157 pub mod RW {}
1158 }
1159
1160 /// LSI1 ready interrupt clear
1161 pub mod LSI1RDYC {
1162 /// Offset (0 bits)
1163 pub const offset: u32 = 0;
1164 /// Mask (1 bit: 1 << 0)
1165 pub const mask: u32 = 1 << offset;
1166 /// Read-only values (empty)
1167 pub mod R {}
1168 /// Write-only values (empty)
1169 pub mod W {}
1170 /// Read-write values (empty)
1171 pub mod RW {}
1172 }
1173}
1174
1175/// Step Down converter control register
1176pub mod SMPSCR {
1177
1178 /// Step Down converter clock switch status
1179 pub mod SMPSSWS {
1180 /// Offset (8 bits)
1181 pub const offset: u32 = 8;
1182 /// Mask (2 bits: 0b11 << 8)
1183 pub const mask: u32 = 0b11 << offset;
1184 /// Read-only values (empty)
1185 pub mod R {}
1186 /// Write-only values (empty)
1187 pub mod W {}
1188 /// Read-write values (empty)
1189 pub mod RW {}
1190 }
1191
1192 /// Step Down converter clock prescaler
1193 pub mod SMPSDIV {
1194 /// Offset (4 bits)
1195 pub const offset: u32 = 4;
1196 /// Mask (2 bits: 0b11 << 4)
1197 pub const mask: u32 = 0b11 << offset;
1198 /// Read-only values (empty)
1199 pub mod R {}
1200 /// Write-only values (empty)
1201 pub mod W {}
1202 /// Read-write values (empty)
1203 pub mod RW {}
1204 }
1205
1206 /// Step Down converter clock selection
1207 pub mod SMPSSEL {
1208 /// Offset (0 bits)
1209 pub const offset: u32 = 0;
1210 /// Mask (2 bits: 0b11 << 0)
1211 pub const mask: u32 = 0b11 << offset;
1212 /// Read-only values (empty)
1213 pub mod R {}
1214 /// Write-only values (empty)
1215 pub mod W {}
1216 /// Read-write values (empty)
1217 pub mod RW {}
1218 }
1219}
1220
1221/// AHB1 peripheral reset register
1222pub mod AHB1RSTR {
1223
1224 /// Touch Sensing Controller reset
1225 pub mod TSCRST {
1226 /// Offset (16 bits)
1227 pub const offset: u32 = 16;
1228 /// Mask (1 bit: 1 << 16)
1229 pub const mask: u32 = 1 << offset;
1230 /// Read-only values (empty)
1231 pub mod R {}
1232 /// Write-only values (empty)
1233 pub mod W {}
1234 /// Read-write values (empty)
1235 pub mod RW {}
1236 }
1237
1238 /// CRC reset
1239 pub mod CRCRST {
1240 /// Offset (12 bits)
1241 pub const offset: u32 = 12;
1242 /// Mask (1 bit: 1 << 12)
1243 pub const mask: u32 = 1 << offset;
1244 /// Read-only values (empty)
1245 pub mod R {}
1246 /// Write-only values (empty)
1247 pub mod W {}
1248 /// Read-write values (empty)
1249 pub mod RW {}
1250 }
1251
1252 /// DMAMUX reset
1253 pub mod DMAMUXRST {
1254 /// Offset (2 bits)
1255 pub const offset: u32 = 2;
1256 /// Mask (1 bit: 1 << 2)
1257 pub const mask: u32 = 1 << offset;
1258 /// Read-only values (empty)
1259 pub mod R {}
1260 /// Write-only values (empty)
1261 pub mod W {}
1262 /// Read-write values (empty)
1263 pub mod RW {}
1264 }
1265
1266 /// DMA2 reset
1267 pub mod DMA2RST {
1268 /// Offset (1 bits)
1269 pub const offset: u32 = 1;
1270 /// Mask (1 bit: 1 << 1)
1271 pub const mask: u32 = 1 << offset;
1272 /// Read-only values (empty)
1273 pub mod R {}
1274 /// Write-only values (empty)
1275 pub mod W {}
1276 /// Read-write values (empty)
1277 pub mod RW {}
1278 }
1279
1280 /// DMA1 reset
1281 pub mod DMA1RST {
1282 /// Offset (0 bits)
1283 pub const offset: u32 = 0;
1284 /// Mask (1 bit: 1 << 0)
1285 pub const mask: u32 = 1 << offset;
1286 /// Read-only values (empty)
1287 pub mod R {}
1288 /// Write-only values (empty)
1289 pub mod W {}
1290 /// Read-write values (empty)
1291 pub mod RW {}
1292 }
1293}
1294
1295/// AHB2 peripheral reset register
1296pub mod AHB2RSTR {
1297
1298 /// AES1 hardware accelerator reset
1299 pub mod AES1RST {
1300 /// Offset (16 bits)
1301 pub const offset: u32 = 16;
1302 /// Mask (1 bit: 1 << 16)
1303 pub const mask: u32 = 1 << offset;
1304 /// Read-only values (empty)
1305 pub mod R {}
1306 /// Write-only values (empty)
1307 pub mod W {}
1308 /// Read-write values (empty)
1309 pub mod RW {}
1310 }
1311
1312 /// ADC reset
1313 pub mod ADCRST {
1314 /// Offset (13 bits)
1315 pub const offset: u32 = 13;
1316 /// Mask (1 bit: 1 << 13)
1317 pub const mask: u32 = 1 << offset;
1318 /// Read-only values (empty)
1319 pub mod R {}
1320 /// Write-only values (empty)
1321 pub mod W {}
1322 /// Read-write values (empty)
1323 pub mod RW {}
1324 }
1325
1326 /// IO port H reset
1327 pub mod GPIOHRST {
1328 /// Offset (7 bits)
1329 pub const offset: u32 = 7;
1330 /// Mask (1 bit: 1 << 7)
1331 pub const mask: u32 = 1 << offset;
1332 /// Read-only values (empty)
1333 pub mod R {}
1334 /// Write-only values (empty)
1335 pub mod W {}
1336 /// Read-write values (empty)
1337 pub mod RW {}
1338 }
1339
1340 /// IO port E reset
1341 pub mod GPIOERST {
1342 /// Offset (4 bits)
1343 pub const offset: u32 = 4;
1344 /// Mask (1 bit: 1 << 4)
1345 pub const mask: u32 = 1 << offset;
1346 /// Read-only values (empty)
1347 pub mod R {}
1348 /// Write-only values (empty)
1349 pub mod W {}
1350 /// Read-write values (empty)
1351 pub mod RW {}
1352 }
1353
1354 /// IO port D reset
1355 pub mod GPIODRST {
1356 /// Offset (3 bits)
1357 pub const offset: u32 = 3;
1358 /// Mask (1 bit: 1 << 3)
1359 pub const mask: u32 = 1 << offset;
1360 /// Read-only values (empty)
1361 pub mod R {}
1362 /// Write-only values (empty)
1363 pub mod W {}
1364 /// Read-write values (empty)
1365 pub mod RW {}
1366 }
1367
1368 /// IO port C reset
1369 pub mod GPIOCRST {
1370 /// Offset (2 bits)
1371 pub const offset: u32 = 2;
1372 /// Mask (1 bit: 1 << 2)
1373 pub const mask: u32 = 1 << offset;
1374 /// Read-only values (empty)
1375 pub mod R {}
1376 /// Write-only values (empty)
1377 pub mod W {}
1378 /// Read-write values (empty)
1379 pub mod RW {}
1380 }
1381
1382 /// IO port B reset
1383 pub mod GPIOBRST {
1384 /// Offset (1 bits)
1385 pub const offset: u32 = 1;
1386 /// Mask (1 bit: 1 << 1)
1387 pub const mask: u32 = 1 << offset;
1388 /// Read-only values (empty)
1389 pub mod R {}
1390 /// Write-only values (empty)
1391 pub mod W {}
1392 /// Read-write values (empty)
1393 pub mod RW {}
1394 }
1395
1396 /// IO port A reset
1397 pub mod GPIOARST {
1398 /// Offset (0 bits)
1399 pub const offset: u32 = 0;
1400 /// Mask (1 bit: 1 << 0)
1401 pub const mask: u32 = 1 << offset;
1402 /// Read-only values (empty)
1403 pub mod R {}
1404 /// Write-only values (empty)
1405 pub mod W {}
1406 /// Read-write values (empty)
1407 pub mod RW {}
1408 }
1409}
1410
1411/// AHB3 peripheral reset register
1412pub mod AHB3RSTR {
1413
1414 /// Flash interface reset
1415 pub mod FLASHRST {
1416 /// Offset (25 bits)
1417 pub const offset: u32 = 25;
1418 /// Mask (1 bit: 1 << 25)
1419 pub const mask: u32 = 1 << offset;
1420 /// Read-only values (empty)
1421 pub mod R {}
1422 /// Write-only values (empty)
1423 pub mod W {}
1424 /// Read-write values (empty)
1425 pub mod RW {}
1426 }
1427
1428 /// IPCC interface reset
1429 pub mod IPCCRST {
1430 /// Offset (20 bits)
1431 pub const offset: u32 = 20;
1432 /// Mask (1 bit: 1 << 20)
1433 pub const mask: u32 = 1 << offset;
1434 /// Read-only values (empty)
1435 pub mod R {}
1436 /// Write-only values (empty)
1437 pub mod W {}
1438 /// Read-write values (empty)
1439 pub mod RW {}
1440 }
1441
1442 /// HSEM interface reset
1443 pub mod HSEMRST {
1444 /// Offset (19 bits)
1445 pub const offset: u32 = 19;
1446 /// Mask (1 bit: 1 << 19)
1447 pub const mask: u32 = 1 << offset;
1448 /// Read-only values (empty)
1449 pub mod R {}
1450 /// Write-only values (empty)
1451 pub mod W {}
1452 /// Read-write values (empty)
1453 pub mod RW {}
1454 }
1455
1456 /// RNG interface reset
1457 pub mod RNGRST {
1458 /// Offset (18 bits)
1459 pub const offset: u32 = 18;
1460 /// Mask (1 bit: 1 << 18)
1461 pub const mask: u32 = 1 << offset;
1462 /// Read-only values (empty)
1463 pub mod R {}
1464 /// Write-only values (empty)
1465 pub mod W {}
1466 /// Read-write values (empty)
1467 pub mod RW {}
1468 }
1469
1470 /// AES2 interface reset
1471 pub mod AES2RST {
1472 /// Offset (17 bits)
1473 pub const offset: u32 = 17;
1474 /// Mask (1 bit: 1 << 17)
1475 pub const mask: u32 = 1 << offset;
1476 /// Read-only values (empty)
1477 pub mod R {}
1478 /// Write-only values (empty)
1479 pub mod W {}
1480 /// Read-write values (empty)
1481 pub mod RW {}
1482 }
1483
1484 /// PKA interface reset
1485 pub mod PKARST {
1486 /// Offset (16 bits)
1487 pub const offset: u32 = 16;
1488 /// Mask (1 bit: 1 << 16)
1489 pub const mask: u32 = 1 << offset;
1490 /// Read-only values (empty)
1491 pub mod R {}
1492 /// Write-only values (empty)
1493 pub mod W {}
1494 /// Read-write values (empty)
1495 pub mod RW {}
1496 }
1497
1498 /// Quad SPI memory interface reset
1499 pub mod QSPIRST {
1500 /// Offset (8 bits)
1501 pub const offset: u32 = 8;
1502 /// Mask (1 bit: 1 << 8)
1503 pub const mask: u32 = 1 << offset;
1504 /// Read-only values (empty)
1505 pub mod R {}
1506 /// Write-only values (empty)
1507 pub mod W {}
1508 /// Read-write values (empty)
1509 pub mod RW {}
1510 }
1511}
1512
1513/// APB1 peripheral reset register 1
1514pub mod APB1RSTR1 {
1515
1516 /// Low Power Timer 1 reset
1517 pub mod LPTIM1RST {
1518 /// Offset (31 bits)
1519 pub const offset: u32 = 31;
1520 /// Mask (1 bit: 1 << 31)
1521 pub const mask: u32 = 1 << offset;
1522 /// Read-only values (empty)
1523 pub mod R {}
1524 /// Write-only values (empty)
1525 pub mod W {}
1526 /// Read-write values (empty)
1527 pub mod RW {}
1528 }
1529
1530 /// USB FS reset
1531 pub mod USBFSRST {
1532 /// Offset (26 bits)
1533 pub const offset: u32 = 26;
1534 /// Mask (1 bit: 1 << 26)
1535 pub const mask: u32 = 1 << offset;
1536 /// Read-only values (empty)
1537 pub mod R {}
1538 /// Write-only values (empty)
1539 pub mod W {}
1540 /// Read-write values (empty)
1541 pub mod RW {}
1542 }
1543
1544 /// CRS reset
1545 pub mod CRSRST {
1546 /// Offset (24 bits)
1547 pub const offset: u32 = 24;
1548 /// Mask (1 bit: 1 << 24)
1549 pub const mask: u32 = 1 << offset;
1550 /// Read-only values (empty)
1551 pub mod R {}
1552 /// Write-only values (empty)
1553 pub mod W {}
1554 /// Read-write values (empty)
1555 pub mod RW {}
1556 }
1557
1558 /// I2C3 reset
1559 pub mod I2C3RST {
1560 /// Offset (23 bits)
1561 pub const offset: u32 = 23;
1562 /// Mask (1 bit: 1 << 23)
1563 pub const mask: u32 = 1 << offset;
1564 /// Read-only values (empty)
1565 pub mod R {}
1566 /// Write-only values (empty)
1567 pub mod W {}
1568 /// Read-write values (empty)
1569 pub mod RW {}
1570 }
1571
1572 /// I2C1 reset
1573 pub mod I2C1RST {
1574 /// Offset (21 bits)
1575 pub const offset: u32 = 21;
1576 /// Mask (1 bit: 1 << 21)
1577 pub const mask: u32 = 1 << offset;
1578 /// Read-only values (empty)
1579 pub mod R {}
1580 /// Write-only values (empty)
1581 pub mod W {}
1582 /// Read-write values (empty)
1583 pub mod RW {}
1584 }
1585
1586 /// SPI2 reset
1587 pub mod SPI2RST {
1588 /// Offset (14 bits)
1589 pub const offset: u32 = 14;
1590 /// Mask (1 bit: 1 << 14)
1591 pub const mask: u32 = 1 << offset;
1592 /// Read-only values (empty)
1593 pub mod R {}
1594 /// Write-only values (empty)
1595 pub mod W {}
1596 /// Read-write values (empty)
1597 pub mod RW {}
1598 }
1599
1600 /// LCD interface reset
1601 pub mod LCDRST {
1602 /// Offset (9 bits)
1603 pub const offset: u32 = 9;
1604 /// Mask (1 bit: 1 << 9)
1605 pub const mask: u32 = 1 << offset;
1606 /// Read-only values (empty)
1607 pub mod R {}
1608 /// Write-only values (empty)
1609 pub mod W {}
1610 /// Read-write values (empty)
1611 pub mod RW {}
1612 }
1613
1614 /// TIM2 timer reset
1615 pub mod TIM2RST {
1616 /// Offset (0 bits)
1617 pub const offset: u32 = 0;
1618 /// Mask (1 bit: 1 << 0)
1619 pub const mask: u32 = 1 << offset;
1620 /// Read-only values (empty)
1621 pub mod R {}
1622 /// Write-only values (empty)
1623 pub mod W {}
1624 /// Read-write values (empty)
1625 pub mod RW {}
1626 }
1627}
1628
1629/// APB1 peripheral reset register 2
1630pub mod APB1RSTR2 {
1631
1632 /// Low-power timer 2 reset
1633 pub mod LPTIM2RST {
1634 /// Offset (5 bits)
1635 pub const offset: u32 = 5;
1636 /// Mask (1 bit: 1 << 5)
1637 pub const mask: u32 = 1 << offset;
1638 /// Read-only values (empty)
1639 pub mod R {}
1640 /// Write-only values (empty)
1641 pub mod W {}
1642 /// Read-write values (empty)
1643 pub mod RW {}
1644 }
1645
1646 /// Low-power UART 1 reset
1647 pub mod LPUART1RST {
1648 /// Offset (0 bits)
1649 pub const offset: u32 = 0;
1650 /// Mask (1 bit: 1 << 0)
1651 pub const mask: u32 = 1 << offset;
1652 /// Read-only values (empty)
1653 pub mod R {}
1654 /// Write-only values (empty)
1655 pub mod W {}
1656 /// Read-write values (empty)
1657 pub mod RW {}
1658 }
1659}
1660
1661/// APB2 peripheral reset register
1662pub mod APB2RSTR {
1663
1664 /// Serial audio interface 1 (SAI1) reset
1665 pub mod SAI1RST {
1666 /// Offset (21 bits)
1667 pub const offset: u32 = 21;
1668 /// Mask (1 bit: 1 << 21)
1669 pub const mask: u32 = 1 << offset;
1670 /// Read-only values (empty)
1671 pub mod R {}
1672 /// Write-only values (empty)
1673 pub mod W {}
1674 /// Read-write values (empty)
1675 pub mod RW {}
1676 }
1677
1678 /// TIM17 timer reset
1679 pub mod TIM17RST {
1680 /// Offset (18 bits)
1681 pub const offset: u32 = 18;
1682 /// Mask (1 bit: 1 << 18)
1683 pub const mask: u32 = 1 << offset;
1684 /// Read-only values (empty)
1685 pub mod R {}
1686 /// Write-only values (empty)
1687 pub mod W {}
1688 /// Read-write values (empty)
1689 pub mod RW {}
1690 }
1691
1692 /// TIM16 timer reset
1693 pub mod TIM16RST {
1694 /// Offset (17 bits)
1695 pub const offset: u32 = 17;
1696 /// Mask (1 bit: 1 << 17)
1697 pub const mask: u32 = 1 << offset;
1698 /// Read-only values (empty)
1699 pub mod R {}
1700 /// Write-only values (empty)
1701 pub mod W {}
1702 /// Read-write values (empty)
1703 pub mod RW {}
1704 }
1705
1706 /// USART1 reset
1707 pub mod USART1RST {
1708 /// Offset (14 bits)
1709 pub const offset: u32 = 14;
1710 /// Mask (1 bit: 1 << 14)
1711 pub const mask: u32 = 1 << offset;
1712 /// Read-only values (empty)
1713 pub mod R {}
1714 /// Write-only values (empty)
1715 pub mod W {}
1716 /// Read-write values (empty)
1717 pub mod RW {}
1718 }
1719
1720 /// SPI1 reset
1721 pub mod SPI1RST {
1722 /// Offset (12 bits)
1723 pub const offset: u32 = 12;
1724 /// Mask (1 bit: 1 << 12)
1725 pub const mask: u32 = 1 << offset;
1726 /// Read-only values (empty)
1727 pub mod R {}
1728 /// Write-only values (empty)
1729 pub mod W {}
1730 /// Read-write values (empty)
1731 pub mod RW {}
1732 }
1733
1734 /// TIM1 timer reset
1735 pub mod TIM1RST {
1736 /// Offset (11 bits)
1737 pub const offset: u32 = 11;
1738 /// Mask (1 bit: 1 << 11)
1739 pub const mask: u32 = 1 << offset;
1740 /// Read-only values (empty)
1741 pub mod R {}
1742 /// Write-only values (empty)
1743 pub mod W {}
1744 /// Read-write values (empty)
1745 pub mod RW {}
1746 }
1747}
1748
1749/// APB3 peripheral reset register
1750pub mod APB3RSTR {
1751
1752 /// Radio system BLE reset
1753 pub mod RFRST {
1754 /// Offset (0 bits)
1755 pub const offset: u32 = 0;
1756 /// Mask (1 bit: 1 << 0)
1757 pub const mask: u32 = 1 << offset;
1758 /// Read-only values (empty)
1759 pub mod R {}
1760 /// Write-only values (empty)
1761 pub mod W {}
1762 /// Read-write values (empty)
1763 pub mod RW {}
1764 }
1765}
1766
1767/// AHB1 peripheral clock enable register
1768pub mod AHB1ENR {
1769
1770 /// Touch Sensing Controller clock enable
1771 pub mod TSCEN {
1772 /// Offset (16 bits)
1773 pub const offset: u32 = 16;
1774 /// Mask (1 bit: 1 << 16)
1775 pub const mask: u32 = 1 << offset;
1776 /// Read-only values (empty)
1777 pub mod R {}
1778 /// Write-only values (empty)
1779 pub mod W {}
1780 /// Read-write values (empty)
1781 pub mod RW {}
1782 }
1783
1784 /// CPU1 CRC clock enable
1785 pub mod CRCEN {
1786 /// Offset (12 bits)
1787 pub const offset: u32 = 12;
1788 /// Mask (1 bit: 1 << 12)
1789 pub const mask: u32 = 1 << offset;
1790 /// Read-only values (empty)
1791 pub mod R {}
1792 /// Write-only values (empty)
1793 pub mod W {}
1794 /// Read-write values (empty)
1795 pub mod RW {}
1796 }
1797
1798 /// DMAMUX clock enable
1799 pub mod DMAMUXEN {
1800 /// Offset (2 bits)
1801 pub const offset: u32 = 2;
1802 /// Mask (1 bit: 1 << 2)
1803 pub const mask: u32 = 1 << offset;
1804 /// Read-only values (empty)
1805 pub mod R {}
1806 /// Write-only values (empty)
1807 pub mod W {}
1808 /// Read-write values (empty)
1809 pub mod RW {}
1810 }
1811
1812 /// DMA2 clock enable
1813 pub mod DMA2EN {
1814 /// Offset (1 bits)
1815 pub const offset: u32 = 1;
1816 /// Mask (1 bit: 1 << 1)
1817 pub const mask: u32 = 1 << offset;
1818 /// Read-only values (empty)
1819 pub mod R {}
1820 /// Write-only values (empty)
1821 pub mod W {}
1822 /// Read-write values (empty)
1823 pub mod RW {}
1824 }
1825
1826 /// DMA1 clock enable
1827 pub mod DMA1EN {
1828 /// Offset (0 bits)
1829 pub const offset: u32 = 0;
1830 /// Mask (1 bit: 1 << 0)
1831 pub const mask: u32 = 1 << offset;
1832 /// Read-only values (empty)
1833 pub mod R {}
1834 /// Write-only values (empty)
1835 pub mod W {}
1836 /// Read-write values (empty)
1837 pub mod RW {}
1838 }
1839}
1840
1841/// AHB2 peripheral clock enable register
1842pub mod AHB2ENR {
1843
1844 /// AES1 accelerator clock enable
1845 pub mod AES1EN {
1846 /// Offset (16 bits)
1847 pub const offset: u32 = 16;
1848 /// Mask (1 bit: 1 << 16)
1849 pub const mask: u32 = 1 << offset;
1850 /// Read-only values (empty)
1851 pub mod R {}
1852 /// Write-only values (empty)
1853 pub mod W {}
1854 /// Read-write values (empty)
1855 pub mod RW {}
1856 }
1857
1858 /// ADC clock enable
1859 pub mod ADCEN {
1860 /// Offset (13 bits)
1861 pub const offset: u32 = 13;
1862 /// Mask (1 bit: 1 << 13)
1863 pub const mask: u32 = 1 << offset;
1864 /// Read-only values (empty)
1865 pub mod R {}
1866 /// Write-only values (empty)
1867 pub mod W {}
1868 /// Read-write values (empty)
1869 pub mod RW {}
1870 }
1871
1872 /// IO port H clock enable
1873 pub mod GPIOHEN {
1874 /// Offset (7 bits)
1875 pub const offset: u32 = 7;
1876 /// Mask (1 bit: 1 << 7)
1877 pub const mask: u32 = 1 << offset;
1878 /// Read-only values (empty)
1879 pub mod R {}
1880 /// Write-only values (empty)
1881 pub mod W {}
1882 /// Read-write values (empty)
1883 pub mod RW {}
1884 }
1885
1886 /// IO port E clock enable
1887 pub mod GPIOEEN {
1888 /// Offset (4 bits)
1889 pub const offset: u32 = 4;
1890 /// Mask (1 bit: 1 << 4)
1891 pub const mask: u32 = 1 << offset;
1892 /// Read-only values (empty)
1893 pub mod R {}
1894 /// Write-only values (empty)
1895 pub mod W {}
1896 /// Read-write values (empty)
1897 pub mod RW {}
1898 }
1899
1900 /// IO port D clock enable
1901 pub mod GPIODEN {
1902 /// Offset (3 bits)
1903 pub const offset: u32 = 3;
1904 /// Mask (1 bit: 1 << 3)
1905 pub const mask: u32 = 1 << offset;
1906 /// Read-only values (empty)
1907 pub mod R {}
1908 /// Write-only values (empty)
1909 pub mod W {}
1910 /// Read-write values (empty)
1911 pub mod RW {}
1912 }
1913
1914 /// IO port C clock enable
1915 pub mod GPIOCEN {
1916 /// Offset (2 bits)
1917 pub const offset: u32 = 2;
1918 /// Mask (1 bit: 1 << 2)
1919 pub const mask: u32 = 1 << offset;
1920 /// Read-only values (empty)
1921 pub mod R {}
1922 /// Write-only values (empty)
1923 pub mod W {}
1924 /// Read-write values (empty)
1925 pub mod RW {}
1926 }
1927
1928 /// IO port B clock enable
1929 pub mod GPIOBEN {
1930 /// Offset (1 bits)
1931 pub const offset: u32 = 1;
1932 /// Mask (1 bit: 1 << 1)
1933 pub const mask: u32 = 1 << offset;
1934 /// Read-only values (empty)
1935 pub mod R {}
1936 /// Write-only values (empty)
1937 pub mod W {}
1938 /// Read-write values (empty)
1939 pub mod RW {}
1940 }
1941
1942 /// IO port A clock enable
1943 pub mod GPIOAEN {
1944 /// Offset (0 bits)
1945 pub const offset: u32 = 0;
1946 /// Mask (1 bit: 1 << 0)
1947 pub const mask: u32 = 1 << offset;
1948 /// Read-only values (empty)
1949 pub mod R {}
1950 /// Write-only values (empty)
1951 pub mod W {}
1952 /// Read-write values (empty)
1953 pub mod RW {}
1954 }
1955}
1956
1957/// AHB3 peripheral clock enable register
1958pub mod AHB3ENR {
1959
1960 /// FLASHEN
1961 pub mod FLASHEN {
1962 /// Offset (25 bits)
1963 pub const offset: u32 = 25;
1964 /// Mask (1 bit: 1 << 25)
1965 pub const mask: u32 = 1 << offset;
1966 /// Read-only values (empty)
1967 pub mod R {}
1968 /// Write-only values (empty)
1969 pub mod W {}
1970 /// Read-write values (empty)
1971 pub mod RW {}
1972 }
1973
1974 /// IPCCEN
1975 pub mod IPCCEN {
1976 /// Offset (20 bits)
1977 pub const offset: u32 = 20;
1978 /// Mask (1 bit: 1 << 20)
1979 pub const mask: u32 = 1 << offset;
1980 /// Read-only values (empty)
1981 pub mod R {}
1982 /// Write-only values (empty)
1983 pub mod W {}
1984 /// Read-write values (empty)
1985 pub mod RW {}
1986 }
1987
1988 /// HSEMEN
1989 pub mod HSEMEN {
1990 /// Offset (19 bits)
1991 pub const offset: u32 = 19;
1992 /// Mask (1 bit: 1 << 19)
1993 pub const mask: u32 = 1 << offset;
1994 /// Read-only values (empty)
1995 pub mod R {}
1996 /// Write-only values (empty)
1997 pub mod W {}
1998 /// Read-write values (empty)
1999 pub mod RW {}
2000 }
2001
2002 /// RNGEN
2003 pub mod RNGEN {
2004 /// Offset (18 bits)
2005 pub const offset: u32 = 18;
2006 /// Mask (1 bit: 1 << 18)
2007 pub const mask: u32 = 1 << offset;
2008 /// Read-only values (empty)
2009 pub mod R {}
2010 /// Write-only values (empty)
2011 pub mod W {}
2012 /// Read-write values (empty)
2013 pub mod RW {}
2014 }
2015
2016 /// AES2EN
2017 pub mod AES2EN {
2018 /// Offset (17 bits)
2019 pub const offset: u32 = 17;
2020 /// Mask (1 bit: 1 << 17)
2021 pub const mask: u32 = 1 << offset;
2022 /// Read-only values (empty)
2023 pub mod R {}
2024 /// Write-only values (empty)
2025 pub mod W {}
2026 /// Read-write values (empty)
2027 pub mod RW {}
2028 }
2029
2030 /// PKAEN
2031 pub mod PKAEN {
2032 /// Offset (16 bits)
2033 pub const offset: u32 = 16;
2034 /// Mask (1 bit: 1 << 16)
2035 pub const mask: u32 = 1 << offset;
2036 /// Read-only values (empty)
2037 pub mod R {}
2038 /// Write-only values (empty)
2039 pub mod W {}
2040 /// Read-write values (empty)
2041 pub mod RW {}
2042 }
2043
2044 /// QSPIEN
2045 pub mod QSPIEN {
2046 /// Offset (8 bits)
2047 pub const offset: u32 = 8;
2048 /// Mask (1 bit: 1 << 8)
2049 pub const mask: u32 = 1 << offset;
2050 /// Read-only values (empty)
2051 pub mod R {}
2052 /// Write-only values (empty)
2053 pub mod W {}
2054 /// Read-write values (empty)
2055 pub mod RW {}
2056 }
2057}
2058
2059/// APB1ENR1
2060pub mod APB1ENR1 {
2061
2062 /// CPU1 Low power timer 1 clock enable
2063 pub mod LPTIM1EN {
2064 /// Offset (31 bits)
2065 pub const offset: u32 = 31;
2066 /// Mask (1 bit: 1 << 31)
2067 pub const mask: u32 = 1 << offset;
2068 /// Read-only values (empty)
2069 pub mod R {}
2070 /// Write-only values (empty)
2071 pub mod W {}
2072 /// Read-write values (empty)
2073 pub mod RW {}
2074 }
2075
2076 /// CPU1 USB clock enable
2077 pub mod USBEN {
2078 /// Offset (26 bits)
2079 pub const offset: u32 = 26;
2080 /// Mask (1 bit: 1 << 26)
2081 pub const mask: u32 = 1 << offset;
2082 /// Read-only values (empty)
2083 pub mod R {}
2084 /// Write-only values (empty)
2085 pub mod W {}
2086 /// Read-write values (empty)
2087 pub mod RW {}
2088 }
2089
2090 /// CPU1 CRS clock enable
2091 pub mod CRSEN {
2092 /// Offset (24 bits)
2093 pub const offset: u32 = 24;
2094 /// Mask (1 bit: 1 << 24)
2095 pub const mask: u32 = 1 << offset;
2096 /// Read-only values (empty)
2097 pub mod R {}
2098 /// Write-only values (empty)
2099 pub mod W {}
2100 /// Read-write values (empty)
2101 pub mod RW {}
2102 }
2103
2104 /// CPU1 I2C3 clock enable
2105 pub mod I2C3EN {
2106 /// Offset (23 bits)
2107 pub const offset: u32 = 23;
2108 /// Mask (1 bit: 1 << 23)
2109 pub const mask: u32 = 1 << offset;
2110 /// Read-only values (empty)
2111 pub mod R {}
2112 /// Write-only values (empty)
2113 pub mod W {}
2114 /// Read-write values (empty)
2115 pub mod RW {}
2116 }
2117
2118 /// CPU1 I2C1 clock enable
2119 pub mod I2C1EN {
2120 /// Offset (21 bits)
2121 pub const offset: u32 = 21;
2122 /// Mask (1 bit: 1 << 21)
2123 pub const mask: u32 = 1 << offset;
2124 /// Read-only values (empty)
2125 pub mod R {}
2126 /// Write-only values (empty)
2127 pub mod W {}
2128 /// Read-write values (empty)
2129 pub mod RW {}
2130 }
2131
2132 /// CPU1 SPI2 clock enable
2133 pub mod SPI2EN {
2134 /// Offset (14 bits)
2135 pub const offset: u32 = 14;
2136 /// Mask (1 bit: 1 << 14)
2137 pub const mask: u32 = 1 << offset;
2138 /// Read-only values (empty)
2139 pub mod R {}
2140 /// Write-only values (empty)
2141 pub mod W {}
2142 /// Read-write values (empty)
2143 pub mod RW {}
2144 }
2145
2146 /// CPU1 Window watchdog clock enable
2147 pub mod WWDGEN {
2148 /// Offset (11 bits)
2149 pub const offset: u32 = 11;
2150 /// Mask (1 bit: 1 << 11)
2151 pub const mask: u32 = 1 << offset;
2152 /// Read-only values (empty)
2153 pub mod R {}
2154 /// Write-only values (empty)
2155 pub mod W {}
2156 /// Read-write values (empty)
2157 pub mod RW {}
2158 }
2159
2160 /// CPU1 RTC APB clock enable
2161 pub mod RTCAPBEN {
2162 /// Offset (10 bits)
2163 pub const offset: u32 = 10;
2164 /// Mask (1 bit: 1 << 10)
2165 pub const mask: u32 = 1 << offset;
2166 /// Read-only values (empty)
2167 pub mod R {}
2168 /// Write-only values (empty)
2169 pub mod W {}
2170 /// Read-write values (empty)
2171 pub mod RW {}
2172 }
2173
2174 /// CPU1 LCD clock enable
2175 pub mod LCDEN {
2176 /// Offset (9 bits)
2177 pub const offset: u32 = 9;
2178 /// Mask (1 bit: 1 << 9)
2179 pub const mask: u32 = 1 << offset;
2180 /// Read-only values (empty)
2181 pub mod R {}
2182 /// Write-only values (empty)
2183 pub mod W {}
2184 /// Read-write values (empty)
2185 pub mod RW {}
2186 }
2187
2188 /// CPU1 TIM2 timer clock enable
2189 pub mod TIM2EN {
2190 /// Offset (0 bits)
2191 pub const offset: u32 = 0;
2192 /// Mask (1 bit: 1 << 0)
2193 pub const mask: u32 = 1 << offset;
2194 /// Read-only values (empty)
2195 pub mod R {}
2196 /// Write-only values (empty)
2197 pub mod W {}
2198 /// Read-write values (empty)
2199 pub mod RW {}
2200 }
2201}
2202
2203/// APB1 peripheral clock enable register 2
2204pub mod APB1ENR2 {
2205
2206 /// CPU1 LPTIM2EN
2207 pub mod LPTIM2EN {
2208 /// Offset (5 bits)
2209 pub const offset: u32 = 5;
2210 /// Mask (1 bit: 1 << 5)
2211 pub const mask: u32 = 1 << offset;
2212 /// Read-only values (empty)
2213 pub mod R {}
2214 /// Write-only values (empty)
2215 pub mod W {}
2216 /// Read-write values (empty)
2217 pub mod RW {}
2218 }
2219
2220 /// CPU1 Low power UART 1 clock enable
2221 pub mod LPUART1EN {
2222 /// Offset (0 bits)
2223 pub const offset: u32 = 0;
2224 /// Mask (1 bit: 1 << 0)
2225 pub const mask: u32 = 1 << offset;
2226 /// Read-only values (empty)
2227 pub mod R {}
2228 /// Write-only values (empty)
2229 pub mod W {}
2230 /// Read-write values (empty)
2231 pub mod RW {}
2232 }
2233}
2234
2235/// APB2ENR
2236pub mod APB2ENR {
2237
2238 /// CPU1 SAI1 clock enable
2239 pub mod SAI1EN {
2240 /// Offset (21 bits)
2241 pub const offset: u32 = 21;
2242 /// Mask (1 bit: 1 << 21)
2243 pub const mask: u32 = 1 << offset;
2244 /// Read-only values (empty)
2245 pub mod R {}
2246 /// Write-only values (empty)
2247 pub mod W {}
2248 /// Read-write values (empty)
2249 pub mod RW {}
2250 }
2251
2252 /// CPU1 TIM17 timer clock enable
2253 pub mod TIM17EN {
2254 /// Offset (18 bits)
2255 pub const offset: u32 = 18;
2256 /// Mask (1 bit: 1 << 18)
2257 pub const mask: u32 = 1 << offset;
2258 /// Read-only values (empty)
2259 pub mod R {}
2260 /// Write-only values (empty)
2261 pub mod W {}
2262 /// Read-write values (empty)
2263 pub mod RW {}
2264 }
2265
2266 /// CPU1 TIM16 timer clock enable
2267 pub mod TIM16EN {
2268 /// Offset (17 bits)
2269 pub const offset: u32 = 17;
2270 /// Mask (1 bit: 1 << 17)
2271 pub const mask: u32 = 1 << offset;
2272 /// Read-only values (empty)
2273 pub mod R {}
2274 /// Write-only values (empty)
2275 pub mod W {}
2276 /// Read-write values (empty)
2277 pub mod RW {}
2278 }
2279
2280 /// CPU1 USART1clock enable
2281 pub mod USART1EN {
2282 /// Offset (14 bits)
2283 pub const offset: u32 = 14;
2284 /// Mask (1 bit: 1 << 14)
2285 pub const mask: u32 = 1 << offset;
2286 /// Read-only values (empty)
2287 pub mod R {}
2288 /// Write-only values (empty)
2289 pub mod W {}
2290 /// Read-write values (empty)
2291 pub mod RW {}
2292 }
2293
2294 /// CPU1 SPI1 clock enable
2295 pub mod SPI1EN {
2296 /// Offset (12 bits)
2297 pub const offset: u32 = 12;
2298 /// Mask (1 bit: 1 << 12)
2299 pub const mask: u32 = 1 << offset;
2300 /// Read-only values (empty)
2301 pub mod R {}
2302 /// Write-only values (empty)
2303 pub mod W {}
2304 /// Read-write values (empty)
2305 pub mod RW {}
2306 }
2307
2308 /// CPU1 TIM1 timer clock enable
2309 pub mod TIM1EN {
2310 /// Offset (11 bits)
2311 pub const offset: u32 = 11;
2312 /// Mask (1 bit: 1 << 11)
2313 pub const mask: u32 = 1 << offset;
2314 /// Read-only values (empty)
2315 pub mod R {}
2316 /// Write-only values (empty)
2317 pub mod W {}
2318 /// Read-write values (empty)
2319 pub mod RW {}
2320 }
2321}
2322
2323/// AHB1 peripheral clocks enable in Sleep and Stop modes register
2324pub mod AHB1SMENR {
2325
2326 /// CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes
2327 pub mod TSCSMEN {
2328 /// Offset (16 bits)
2329 pub const offset: u32 = 16;
2330 /// Mask (1 bit: 1 << 16)
2331 pub const mask: u32 = 1 << offset;
2332 /// Read-only values (empty)
2333 pub mod R {}
2334 /// Write-only values (empty)
2335 pub mod W {}
2336 /// Read-write values (empty)
2337 pub mod RW {}
2338 }
2339
2340 /// CPU1 CRCSMEN
2341 pub mod CRCSMEN {
2342 /// Offset (12 bits)
2343 pub const offset: u32 = 12;
2344 /// Mask (1 bit: 1 << 12)
2345 pub const mask: u32 = 1 << offset;
2346 /// Read-only values (empty)
2347 pub mod R {}
2348 /// Write-only values (empty)
2349 pub mod W {}
2350 /// Read-write values (empty)
2351 pub mod RW {}
2352 }
2353
2354 /// CPU1 SRAM1 interface clocks enable during Sleep and Stop modes
2355 pub mod SRAM1SMEN {
2356 /// Offset (9 bits)
2357 pub const offset: u32 = 9;
2358 /// Mask (1 bit: 1 << 9)
2359 pub const mask: u32 = 1 << offset;
2360 /// Read-only values (empty)
2361 pub mod R {}
2362 /// Write-only values (empty)
2363 pub mod W {}
2364 /// Read-write values (empty)
2365 pub mod RW {}
2366 }
2367
2368 /// CPU1 DMAMUX clocks enable during Sleep and Stop modes
2369 pub mod DMAMUXSMEN {
2370 /// Offset (2 bits)
2371 pub const offset: u32 = 2;
2372 /// Mask (1 bit: 1 << 2)
2373 pub const mask: u32 = 1 << offset;
2374 /// Read-only values (empty)
2375 pub mod R {}
2376 /// Write-only values (empty)
2377 pub mod W {}
2378 /// Read-write values (empty)
2379 pub mod RW {}
2380 }
2381
2382 /// CPU1 DMA2 clocks enable during Sleep and Stop modes
2383 pub mod DMA2SMEN {
2384 /// Offset (1 bits)
2385 pub const offset: u32 = 1;
2386 /// Mask (1 bit: 1 << 1)
2387 pub const mask: u32 = 1 << offset;
2388 /// Read-only values (empty)
2389 pub mod R {}
2390 /// Write-only values (empty)
2391 pub mod W {}
2392 /// Read-write values (empty)
2393 pub mod RW {}
2394 }
2395
2396 /// CPU1 DMA1 clocks enable during Sleep and Stop modes
2397 pub mod DMA1SMEN {
2398 /// Offset (0 bits)
2399 pub const offset: u32 = 0;
2400 /// Mask (1 bit: 1 << 0)
2401 pub const mask: u32 = 1 << offset;
2402 /// Read-only values (empty)
2403 pub mod R {}
2404 /// Write-only values (empty)
2405 pub mod W {}
2406 /// Read-write values (empty)
2407 pub mod RW {}
2408 }
2409}
2410
2411/// AHB2 peripheral clocks enable in Sleep and Stop modes register
2412pub mod AHB2SMENR {
2413
2414 /// CPU1 AES1 accelerator clocks enable during Sleep and Stop modes
2415 pub mod AES1SMEN {
2416 /// Offset (16 bits)
2417 pub const offset: u32 = 16;
2418 /// Mask (1 bit: 1 << 16)
2419 pub const mask: u32 = 1 << offset;
2420 /// Read-only values (empty)
2421 pub mod R {}
2422 /// Write-only values (empty)
2423 pub mod W {}
2424 /// Read-write values (empty)
2425 pub mod RW {}
2426 }
2427
2428 /// CPU1 ADC clocks enable during Sleep and Stop modes
2429 pub mod ADCFSSMEN {
2430 /// Offset (13 bits)
2431 pub const offset: u32 = 13;
2432 /// Mask (1 bit: 1 << 13)
2433 pub const mask: u32 = 1 << offset;
2434 /// Read-only values (empty)
2435 pub mod R {}
2436 /// Write-only values (empty)
2437 pub mod W {}
2438 /// Read-write values (empty)
2439 pub mod RW {}
2440 }
2441
2442 /// CPU1 IO port H clocks enable during Sleep and Stop modes
2443 pub mod GPIOHSMEN {
2444 /// Offset (7 bits)
2445 pub const offset: u32 = 7;
2446 /// Mask (1 bit: 1 << 7)
2447 pub const mask: u32 = 1 << offset;
2448 /// Read-only values (empty)
2449 pub mod R {}
2450 /// Write-only values (empty)
2451 pub mod W {}
2452 /// Read-write values (empty)
2453 pub mod RW {}
2454 }
2455
2456 /// CPU1 IO port E clocks enable during Sleep and Stop modes
2457 pub mod GPIOESMEN {
2458 /// Offset (4 bits)
2459 pub const offset: u32 = 4;
2460 /// Mask (1 bit: 1 << 4)
2461 pub const mask: u32 = 1 << offset;
2462 /// Read-only values (empty)
2463 pub mod R {}
2464 /// Write-only values (empty)
2465 pub mod W {}
2466 /// Read-write values (empty)
2467 pub mod RW {}
2468 }
2469
2470 /// CPU1 IO port D clocks enable during Sleep and Stop modes
2471 pub mod GPIODSMEN {
2472 /// Offset (3 bits)
2473 pub const offset: u32 = 3;
2474 /// Mask (1 bit: 1 << 3)
2475 pub const mask: u32 = 1 << offset;
2476 /// Read-only values (empty)
2477 pub mod R {}
2478 /// Write-only values (empty)
2479 pub mod W {}
2480 /// Read-write values (empty)
2481 pub mod RW {}
2482 }
2483
2484 /// CPU1 IO port C clocks enable during Sleep and Stop modes
2485 pub mod GPIOCSMEN {
2486 /// Offset (2 bits)
2487 pub const offset: u32 = 2;
2488 /// Mask (1 bit: 1 << 2)
2489 pub const mask: u32 = 1 << offset;
2490 /// Read-only values (empty)
2491 pub mod R {}
2492 /// Write-only values (empty)
2493 pub mod W {}
2494 /// Read-write values (empty)
2495 pub mod RW {}
2496 }
2497
2498 /// CPU1 IO port B clocks enable during Sleep and Stop modes
2499 pub mod GPIOBSMEN {
2500 /// Offset (1 bits)
2501 pub const offset: u32 = 1;
2502 /// Mask (1 bit: 1 << 1)
2503 pub const mask: u32 = 1 << offset;
2504 /// Read-only values (empty)
2505 pub mod R {}
2506 /// Write-only values (empty)
2507 pub mod W {}
2508 /// Read-write values (empty)
2509 pub mod RW {}
2510 }
2511
2512 /// CPU1 IO port A clocks enable during Sleep and Stop modes
2513 pub mod GPIOASMEN {
2514 /// Offset (0 bits)
2515 pub const offset: u32 = 0;
2516 /// Mask (1 bit: 1 << 0)
2517 pub const mask: u32 = 1 << offset;
2518 /// Read-only values (empty)
2519 pub mod R {}
2520 /// Write-only values (empty)
2521 pub mod W {}
2522 /// Read-write values (empty)
2523 pub mod RW {}
2524 }
2525}
2526
2527/// AHB3 peripheral clocks enable in Sleep and Stop modes register
2528pub mod AHB3SMENR {
2529
2530 /// Flash interface clocks enable during CPU1 sleep mode
2531 pub mod FLASHSMEN {
2532 /// Offset (25 bits)
2533 pub const offset: u32 = 25;
2534 /// Mask (1 bit: 1 << 25)
2535 pub const mask: u32 = 1 << offset;
2536 /// Read-only values (empty)
2537 pub mod R {}
2538 /// Write-only values (empty)
2539 pub mod W {}
2540 /// Read-write values (empty)
2541 pub mod RW {}
2542 }
2543
2544 /// SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode
2545 pub mod SRAM2SMEN {
2546 /// Offset (24 bits)
2547 pub const offset: u32 = 24;
2548 /// Mask (1 bit: 1 << 24)
2549 pub const mask: u32 = 1 << offset;
2550 /// Read-only values (empty)
2551 pub mod R {}
2552 /// Write-only values (empty)
2553 pub mod W {}
2554 /// Read-write values (empty)
2555 pub mod RW {}
2556 }
2557
2558 /// True RNG clocks enable during CPU1 sleep mode
2559 pub mod RNGSMEN {
2560 /// Offset (18 bits)
2561 pub const offset: u32 = 18;
2562 /// Mask (1 bit: 1 << 18)
2563 pub const mask: u32 = 1 << offset;
2564 /// Read-only values (empty)
2565 pub mod R {}
2566 /// Write-only values (empty)
2567 pub mod W {}
2568 /// Read-write values (empty)
2569 pub mod RW {}
2570 }
2571
2572 /// AES2 accelerator clocks enable during CPU1 sleep mode
2573 pub mod AES2SMEN {
2574 /// Offset (17 bits)
2575 pub const offset: u32 = 17;
2576 /// Mask (1 bit: 1 << 17)
2577 pub const mask: u32 = 1 << offset;
2578 /// Read-only values (empty)
2579 pub mod R {}
2580 /// Write-only values (empty)
2581 pub mod W {}
2582 /// Read-write values (empty)
2583 pub mod RW {}
2584 }
2585
2586 /// PKA accelerator clocks enable during CPU1 sleep mode
2587 pub mod PKASMEN {
2588 /// Offset (16 bits)
2589 pub const offset: u32 = 16;
2590 /// Mask (1 bit: 1 << 16)
2591 pub const mask: u32 = 1 << offset;
2592 /// Read-only values (empty)
2593 pub mod R {}
2594 /// Write-only values (empty)
2595 pub mod W {}
2596 /// Read-write values (empty)
2597 pub mod RW {}
2598 }
2599
2600 /// QSPISMEN
2601 pub mod QSPISMEN {
2602 /// Offset (8 bits)
2603 pub const offset: u32 = 8;
2604 /// Mask (1 bit: 1 << 8)
2605 pub const mask: u32 = 1 << offset;
2606 /// Read-only values (empty)
2607 pub mod R {}
2608 /// Write-only values (empty)
2609 pub mod W {}
2610 /// Read-write values (empty)
2611 pub mod RW {}
2612 }
2613}
2614
2615/// APB1SMENR1
2616pub mod APB1SMENR1 {
2617
2618 /// Low power timer 1 clocks enable during CPU1 Sleep mode
2619 pub mod LPTIM1SMEN {
2620 /// Offset (31 bits)
2621 pub const offset: u32 = 31;
2622 /// Mask (1 bit: 1 << 31)
2623 pub const mask: u32 = 1 << offset;
2624 /// Read-only values (empty)
2625 pub mod R {}
2626 /// Write-only values (empty)
2627 pub mod W {}
2628 /// Read-write values (empty)
2629 pub mod RW {}
2630 }
2631
2632 /// USB FS clocks enable during CPU1 Sleep mode
2633 pub mod USBSMEN {
2634 /// Offset (26 bits)
2635 pub const offset: u32 = 26;
2636 /// Mask (1 bit: 1 << 26)
2637 pub const mask: u32 = 1 << offset;
2638 /// Read-only values (empty)
2639 pub mod R {}
2640 /// Write-only values (empty)
2641 pub mod W {}
2642 /// Read-write values (empty)
2643 pub mod RW {}
2644 }
2645
2646 /// CRS clocks enable during CPU1 Sleep mode
2647 pub mod CRSMEN {
2648 /// Offset (24 bits)
2649 pub const offset: u32 = 24;
2650 /// Mask (1 bit: 1 << 24)
2651 pub const mask: u32 = 1 << offset;
2652 /// Read-only values (empty)
2653 pub mod R {}
2654 /// Write-only values (empty)
2655 pub mod W {}
2656 /// Read-write values (empty)
2657 pub mod RW {}
2658 }
2659
2660 /// I2C3 clocks enable during CPU1 Sleep mode
2661 pub mod I2C3SMEN {
2662 /// Offset (23 bits)
2663 pub const offset: u32 = 23;
2664 /// Mask (1 bit: 1 << 23)
2665 pub const mask: u32 = 1 << offset;
2666 /// Read-only values (empty)
2667 pub mod R {}
2668 /// Write-only values (empty)
2669 pub mod W {}
2670 /// Read-write values (empty)
2671 pub mod RW {}
2672 }
2673
2674 /// I2C1 clocks enable during CPU1 Sleep mode
2675 pub mod I2C1SMEN {
2676 /// Offset (21 bits)
2677 pub const offset: u32 = 21;
2678 /// Mask (1 bit: 1 << 21)
2679 pub const mask: u32 = 1 << offset;
2680 /// Read-only values (empty)
2681 pub mod R {}
2682 /// Write-only values (empty)
2683 pub mod W {}
2684 /// Read-write values (empty)
2685 pub mod RW {}
2686 }
2687
2688 /// SPI2 clocks enable during CPU1 Sleep mode
2689 pub mod SPI2SMEN {
2690 /// Offset (14 bits)
2691 pub const offset: u32 = 14;
2692 /// Mask (1 bit: 1 << 14)
2693 pub const mask: u32 = 1 << offset;
2694 /// Read-only values (empty)
2695 pub mod R {}
2696 /// Write-only values (empty)
2697 pub mod W {}
2698 /// Read-write values (empty)
2699 pub mod RW {}
2700 }
2701
2702 /// Window watchdog clocks enable during CPU1 Sleep mode
2703 pub mod WWDGSMEN {
2704 /// Offset (11 bits)
2705 pub const offset: u32 = 11;
2706 /// Mask (1 bit: 1 << 11)
2707 pub const mask: u32 = 1 << offset;
2708 /// Read-only values (empty)
2709 pub mod R {}
2710 /// Write-only values (empty)
2711 pub mod W {}
2712 /// Read-write values (empty)
2713 pub mod RW {}
2714 }
2715
2716 /// RTC APB clocks enable during CPU1 Sleep mode
2717 pub mod RTCAPBSMEN {
2718 /// Offset (10 bits)
2719 pub const offset: u32 = 10;
2720 /// Mask (1 bit: 1 << 10)
2721 pub const mask: u32 = 1 << offset;
2722 /// Read-only values (empty)
2723 pub mod R {}
2724 /// Write-only values (empty)
2725 pub mod W {}
2726 /// Read-write values (empty)
2727 pub mod RW {}
2728 }
2729
2730 /// LCD clocks enable during CPU1 Sleep mode
2731 pub mod LCDSMEN {
2732 /// Offset (9 bits)
2733 pub const offset: u32 = 9;
2734 /// Mask (1 bit: 1 << 9)
2735 pub const mask: u32 = 1 << offset;
2736 /// Read-only values (empty)
2737 pub mod R {}
2738 /// Write-only values (empty)
2739 pub mod W {}
2740 /// Read-write values (empty)
2741 pub mod RW {}
2742 }
2743
2744 /// TIM2 timer clocks enable during CPU1 Sleep mode
2745 pub mod TIM2SMEN {
2746 /// Offset (0 bits)
2747 pub const offset: u32 = 0;
2748 /// Mask (1 bit: 1 << 0)
2749 pub const mask: u32 = 1 << offset;
2750 /// Read-only values (empty)
2751 pub mod R {}
2752 /// Write-only values (empty)
2753 pub mod W {}
2754 /// Read-write values (empty)
2755 pub mod RW {}
2756 }
2757}
2758
2759/// APB1 peripheral clocks enable in Sleep and Stop modes register 2
2760pub mod APB1SMENR2 {
2761
2762 /// Low power timer 2 clocks enable during CPU1 Sleep mode
2763 pub mod LPTIM2SMEN {
2764 /// Offset (5 bits)
2765 pub const offset: u32 = 5;
2766 /// Mask (1 bit: 1 << 5)
2767 pub const mask: u32 = 1 << offset;
2768 /// Read-only values (empty)
2769 pub mod R {}
2770 /// Write-only values (empty)
2771 pub mod W {}
2772 /// Read-write values (empty)
2773 pub mod RW {}
2774 }
2775
2776 /// Low power UART 1 clocks enable during CPU1 Sleep mode
2777 pub mod LPUART1SMEN {
2778 /// Offset (0 bits)
2779 pub const offset: u32 = 0;
2780 /// Mask (1 bit: 1 << 0)
2781 pub const mask: u32 = 1 << offset;
2782 /// Read-only values (empty)
2783 pub mod R {}
2784 /// Write-only values (empty)
2785 pub mod W {}
2786 /// Read-write values (empty)
2787 pub mod RW {}
2788 }
2789}
2790
2791/// APB2SMENR
2792pub mod APB2SMENR {
2793
2794 /// SAI1 clocks enable during CPU1 Sleep mode
2795 pub mod SAI1SMEN {
2796 /// Offset (21 bits)
2797 pub const offset: u32 = 21;
2798 /// Mask (1 bit: 1 << 21)
2799 pub const mask: u32 = 1 << offset;
2800 /// Read-only values (empty)
2801 pub mod R {}
2802 /// Write-only values (empty)
2803 pub mod W {}
2804 /// Read-write values (empty)
2805 pub mod RW {}
2806 }
2807
2808 /// TIM17 timer clocks enable during CPU1 Sleep mode
2809 pub mod TIM17SMEN {
2810 /// Offset (18 bits)
2811 pub const offset: u32 = 18;
2812 /// Mask (1 bit: 1 << 18)
2813 pub const mask: u32 = 1 << offset;
2814 /// Read-only values (empty)
2815 pub mod R {}
2816 /// Write-only values (empty)
2817 pub mod W {}
2818 /// Read-write values (empty)
2819 pub mod RW {}
2820 }
2821
2822 /// TIM16 timer clocks enable during CPU1 Sleep mode
2823 pub mod TIM16SMEN {
2824 /// Offset (17 bits)
2825 pub const offset: u32 = 17;
2826 /// Mask (1 bit: 1 << 17)
2827 pub const mask: u32 = 1 << offset;
2828 /// Read-only values (empty)
2829 pub mod R {}
2830 /// Write-only values (empty)
2831 pub mod W {}
2832 /// Read-write values (empty)
2833 pub mod RW {}
2834 }
2835
2836 /// USART1clocks enable during CPU1 Sleep mode
2837 pub mod USART1SMEN {
2838 /// Offset (14 bits)
2839 pub const offset: u32 = 14;
2840 /// Mask (1 bit: 1 << 14)
2841 pub const mask: u32 = 1 << offset;
2842 /// Read-only values (empty)
2843 pub mod R {}
2844 /// Write-only values (empty)
2845 pub mod W {}
2846 /// Read-write values (empty)
2847 pub mod RW {}
2848 }
2849
2850 /// SPI1 clocks enable during CPU1 Sleep mode
2851 pub mod SPI1SMEN {
2852 /// Offset (12 bits)
2853 pub const offset: u32 = 12;
2854 /// Mask (1 bit: 1 << 12)
2855 pub const mask: u32 = 1 << offset;
2856 /// Read-only values (empty)
2857 pub mod R {}
2858 /// Write-only values (empty)
2859 pub mod W {}
2860 /// Read-write values (empty)
2861 pub mod RW {}
2862 }
2863
2864 /// TIM1 timer clocks enable during CPU1 Sleep mode
2865 pub mod TIM1SMEN {
2866 /// Offset (11 bits)
2867 pub const offset: u32 = 11;
2868 /// Mask (1 bit: 1 << 11)
2869 pub const mask: u32 = 1 << offset;
2870 /// Read-only values (empty)
2871 pub mod R {}
2872 /// Write-only values (empty)
2873 pub mod W {}
2874 /// Read-write values (empty)
2875 pub mod RW {}
2876 }
2877}
2878
2879/// CCIPR
2880pub mod CCIPR {
2881
2882 /// RNG clock source selection
2883 pub mod RNGSEL {
2884 /// Offset (30 bits)
2885 pub const offset: u32 = 30;
2886 /// Mask (2 bits: 0b11 << 30)
2887 pub const mask: u32 = 0b11 << offset;
2888 /// Read-only values (empty)
2889 pub mod R {}
2890 /// Write-only values (empty)
2891 pub mod W {}
2892 /// Read-write values (empty)
2893 pub mod RW {}
2894 }
2895
2896 /// ADCs clock source selection
2897 pub mod ADCSEL {
2898 /// Offset (28 bits)
2899 pub const offset: u32 = 28;
2900 /// Mask (2 bits: 0b11 << 28)
2901 pub const mask: u32 = 0b11 << offset;
2902 /// Read-only values (empty)
2903 pub mod R {}
2904 /// Write-only values (empty)
2905 pub mod W {}
2906 /// Read-write values (empty)
2907 pub mod RW {}
2908 }
2909
2910 /// 48 MHz clock source selection
2911 pub mod CLK48SEL {
2912 /// Offset (26 bits)
2913 pub const offset: u32 = 26;
2914 /// Mask (2 bits: 0b11 << 26)
2915 pub const mask: u32 = 0b11 << offset;
2916 /// Read-only values (empty)
2917 pub mod R {}
2918 /// Write-only values (empty)
2919 pub mod W {}
2920 /// Read-write values (empty)
2921 pub mod RW {}
2922 }
2923
2924 /// SAI1 clock source selection
2925 pub mod SAI1SEL {
2926 /// Offset (22 bits)
2927 pub const offset: u32 = 22;
2928 /// Mask (2 bits: 0b11 << 22)
2929 pub const mask: u32 = 0b11 << offset;
2930 /// Read-only values (empty)
2931 pub mod R {}
2932 /// Write-only values (empty)
2933 pub mod W {}
2934 /// Read-write values (empty)
2935 pub mod RW {}
2936 }
2937
2938 /// Low power timer 2 clock source selection
2939 pub mod LPTIM2SEL {
2940 /// Offset (20 bits)
2941 pub const offset: u32 = 20;
2942 /// Mask (2 bits: 0b11 << 20)
2943 pub const mask: u32 = 0b11 << offset;
2944 /// Read-only values (empty)
2945 pub mod R {}
2946 /// Write-only values (empty)
2947 pub mod W {}
2948 /// Read-write values (empty)
2949 pub mod RW {}
2950 }
2951
2952 /// Low power timer 1 clock source selection
2953 pub mod LPTIM1SEL {
2954 /// Offset (18 bits)
2955 pub const offset: u32 = 18;
2956 /// Mask (2 bits: 0b11 << 18)
2957 pub const mask: u32 = 0b11 << offset;
2958 /// Read-only values (empty)
2959 pub mod R {}
2960 /// Write-only values (empty)
2961 pub mod W {}
2962 /// Read-write values (empty)
2963 pub mod RW {}
2964 }
2965
2966 /// I2C3 clock source selection
2967 pub mod I2C3SEL {
2968 /// Offset (16 bits)
2969 pub const offset: u32 = 16;
2970 /// Mask (2 bits: 0b11 << 16)
2971 pub const mask: u32 = 0b11 << offset;
2972 /// Read-only values (empty)
2973 pub mod R {}
2974 /// Write-only values (empty)
2975 pub mod W {}
2976 /// Read-write values (empty)
2977 pub mod RW {}
2978 }
2979
2980 /// I2C1 clock source selection
2981 pub mod I2C1SEL {
2982 /// Offset (12 bits)
2983 pub const offset: u32 = 12;
2984 /// Mask (2 bits: 0b11 << 12)
2985 pub const mask: u32 = 0b11 << offset;
2986 /// Read-only values (empty)
2987 pub mod R {}
2988 /// Write-only values (empty)
2989 pub mod W {}
2990 /// Read-write values (empty)
2991 pub mod RW {}
2992 }
2993
2994 /// LPUART1 clock source selection
2995 pub mod LPUART1SEL {
2996 /// Offset (10 bits)
2997 pub const offset: u32 = 10;
2998 /// Mask (2 bits: 0b11 << 10)
2999 pub const mask: u32 = 0b11 << offset;
3000 /// Read-only values (empty)
3001 pub mod R {}
3002 /// Write-only values (empty)
3003 pub mod W {}
3004 /// Read-write values (empty)
3005 pub mod RW {}
3006 }
3007
3008 /// USART1 clock source selection
3009 pub mod USART1SEL {
3010 /// Offset (0 bits)
3011 pub const offset: u32 = 0;
3012 /// Mask (2 bits: 0b11 << 0)
3013 pub const mask: u32 = 0b11 << offset;
3014 /// Read-only values (empty)
3015 pub mod R {}
3016 /// Write-only values (empty)
3017 pub mod W {}
3018 /// Read-write values (empty)
3019 pub mod RW {}
3020 }
3021}
3022
3023/// BDCR
3024pub mod BDCR {
3025
3026 /// Low speed clock output selection
3027 pub mod LSCOSEL {
3028 /// Offset (25 bits)
3029 pub const offset: u32 = 25;
3030 /// Mask (2 bits: 0b11 << 25)
3031 pub const mask: u32 = 0b11 << offset;
3032 /// Read-only values (empty)
3033 pub mod R {}
3034 /// Write-only values (empty)
3035 pub mod W {}
3036 /// Read-write values (empty)
3037 pub mod RW {}
3038 }
3039
3040 /// Low speed clock output enable
3041 pub mod LSCOEN {
3042 /// Offset (24 bits)
3043 pub const offset: u32 = 24;
3044 /// Mask (1 bit: 1 << 24)
3045 pub const mask: u32 = 1 << offset;
3046 /// Read-only values (empty)
3047 pub mod R {}
3048 /// Write-only values (empty)
3049 pub mod W {}
3050 /// Read-write values (empty)
3051 pub mod RW {}
3052 }
3053
3054 /// Backup domain software reset
3055 pub mod BDRST {
3056 /// Offset (16 bits)
3057 pub const offset: u32 = 16;
3058 /// Mask (1 bit: 1 << 16)
3059 pub const mask: u32 = 1 << offset;
3060 /// Read-only values (empty)
3061 pub mod R {}
3062 /// Write-only values (empty)
3063 pub mod W {}
3064 /// Read-write values (empty)
3065 pub mod RW {}
3066 }
3067
3068 /// RTC clock enable
3069 pub mod RTCEN {
3070 /// Offset (15 bits)
3071 pub const offset: u32 = 15;
3072 /// Mask (1 bit: 1 << 15)
3073 pub const mask: u32 = 1 << offset;
3074 /// Read-only values (empty)
3075 pub mod R {}
3076 /// Write-only values (empty)
3077 pub mod W {}
3078 /// Read-write values (empty)
3079 pub mod RW {}
3080 }
3081
3082 /// RTC clock source selection
3083 pub mod RTCSEL {
3084 /// Offset (8 bits)
3085 pub const offset: u32 = 8;
3086 /// Mask (2 bits: 0b11 << 8)
3087 pub const mask: u32 = 0b11 << offset;
3088 /// Read-only values (empty)
3089 pub mod R {}
3090 /// Write-only values (empty)
3091 pub mod W {}
3092 /// Read-write values (empty)
3093 pub mod RW {}
3094 }
3095
3096 /// CSS on LSE failure detection
3097 pub mod LSECSSD_ {
3098 /// Offset (6 bits)
3099 pub const offset: u32 = 6;
3100 /// Mask (1 bit: 1 << 6)
3101 pub const mask: u32 = 1 << offset;
3102 /// Read-only values (empty)
3103 pub mod R {}
3104 /// Write-only values (empty)
3105 pub mod W {}
3106 /// Read-write values (empty)
3107 pub mod RW {}
3108 }
3109
3110 /// LSECSSON
3111 pub mod LSECSSON {
3112 /// Offset (5 bits)
3113 pub const offset: u32 = 5;
3114 /// Mask (1 bit: 1 << 5)
3115 pub const mask: u32 = 1 << offset;
3116 /// Read-only values (empty)
3117 pub mod R {}
3118 /// Write-only values (empty)
3119 pub mod W {}
3120 /// Read-write values (empty)
3121 pub mod RW {}
3122 }
3123
3124 /// SE oscillator drive capability
3125 pub mod LSEDRV {
3126 /// Offset (3 bits)
3127 pub const offset: u32 = 3;
3128 /// Mask (2 bits: 0b11 << 3)
3129 pub const mask: u32 = 0b11 << offset;
3130 /// Read-only values (empty)
3131 pub mod R {}
3132 /// Write-only values (empty)
3133 pub mod W {}
3134 /// Read-write values (empty)
3135 pub mod RW {}
3136 }
3137
3138 /// LSE oscillator bypass
3139 pub mod LSEBYP {
3140 /// Offset (2 bits)
3141 pub const offset: u32 = 2;
3142 /// Mask (1 bit: 1 << 2)
3143 pub const mask: u32 = 1 << offset;
3144 /// Read-only values (empty)
3145 pub mod R {}
3146 /// Write-only values (empty)
3147 pub mod W {}
3148 /// Read-write values (empty)
3149 pub mod RW {}
3150 }
3151
3152 /// LSE oscillator ready
3153 pub mod LSERDY {
3154 /// Offset (1 bits)
3155 pub const offset: u32 = 1;
3156 /// Mask (1 bit: 1 << 1)
3157 pub const mask: u32 = 1 << offset;
3158 /// Read-only values (empty)
3159 pub mod R {}
3160 /// Write-only values (empty)
3161 pub mod W {}
3162 /// Read-write values (empty)
3163 pub mod RW {}
3164 }
3165
3166 /// LSE oscillator enable
3167 pub mod LSEON {
3168 /// Offset (0 bits)
3169 pub const offset: u32 = 0;
3170 /// Mask (1 bit: 1 << 0)
3171 pub const mask: u32 = 1 << offset;
3172 /// Read-only values (empty)
3173 pub mod R {}
3174 /// Write-only values (empty)
3175 pub mod W {}
3176 /// Read-write values (empty)
3177 pub mod RW {}
3178 }
3179}
3180
3181/// CSR
3182pub mod CSR {
3183
3184 /// Low-power reset flag
3185 pub mod LPWRRSTF {
3186 /// Offset (31 bits)
3187 pub const offset: u32 = 31;
3188 /// Mask (1 bit: 1 << 31)
3189 pub const mask: u32 = 1 << offset;
3190 /// Read-only values (empty)
3191 pub mod R {}
3192 /// Write-only values (empty)
3193 pub mod W {}
3194 /// Read-write values (empty)
3195 pub mod RW {}
3196 }
3197
3198 /// Window watchdog reset flag
3199 pub mod WWDGRSTF {
3200 /// Offset (30 bits)
3201 pub const offset: u32 = 30;
3202 /// Mask (1 bit: 1 << 30)
3203 pub const mask: u32 = 1 << offset;
3204 /// Read-only values (empty)
3205 pub mod R {}
3206 /// Write-only values (empty)
3207 pub mod W {}
3208 /// Read-write values (empty)
3209 pub mod RW {}
3210 }
3211
3212 /// Independent window watchdog reset flag
3213 pub mod IWDGRSTF {
3214 /// Offset (29 bits)
3215 pub const offset: u32 = 29;
3216 /// Mask (1 bit: 1 << 29)
3217 pub const mask: u32 = 1 << offset;
3218 /// Read-only values (empty)
3219 pub mod R {}
3220 /// Write-only values (empty)
3221 pub mod W {}
3222 /// Read-write values (empty)
3223 pub mod RW {}
3224 }
3225
3226 /// Software reset flag
3227 pub mod SFTRSTF {
3228 /// Offset (28 bits)
3229 pub const offset: u32 = 28;
3230 /// Mask (1 bit: 1 << 28)
3231 pub const mask: u32 = 1 << offset;
3232 /// Read-only values (empty)
3233 pub mod R {}
3234 /// Write-only values (empty)
3235 pub mod W {}
3236 /// Read-write values (empty)
3237 pub mod RW {}
3238 }
3239
3240 /// BOR flag
3241 pub mod BORRSTF {
3242 /// Offset (27 bits)
3243 pub const offset: u32 = 27;
3244 /// Mask (1 bit: 1 << 27)
3245 pub const mask: u32 = 1 << offset;
3246 /// Read-only values (empty)
3247 pub mod R {}
3248 /// Write-only values (empty)
3249 pub mod W {}
3250 /// Read-write values (empty)
3251 pub mod RW {}
3252 }
3253
3254 /// Pin reset flag
3255 pub mod PINRSTF {
3256 /// Offset (26 bits)
3257 pub const offset: u32 = 26;
3258 /// Mask (1 bit: 1 << 26)
3259 pub const mask: u32 = 1 << offset;
3260 /// Read-only values (empty)
3261 pub mod R {}
3262 /// Write-only values (empty)
3263 pub mod W {}
3264 /// Read-write values (empty)
3265 pub mod RW {}
3266 }
3267
3268 /// Option byte loader reset flag
3269 pub mod OBLRSTF {
3270 /// Offset (25 bits)
3271 pub const offset: u32 = 25;
3272 /// Mask (1 bit: 1 << 25)
3273 pub const mask: u32 = 1 << offset;
3274 /// Read-only values (empty)
3275 pub mod R {}
3276 /// Write-only values (empty)
3277 pub mod W {}
3278 /// Read-write values (empty)
3279 pub mod RW {}
3280 }
3281
3282 /// Remove reset flag
3283 pub mod RMVF {
3284 /// Offset (23 bits)
3285 pub const offset: u32 = 23;
3286 /// Mask (1 bit: 1 << 23)
3287 pub const mask: u32 = 1 << offset;
3288 /// Read-only values (empty)
3289 pub mod R {}
3290 /// Write-only values (empty)
3291 pub mod W {}
3292 /// Read-write values (empty)
3293 pub mod RW {}
3294 }
3295
3296 /// RF system wakeup clock source selection
3297 pub mod RFWKPSEL {
3298 /// Offset (14 bits)
3299 pub const offset: u32 = 14;
3300 /// Mask (2 bits: 0b11 << 14)
3301 pub const mask: u32 = 0b11 << offset;
3302 /// Read-only values (empty)
3303 pub mod R {}
3304 /// Write-only values (empty)
3305 pub mod W {}
3306 /// Read-write values (empty)
3307 pub mod RW {}
3308 }
3309
3310 /// LSI2 oscillator bias configuration
3311 pub mod LSI2BW {
3312 /// Offset (8 bits)
3313 pub const offset: u32 = 8;
3314 /// Mask (4 bits: 0b1111 << 8)
3315 pub const mask: u32 = 0b1111 << offset;
3316 /// Read-only values (empty)
3317 pub mod R {}
3318 /// Write-only values (empty)
3319 pub mod W {}
3320 /// Read-write values (empty)
3321 pub mod RW {}
3322 }
3323
3324 /// LSI2 oscillator trim OK
3325 pub mod LSI2TRIMOK {
3326 /// Offset (5 bits)
3327 pub const offset: u32 = 5;
3328 /// Mask (1 bit: 1 << 5)
3329 pub const mask: u32 = 1 << offset;
3330 /// Read-only values (empty)
3331 pub mod R {}
3332 /// Write-only values (empty)
3333 pub mod W {}
3334 /// Read-write values (empty)
3335 pub mod RW {}
3336 }
3337
3338 /// LSI2 oscillator trimming enable
3339 pub mod LSI2TRIMEN {
3340 /// Offset (4 bits)
3341 pub const offset: u32 = 4;
3342 /// Mask (1 bit: 1 << 4)
3343 pub const mask: u32 = 1 << offset;
3344 /// Read-only values (empty)
3345 pub mod R {}
3346 /// Write-only values (empty)
3347 pub mod W {}
3348 /// Read-write values (empty)
3349 pub mod RW {}
3350 }
3351
3352 /// LSI2 oscillator ready
3353 pub mod LSI2RDY {
3354 /// Offset (3 bits)
3355 pub const offset: u32 = 3;
3356 /// Mask (1 bit: 1 << 3)
3357 pub const mask: u32 = 1 << offset;
3358 /// Read-only values (empty)
3359 pub mod R {}
3360 /// Write-only values (empty)
3361 pub mod W {}
3362 /// Read-write values (empty)
3363 pub mod RW {}
3364 }
3365
3366 /// LSI2 oscillator enabled
3367 pub mod LSI2ON {
3368 /// Offset (2 bits)
3369 pub const offset: u32 = 2;
3370 /// Mask (1 bit: 1 << 2)
3371 pub const mask: u32 = 1 << offset;
3372 /// Read-only values (empty)
3373 pub mod R {}
3374 /// Write-only values (empty)
3375 pub mod W {}
3376 /// Read-write values (empty)
3377 pub mod RW {}
3378 }
3379
3380 /// LSI1 oscillator ready
3381 pub mod LSI1RDY {
3382 /// Offset (1 bits)
3383 pub const offset: u32 = 1;
3384 /// Mask (1 bit: 1 << 1)
3385 pub const mask: u32 = 1 << offset;
3386 /// Read-only values (empty)
3387 pub mod R {}
3388 /// Write-only values (empty)
3389 pub mod W {}
3390 /// Read-write values (empty)
3391 pub mod RW {}
3392 }
3393
3394 /// LSI1 oscillator enabled
3395 pub mod LSI1ON {
3396 /// Offset (0 bits)
3397 pub const offset: u32 = 0;
3398 /// Mask (1 bit: 1 << 0)
3399 pub const mask: u32 = 1 << offset;
3400 /// Read-only values (empty)
3401 pub mod R {}
3402 /// Write-only values (empty)
3403 pub mod W {}
3404 /// Read-write values (empty)
3405 pub mod RW {}
3406 }
3407
3408 /// Radio system BLE and 802.15.4 reset status
3409 pub mod RFRSTS {
3410 /// Offset (16 bits)
3411 pub const offset: u32 = 16;
3412 /// Mask (1 bit: 1 << 16)
3413 pub const mask: u32 = 1 << offset;
3414 /// Read-only values (empty)
3415 pub mod R {}
3416 /// Write-only values (empty)
3417 pub mod W {}
3418 /// Read-write values (empty)
3419 pub mod RW {}
3420 }
3421}
3422
3423/// Clock recovery RC register
3424pub mod CRRCR {
3425
3426 /// HSI48 clock calibration
3427 pub mod HSI48CAL {
3428 /// Offset (7 bits)
3429 pub const offset: u32 = 7;
3430 /// Mask (9 bits: 0x1ff << 7)
3431 pub const mask: u32 = 0x1ff << offset;
3432 /// Read-only values (empty)
3433 pub mod R {}
3434 /// Write-only values (empty)
3435 pub mod W {}
3436 /// Read-write values (empty)
3437 pub mod RW {}
3438 }
3439
3440 /// HSI48 clock ready
3441 pub mod HSI48RDY {
3442 /// Offset (1 bits)
3443 pub const offset: u32 = 1;
3444 /// Mask (1 bit: 1 << 1)
3445 pub const mask: u32 = 1 << offset;
3446 /// Read-only values (empty)
3447 pub mod R {}
3448 /// Write-only values (empty)
3449 pub mod W {}
3450 /// Read-write values (empty)
3451 pub mod RW {}
3452 }
3453
3454 /// HSI48 oscillator enabled
3455 pub mod HSI48ON {
3456 /// Offset (0 bits)
3457 pub const offset: u32 = 0;
3458 /// Mask (1 bit: 1 << 0)
3459 pub const mask: u32 = 1 << offset;
3460 /// Read-only values (empty)
3461 pub mod R {}
3462 /// Write-only values (empty)
3463 pub mod W {}
3464 /// Read-write values (empty)
3465 pub mod RW {}
3466 }
3467}
3468
3469/// Clock HSE register
3470pub mod HSECR {
3471
3472 /// HSE capacitor tuning
3473 pub mod HSETUNE {
3474 /// Offset (8 bits)
3475 pub const offset: u32 = 8;
3476 /// Mask (6 bits: 0x3f << 8)
3477 pub const mask: u32 = 0x3f << offset;
3478 /// Read-only values (empty)
3479 pub mod R {}
3480 /// Write-only values (empty)
3481 pub mod W {}
3482 /// Read-write values (empty)
3483 pub mod RW {}
3484 }
3485
3486 /// HSE current control
3487 pub mod HSEGMC {
3488 /// Offset (4 bits)
3489 pub const offset: u32 = 4;
3490 /// Mask (3 bits: 0b111 << 4)
3491 pub const mask: u32 = 0b111 << offset;
3492 /// Read-only values (empty)
3493 pub mod R {}
3494 /// Write-only values (empty)
3495 pub mod W {}
3496 /// Read-write values (empty)
3497 pub mod RW {}
3498 }
3499
3500 /// HSE Sense amplifier threshold
3501 pub mod HSES {
3502 /// Offset (3 bits)
3503 pub const offset: u32 = 3;
3504 /// Mask (1 bit: 1 << 3)
3505 pub const mask: u32 = 1 << offset;
3506 /// Read-only values (empty)
3507 pub mod R {}
3508 /// Write-only values (empty)
3509 pub mod W {}
3510 /// Read-write values (empty)
3511 pub mod RW {}
3512 }
3513
3514 /// Register lock system
3515 pub mod UNLOCKED {
3516 /// Offset (0 bits)
3517 pub const offset: u32 = 0;
3518 /// Mask (1 bit: 1 << 0)
3519 pub const mask: u32 = 1 << offset;
3520 /// Read-only values (empty)
3521 pub mod R {}
3522 /// Write-only values (empty)
3523 pub mod W {}
3524 /// Read-write values (empty)
3525 pub mod RW {}
3526 }
3527}
3528
3529/// Extended clock recovery register
3530pub mod EXTCFGR {
3531
3532 /// RF clock source selected
3533 pub mod RFCSS {
3534 /// Offset (20 bits)
3535 pub const offset: u32 = 20;
3536 /// Mask (1 bit: 1 << 20)
3537 pub const mask: u32 = 1 << offset;
3538 /// Read-only values (empty)
3539 pub mod R {}
3540 /// Write-only values (empty)
3541 pub mod W {}
3542 /// Read-write values (empty)
3543 pub mod RW {}
3544 }
3545
3546 /// CPU2 AHB prescaler flag
3547 pub mod C2HPREF {
3548 /// Offset (17 bits)
3549 pub const offset: u32 = 17;
3550 /// Mask (1 bit: 1 << 17)
3551 pub const mask: u32 = 1 << offset;
3552 /// Read-only values (empty)
3553 pub mod R {}
3554 /// Write-only values (empty)
3555 pub mod W {}
3556 /// Read-write values (empty)
3557 pub mod RW {}
3558 }
3559
3560 /// Shared AHB prescaler flag
3561 pub mod SHDHPREF {
3562 /// Offset (16 bits)
3563 pub const offset: u32 = 16;
3564 /// Mask (1 bit: 1 << 16)
3565 pub const mask: u32 = 1 << offset;
3566 /// Read-only values (empty)
3567 pub mod R {}
3568 /// Write-only values (empty)
3569 pub mod W {}
3570 /// Read-write values (empty)
3571 pub mod RW {}
3572 }
3573
3574 /// CPU2 AHB prescaler
3575 pub mod C2HPRE {
3576 /// Offset (4 bits)
3577 pub const offset: u32 = 4;
3578 /// Mask (4 bits: 0b1111 << 4)
3579 pub const mask: u32 = 0b1111 << offset;
3580 /// Read-only values (empty)
3581 pub mod R {}
3582 /// Write-only values (empty)
3583 pub mod W {}
3584 /// Read-write values (empty)
3585 pub mod RW {}
3586 }
3587
3588 /// Shared AHB prescaler
3589 pub mod SHDHPRE {
3590 /// Offset (0 bits)
3591 pub const offset: u32 = 0;
3592 /// Mask (4 bits: 0b1111 << 0)
3593 pub const mask: u32 = 0b1111 << offset;
3594 /// Read-only values (empty)
3595 pub mod R {}
3596 /// Write-only values (empty)
3597 pub mod W {}
3598 /// Read-write values (empty)
3599 pub mod RW {}
3600 }
3601}
3602
3603/// CPU2 AHB1 peripheral clock enable register
3604pub mod C2AHB1ENR {
3605
3606 /// CPU2 Touch Sensing Controller clock enable
3607 pub mod TSCEN {
3608 /// Offset (16 bits)
3609 pub const offset: u32 = 16;
3610 /// Mask (1 bit: 1 << 16)
3611 pub const mask: u32 = 1 << offset;
3612 /// Read-only values (empty)
3613 pub mod R {}
3614 /// Write-only values (empty)
3615 pub mod W {}
3616 /// Read-write values (empty)
3617 pub mod RW {}
3618 }
3619
3620 /// CPU2 CRC clock enable
3621 pub mod CRCEN {
3622 /// Offset (12 bits)
3623 pub const offset: u32 = 12;
3624 /// Mask (1 bit: 1 << 12)
3625 pub const mask: u32 = 1 << offset;
3626 /// Read-only values (empty)
3627 pub mod R {}
3628 /// Write-only values (empty)
3629 pub mod W {}
3630 /// Read-write values (empty)
3631 pub mod RW {}
3632 }
3633
3634 /// CPU2 SRAM1 clock enable
3635 pub mod SRAM1EN {
3636 /// Offset (9 bits)
3637 pub const offset: u32 = 9;
3638 /// Mask (1 bit: 1 << 9)
3639 pub const mask: u32 = 1 << offset;
3640 /// Read-only values (empty)
3641 pub mod R {}
3642 /// Write-only values (empty)
3643 pub mod W {}
3644 /// Read-write values (empty)
3645 pub mod RW {}
3646 }
3647
3648 /// CPU2 DMAMUX clock enable
3649 pub mod DMAMUXEN {
3650 /// Offset (2 bits)
3651 pub const offset: u32 = 2;
3652 /// Mask (1 bit: 1 << 2)
3653 pub const mask: u32 = 1 << offset;
3654 /// Read-only values (empty)
3655 pub mod R {}
3656 /// Write-only values (empty)
3657 pub mod W {}
3658 /// Read-write values (empty)
3659 pub mod RW {}
3660 }
3661
3662 /// CPU2 DMA2 clock enable
3663 pub mod DMA2EN {
3664 /// Offset (1 bits)
3665 pub const offset: u32 = 1;
3666 /// Mask (1 bit: 1 << 1)
3667 pub const mask: u32 = 1 << offset;
3668 /// Read-only values (empty)
3669 pub mod R {}
3670 /// Write-only values (empty)
3671 pub mod W {}
3672 /// Read-write values (empty)
3673 pub mod RW {}
3674 }
3675
3676 /// CPU2 DMA1 clock enable
3677 pub mod DMA1EN {
3678 /// Offset (0 bits)
3679 pub const offset: u32 = 0;
3680 /// Mask (1 bit: 1 << 0)
3681 pub const mask: u32 = 1 << offset;
3682 /// Read-only values (empty)
3683 pub mod R {}
3684 /// Write-only values (empty)
3685 pub mod W {}
3686 /// Read-write values (empty)
3687 pub mod RW {}
3688 }
3689}
3690
3691/// CPU2 AHB2 peripheral clock enable register
3692pub mod C2AHB2ENR {
3693 pub use super::AHB2ENR::ADCEN;
3694 pub use super::AHB2ENR::AES1EN;
3695 pub use super::AHB2ENR::GPIOAEN;
3696 pub use super::AHB2ENR::GPIOBEN;
3697 pub use super::AHB2ENR::GPIOCEN;
3698 pub use super::AHB2ENR::GPIODEN;
3699 pub use super::AHB2ENR::GPIOEEN;
3700 pub use super::AHB2ENR::GPIOHEN;
3701}
3702
3703/// CPU2 AHB3 peripheral clock enable register
3704pub mod C2AHB3ENR {
3705
3706 /// CPU2 FLASHEN
3707 pub mod FLASHEN {
3708 /// Offset (25 bits)
3709 pub const offset: u32 = 25;
3710 /// Mask (1 bit: 1 << 25)
3711 pub const mask: u32 = 1 << offset;
3712 /// Read-only values (empty)
3713 pub mod R {}
3714 /// Write-only values (empty)
3715 pub mod W {}
3716 /// Read-write values (empty)
3717 pub mod RW {}
3718 }
3719
3720 /// CPU2 IPCCEN
3721 pub mod IPCCEN {
3722 /// Offset (20 bits)
3723 pub const offset: u32 = 20;
3724 /// Mask (1 bit: 1 << 20)
3725 pub const mask: u32 = 1 << offset;
3726 /// Read-only values (empty)
3727 pub mod R {}
3728 /// Write-only values (empty)
3729 pub mod W {}
3730 /// Read-write values (empty)
3731 pub mod RW {}
3732 }
3733
3734 /// CPU2 HSEMEN
3735 pub mod HSEMEN {
3736 /// Offset (19 bits)
3737 pub const offset: u32 = 19;
3738 /// Mask (1 bit: 1 << 19)
3739 pub const mask: u32 = 1 << offset;
3740 /// Read-only values (empty)
3741 pub mod R {}
3742 /// Write-only values (empty)
3743 pub mod W {}
3744 /// Read-write values (empty)
3745 pub mod RW {}
3746 }
3747
3748 /// CPU2 RNGEN
3749 pub mod RNGEN {
3750 /// Offset (18 bits)
3751 pub const offset: u32 = 18;
3752 /// Mask (1 bit: 1 << 18)
3753 pub const mask: u32 = 1 << offset;
3754 /// Read-only values (empty)
3755 pub mod R {}
3756 /// Write-only values (empty)
3757 pub mod W {}
3758 /// Read-write values (empty)
3759 pub mod RW {}
3760 }
3761
3762 /// CPU2 AES2EN
3763 pub mod AES2EN {
3764 /// Offset (17 bits)
3765 pub const offset: u32 = 17;
3766 /// Mask (1 bit: 1 << 17)
3767 pub const mask: u32 = 1 << offset;
3768 /// Read-only values (empty)
3769 pub mod R {}
3770 /// Write-only values (empty)
3771 pub mod W {}
3772 /// Read-write values (empty)
3773 pub mod RW {}
3774 }
3775
3776 /// CPU2 PKAEN
3777 pub mod PKAEN {
3778 /// Offset (16 bits)
3779 pub const offset: u32 = 16;
3780 /// Mask (1 bit: 1 << 16)
3781 pub const mask: u32 = 1 << offset;
3782 /// Read-only values (empty)
3783 pub mod R {}
3784 /// Write-only values (empty)
3785 pub mod W {}
3786 /// Read-write values (empty)
3787 pub mod RW {}
3788 }
3789}
3790
3791/// CPU2 APB1ENR1
3792pub mod C2APB1ENR1 {
3793
3794 /// CPU2 Low power timer 1 clock enable
3795 pub mod LPTIM1EN {
3796 /// Offset (31 bits)
3797 pub const offset: u32 = 31;
3798 /// Mask (1 bit: 1 << 31)
3799 pub const mask: u32 = 1 << offset;
3800 /// Read-only values (empty)
3801 pub mod R {}
3802 /// Write-only values (empty)
3803 pub mod W {}
3804 /// Read-write values (empty)
3805 pub mod RW {}
3806 }
3807
3808 /// CPU2 USB clock enable
3809 pub mod USBEN {
3810 /// Offset (26 bits)
3811 pub const offset: u32 = 26;
3812 /// Mask (1 bit: 1 << 26)
3813 pub const mask: u32 = 1 << offset;
3814 /// Read-only values (empty)
3815 pub mod R {}
3816 /// Write-only values (empty)
3817 pub mod W {}
3818 /// Read-write values (empty)
3819 pub mod RW {}
3820 }
3821
3822 /// CPU2 CRS clock enable
3823 pub mod CRSEN {
3824 /// Offset (24 bits)
3825 pub const offset: u32 = 24;
3826 /// Mask (1 bit: 1 << 24)
3827 pub const mask: u32 = 1 << offset;
3828 /// Read-only values (empty)
3829 pub mod R {}
3830 /// Write-only values (empty)
3831 pub mod W {}
3832 /// Read-write values (empty)
3833 pub mod RW {}
3834 }
3835
3836 /// CPU2 I2C3 clock enable
3837 pub mod I2C3EN {
3838 /// Offset (23 bits)
3839 pub const offset: u32 = 23;
3840 /// Mask (1 bit: 1 << 23)
3841 pub const mask: u32 = 1 << offset;
3842 /// Read-only values (empty)
3843 pub mod R {}
3844 /// Write-only values (empty)
3845 pub mod W {}
3846 /// Read-write values (empty)
3847 pub mod RW {}
3848 }
3849
3850 /// CPU2 I2C1 clock enable
3851 pub mod I2C1EN {
3852 /// Offset (21 bits)
3853 pub const offset: u32 = 21;
3854 /// Mask (1 bit: 1 << 21)
3855 pub const mask: u32 = 1 << offset;
3856 /// Read-only values (empty)
3857 pub mod R {}
3858 /// Write-only values (empty)
3859 pub mod W {}
3860 /// Read-write values (empty)
3861 pub mod RW {}
3862 }
3863
3864 /// CPU2 SPI2 clock enable
3865 pub mod SPI2EN {
3866 /// Offset (14 bits)
3867 pub const offset: u32 = 14;
3868 /// Mask (1 bit: 1 << 14)
3869 pub const mask: u32 = 1 << offset;
3870 /// Read-only values (empty)
3871 pub mod R {}
3872 /// Write-only values (empty)
3873 pub mod W {}
3874 /// Read-write values (empty)
3875 pub mod RW {}
3876 }
3877
3878 /// CPU2 RTC APB clock enable
3879 pub mod RTCAPBEN {
3880 /// Offset (10 bits)
3881 pub const offset: u32 = 10;
3882 /// Mask (1 bit: 1 << 10)
3883 pub const mask: u32 = 1 << offset;
3884 /// Read-only values (empty)
3885 pub mod R {}
3886 /// Write-only values (empty)
3887 pub mod W {}
3888 /// Read-write values (empty)
3889 pub mod RW {}
3890 }
3891
3892 /// CPU2 LCD clock enable
3893 pub mod LCDEN {
3894 /// Offset (9 bits)
3895 pub const offset: u32 = 9;
3896 /// Mask (1 bit: 1 << 9)
3897 pub const mask: u32 = 1 << offset;
3898 /// Read-only values (empty)
3899 pub mod R {}
3900 /// Write-only values (empty)
3901 pub mod W {}
3902 /// Read-write values (empty)
3903 pub mod RW {}
3904 }
3905
3906 /// CPU2 TIM2 timer clock enable
3907 pub mod TIM2EN {
3908 /// Offset (0 bits)
3909 pub const offset: u32 = 0;
3910 /// Mask (1 bit: 1 << 0)
3911 pub const mask: u32 = 1 << offset;
3912 /// Read-only values (empty)
3913 pub mod R {}
3914 /// Write-only values (empty)
3915 pub mod W {}
3916 /// Read-write values (empty)
3917 pub mod RW {}
3918 }
3919}
3920
3921/// CPU2 APB1 peripheral clock enable register 2
3922pub mod C2APB1ENR2 {
3923 pub use super::APB1ENR2::LPTIM2EN;
3924 pub use super::APB1ENR2::LPUART1EN;
3925}
3926
3927/// CPU2 APB2ENR
3928pub mod C2APB2ENR {
3929 pub use super::APB2ENR::SAI1EN;
3930 pub use super::APB2ENR::SPI1EN;
3931 pub use super::APB2ENR::TIM16EN;
3932 pub use super::APB2ENR::TIM17EN;
3933 pub use super::APB2ENR::TIM1EN;
3934 pub use super::APB2ENR::USART1EN;
3935}
3936
3937/// CPU2 APB3ENR
3938pub mod C2APB3ENR {
3939
3940 /// CPU2 802.15.4 interface clock enable
3941 pub mod EN802 {
3942 /// Offset (1 bits)
3943 pub const offset: u32 = 1;
3944 /// Mask (1 bit: 1 << 1)
3945 pub const mask: u32 = 1 << offset;
3946 /// Read-only values (empty)
3947 pub mod R {}
3948 /// Write-only values (empty)
3949 pub mod W {}
3950 /// Read-write values (empty)
3951 pub mod RW {}
3952 }
3953
3954 /// CPU2 BLE interface clock enable
3955 pub mod BLEEN {
3956 /// Offset (0 bits)
3957 pub const offset: u32 = 0;
3958 /// Mask (1 bit: 1 << 0)
3959 pub const mask: u32 = 1 << offset;
3960 /// Read-only values (empty)
3961 pub mod R {}
3962 /// Write-only values (empty)
3963 pub mod W {}
3964 /// Read-write values (empty)
3965 pub mod RW {}
3966 }
3967}
3968
3969/// CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
3970pub mod C2AHB1SMENR {
3971 pub use super::AHB1SMENR::CRCSMEN;
3972 pub use super::AHB1SMENR::DMA1SMEN;
3973 pub use super::AHB1SMENR::DMA2SMEN;
3974 pub use super::AHB1SMENR::DMAMUXSMEN;
3975 pub use super::AHB1SMENR::SRAM1SMEN;
3976 pub use super::AHB1SMENR::TSCSMEN;
3977}
3978
3979/// CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
3980pub mod C2AHB2SMENR {
3981 pub use super::AHB2SMENR::ADCFSSMEN;
3982 pub use super::AHB2SMENR::AES1SMEN;
3983 pub use super::AHB2SMENR::GPIOASMEN;
3984 pub use super::AHB2SMENR::GPIOBSMEN;
3985 pub use super::AHB2SMENR::GPIOCSMEN;
3986 pub use super::AHB2SMENR::GPIODSMEN;
3987 pub use super::AHB2SMENR::GPIOESMEN;
3988 pub use super::AHB2SMENR::GPIOHSMEN;
3989}
3990
3991/// CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
3992pub mod C2AHB3SMENR {
3993
3994 /// Flash interface clocks enable during CPU2 sleep modes
3995 pub mod FLASHSMEN {
3996 /// Offset (25 bits)
3997 pub const offset: u32 = 25;
3998 /// Mask (1 bit: 1 << 25)
3999 pub const mask: u32 = 1 << offset;
4000 /// Read-only values (empty)
4001 pub mod R {}
4002 /// Write-only values (empty)
4003 pub mod W {}
4004 /// Read-write values (empty)
4005 pub mod RW {}
4006 }
4007
4008 /// SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes
4009 pub mod SRAM2SMEN {
4010 /// Offset (24 bits)
4011 pub const offset: u32 = 24;
4012 /// Mask (1 bit: 1 << 24)
4013 pub const mask: u32 = 1 << offset;
4014 /// Read-only values (empty)
4015 pub mod R {}
4016 /// Write-only values (empty)
4017 pub mod W {}
4018 /// Read-write values (empty)
4019 pub mod RW {}
4020 }
4021
4022 /// True RNG clocks enable during CPU2 sleep modes
4023 pub mod RNGSMEN {
4024 /// Offset (18 bits)
4025 pub const offset: u32 = 18;
4026 /// Mask (1 bit: 1 << 18)
4027 pub const mask: u32 = 1 << offset;
4028 /// Read-only values (empty)
4029 pub mod R {}
4030 /// Write-only values (empty)
4031 pub mod W {}
4032 /// Read-write values (empty)
4033 pub mod RW {}
4034 }
4035
4036 /// AES2 accelerator clocks enable during CPU2 sleep modes
4037 pub mod AES2SMEN {
4038 /// Offset (17 bits)
4039 pub const offset: u32 = 17;
4040 /// Mask (1 bit: 1 << 17)
4041 pub const mask: u32 = 1 << offset;
4042 /// Read-only values (empty)
4043 pub mod R {}
4044 /// Write-only values (empty)
4045 pub mod W {}
4046 /// Read-write values (empty)
4047 pub mod RW {}
4048 }
4049
4050 /// PKA accelerator clocks enable during CPU2 sleep modes
4051 pub mod PKASMEN {
4052 /// Offset (16 bits)
4053 pub const offset: u32 = 16;
4054 /// Mask (1 bit: 1 << 16)
4055 pub const mask: u32 = 1 << offset;
4056 /// Read-only values (empty)
4057 pub mod R {}
4058 /// Write-only values (empty)
4059 pub mod W {}
4060 /// Read-write values (empty)
4061 pub mod RW {}
4062 }
4063}
4064
4065/// CPU2 APB1SMENR1
4066pub mod C2APB1SMENR1 {
4067
4068 /// Low power timer 1 clocks enable during CPU2 Sleep mode
4069 pub mod LPTIM1SMEN {
4070 /// Offset (31 bits)
4071 pub const offset: u32 = 31;
4072 /// Mask (1 bit: 1 << 31)
4073 pub const mask: u32 = 1 << offset;
4074 /// Read-only values (empty)
4075 pub mod R {}
4076 /// Write-only values (empty)
4077 pub mod W {}
4078 /// Read-write values (empty)
4079 pub mod RW {}
4080 }
4081
4082 /// USB FS clocks enable during CPU2 Sleep mode
4083 pub mod USBSMEN {
4084 /// Offset (26 bits)
4085 pub const offset: u32 = 26;
4086 /// Mask (1 bit: 1 << 26)
4087 pub const mask: u32 = 1 << offset;
4088 /// Read-only values (empty)
4089 pub mod R {}
4090 /// Write-only values (empty)
4091 pub mod W {}
4092 /// Read-write values (empty)
4093 pub mod RW {}
4094 }
4095
4096 /// CRS clocks enable during CPU2 Sleep mode
4097 pub mod CRSMEN {
4098 /// Offset (24 bits)
4099 pub const offset: u32 = 24;
4100 /// Mask (1 bit: 1 << 24)
4101 pub const mask: u32 = 1 << offset;
4102 /// Read-only values (empty)
4103 pub mod R {}
4104 /// Write-only values (empty)
4105 pub mod W {}
4106 /// Read-write values (empty)
4107 pub mod RW {}
4108 }
4109
4110 /// I2C3 clocks enable during CPU2 Sleep mode
4111 pub mod I2C3SMEN {
4112 /// Offset (23 bits)
4113 pub const offset: u32 = 23;
4114 /// Mask (1 bit: 1 << 23)
4115 pub const mask: u32 = 1 << offset;
4116 /// Read-only values (empty)
4117 pub mod R {}
4118 /// Write-only values (empty)
4119 pub mod W {}
4120 /// Read-write values (empty)
4121 pub mod RW {}
4122 }
4123
4124 /// I2C1 clocks enable during CPU2 Sleep mode
4125 pub mod I2C1SMEN {
4126 /// Offset (21 bits)
4127 pub const offset: u32 = 21;
4128 /// Mask (1 bit: 1 << 21)
4129 pub const mask: u32 = 1 << offset;
4130 /// Read-only values (empty)
4131 pub mod R {}
4132 /// Write-only values (empty)
4133 pub mod W {}
4134 /// Read-write values (empty)
4135 pub mod RW {}
4136 }
4137
4138 /// SPI2 clocks enable during CPU2 Sleep mode
4139 pub mod SPI2SMEN {
4140 /// Offset (14 bits)
4141 pub const offset: u32 = 14;
4142 /// Mask (1 bit: 1 << 14)
4143 pub const mask: u32 = 1 << offset;
4144 /// Read-only values (empty)
4145 pub mod R {}
4146 /// Write-only values (empty)
4147 pub mod W {}
4148 /// Read-write values (empty)
4149 pub mod RW {}
4150 }
4151
4152 /// RTC APB clocks enable during CPU2 Sleep mode
4153 pub mod RTCAPBSMEN {
4154 /// Offset (10 bits)
4155 pub const offset: u32 = 10;
4156 /// Mask (1 bit: 1 << 10)
4157 pub const mask: u32 = 1 << offset;
4158 /// Read-only values (empty)
4159 pub mod R {}
4160 /// Write-only values (empty)
4161 pub mod W {}
4162 /// Read-write values (empty)
4163 pub mod RW {}
4164 }
4165
4166 /// LCD clocks enable during CPU2 Sleep mode
4167 pub mod LCDSMEN {
4168 /// Offset (9 bits)
4169 pub const offset: u32 = 9;
4170 /// Mask (1 bit: 1 << 9)
4171 pub const mask: u32 = 1 << offset;
4172 /// Read-only values (empty)
4173 pub mod R {}
4174 /// Write-only values (empty)
4175 pub mod W {}
4176 /// Read-write values (empty)
4177 pub mod RW {}
4178 }
4179
4180 /// TIM2 timer clocks enable during CPU2 Sleep mode
4181 pub mod TIM2SMEN {
4182 /// Offset (0 bits)
4183 pub const offset: u32 = 0;
4184 /// Mask (1 bit: 1 << 0)
4185 pub const mask: u32 = 1 << offset;
4186 /// Read-only values (empty)
4187 pub mod R {}
4188 /// Write-only values (empty)
4189 pub mod W {}
4190 /// Read-write values (empty)
4191 pub mod RW {}
4192 }
4193}
4194
4195/// CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
4196pub mod C2APB1SMENR2 {
4197 pub use super::APB1SMENR2::LPTIM2SMEN;
4198 pub use super::APB1SMENR2::LPUART1SMEN;
4199}
4200
4201/// CPU2 APB2SMENR
4202pub mod C2APB2SMENR {
4203 pub use super::APB2SMENR::SAI1SMEN;
4204 pub use super::APB2SMENR::SPI1SMEN;
4205 pub use super::APB2SMENR::TIM16SMEN;
4206 pub use super::APB2SMENR::TIM17SMEN;
4207 pub use super::APB2SMENR::TIM1SMEN;
4208 pub use super::APB2SMENR::USART1SMEN;
4209}
4210
4211/// CPU2 APB3SMENR
4212pub mod C2APB3SMENR {
4213
4214 /// 802.15.4 interface clocks enable during CPU2 Sleep modes
4215 pub mod SMEN802 {
4216 /// Offset (1 bits)
4217 pub const offset: u32 = 1;
4218 /// Mask (1 bit: 1 << 1)
4219 pub const mask: u32 = 1 << offset;
4220 /// Read-only values (empty)
4221 pub mod R {}
4222 /// Write-only values (empty)
4223 pub mod W {}
4224 /// Read-write values (empty)
4225 pub mod RW {}
4226 }
4227
4228 /// BLE interface clocks enable during CPU2 Sleep mode
4229 pub mod BLESMEN {
4230 /// Offset (0 bits)
4231 pub const offset: u32 = 0;
4232 /// Mask (1 bit: 1 << 0)
4233 pub const mask: u32 = 1 << offset;
4234 /// Read-only values (empty)
4235 pub mod R {}
4236 /// Write-only values (empty)
4237 pub mod W {}
4238 /// Read-write values (empty)
4239 pub mod RW {}
4240 }
4241}
4242#[repr(C)]
4243pub struct RegisterBlock {
4244 /// Clock control register
4245 pub CR: RWRegister<u32>,
4246
4247 /// Internal clock sources calibration register
4248 pub ICSCR: RWRegister<u32>,
4249
4250 /// Clock configuration register
4251 pub CFGR: RWRegister<u32>,
4252
4253 /// PLLSYS configuration register
4254 pub PLLCFGR: RWRegister<u32>,
4255
4256 /// PLLSAI1 configuration register
4257 pub PLLSAI1CFGR: RWRegister<u32>,
4258
4259 _reserved1: [u8; 4],
4260
4261 /// Clock interrupt enable register
4262 pub CIER: RWRegister<u32>,
4263
4264 /// Clock interrupt flag register
4265 pub CIFR: RORegister<u32>,
4266
4267 /// Clock interrupt clear register
4268 pub CICR: WORegister<u32>,
4269
4270 /// Step Down converter control register
4271 pub SMPSCR: RWRegister<u32>,
4272
4273 /// AHB1 peripheral reset register
4274 pub AHB1RSTR: RWRegister<u32>,
4275
4276 /// AHB2 peripheral reset register
4277 pub AHB2RSTR: RWRegister<u32>,
4278
4279 /// AHB3 peripheral reset register
4280 pub AHB3RSTR: RWRegister<u32>,
4281
4282 _reserved2: [u8; 4],
4283
4284 /// APB1 peripheral reset register 1
4285 pub APB1RSTR1: RWRegister<u32>,
4286
4287 /// APB1 peripheral reset register 2
4288 pub APB1RSTR2: RWRegister<u32>,
4289
4290 /// APB2 peripheral reset register
4291 pub APB2RSTR: RWRegister<u32>,
4292
4293 /// APB3 peripheral reset register
4294 pub APB3RSTR: RWRegister<u32>,
4295
4296 /// AHB1 peripheral clock enable register
4297 pub AHB1ENR: RWRegister<u32>,
4298
4299 /// AHB2 peripheral clock enable register
4300 pub AHB2ENR: RWRegister<u32>,
4301
4302 /// AHB3 peripheral clock enable register
4303 pub AHB3ENR: RWRegister<u32>,
4304
4305 _reserved3: [u8; 4],
4306
4307 /// APB1ENR1
4308 pub APB1ENR1: RWRegister<u32>,
4309
4310 /// APB1 peripheral clock enable register 2
4311 pub APB1ENR2: RWRegister<u32>,
4312
4313 /// APB2ENR
4314 pub APB2ENR: RWRegister<u32>,
4315
4316 _reserved4: [u8; 4],
4317
4318 /// AHB1 peripheral clocks enable in Sleep and Stop modes register
4319 pub AHB1SMENR: RWRegister<u32>,
4320
4321 /// AHB2 peripheral clocks enable in Sleep and Stop modes register
4322 pub AHB2SMENR: RWRegister<u32>,
4323
4324 /// AHB3 peripheral clocks enable in Sleep and Stop modes register
4325 pub AHB3SMENR: RWRegister<u32>,
4326
4327 _reserved5: [u8; 4],
4328
4329 /// APB1SMENR1
4330 pub APB1SMENR1: RWRegister<u32>,
4331
4332 /// APB1 peripheral clocks enable in Sleep and Stop modes register 2
4333 pub APB1SMENR2: RWRegister<u32>,
4334
4335 /// APB2SMENR
4336 pub APB2SMENR: RWRegister<u32>,
4337
4338 _reserved6: [u8; 4],
4339
4340 /// CCIPR
4341 pub CCIPR: RWRegister<u32>,
4342
4343 _reserved7: [u8; 4],
4344
4345 /// BDCR
4346 pub BDCR: RWRegister<u32>,
4347
4348 /// CSR
4349 pub CSR: RWRegister<u32>,
4350
4351 /// Clock recovery RC register
4352 pub CRRCR: RWRegister<u32>,
4353
4354 /// Clock HSE register
4355 pub HSECR: RWRegister<u32>,
4356
4357 _reserved8: [u8; 104],
4358
4359 /// Extended clock recovery register
4360 pub EXTCFGR: RWRegister<u32>,
4361
4362 _reserved9: [u8; 60],
4363
4364 /// CPU2 AHB1 peripheral clock enable register
4365 pub C2AHB1ENR: RWRegister<u32>,
4366
4367 /// CPU2 AHB2 peripheral clock enable register
4368 pub C2AHB2ENR: RWRegister<u32>,
4369
4370 /// CPU2 AHB3 peripheral clock enable register
4371 pub C2AHB3ENR: RWRegister<u32>,
4372
4373 _reserved10: [u8; 4],
4374
4375 /// CPU2 APB1ENR1
4376 pub C2APB1ENR1: RWRegister<u32>,
4377
4378 /// CPU2 APB1 peripheral clock enable register 2
4379 pub C2APB1ENR2: RWRegister<u32>,
4380
4381 /// CPU2 APB2ENR
4382 pub C2APB2ENR: RWRegister<u32>,
4383
4384 /// CPU2 APB3ENR
4385 pub C2APB3ENR: RWRegister<u32>,
4386
4387 /// CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
4388 pub C2AHB1SMENR: RWRegister<u32>,
4389
4390 /// CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
4391 pub C2AHB2SMENR: RWRegister<u32>,
4392
4393 /// CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
4394 pub C2AHB3SMENR: RWRegister<u32>,
4395
4396 _reserved11: [u8; 4],
4397
4398 /// CPU2 APB1SMENR1
4399 pub C2APB1SMENR1: RWRegister<u32>,
4400
4401 /// CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
4402 pub C2APB1SMENR2: RWRegister<u32>,
4403
4404 /// CPU2 APB2SMENR
4405 pub C2APB2SMENR: RWRegister<u32>,
4406
4407 /// CPU2 APB3SMENR
4408 pub C2APB3SMENR: RWRegister<u32>,
4409}
4410pub struct ResetValues {
4411 pub CR: u32,
4412 pub ICSCR: u32,
4413 pub CFGR: u32,
4414 pub PLLCFGR: u32,
4415 pub PLLSAI1CFGR: u32,
4416 pub CIER: u32,
4417 pub CIFR: u32,
4418 pub CICR: u32,
4419 pub SMPSCR: u32,
4420 pub AHB1RSTR: u32,
4421 pub AHB2RSTR: u32,
4422 pub AHB3RSTR: u32,
4423 pub APB1RSTR1: u32,
4424 pub APB1RSTR2: u32,
4425 pub APB2RSTR: u32,
4426 pub APB3RSTR: u32,
4427 pub AHB1ENR: u32,
4428 pub AHB2ENR: u32,
4429 pub AHB3ENR: u32,
4430 pub APB1ENR1: u32,
4431 pub APB1ENR2: u32,
4432 pub APB2ENR: u32,
4433 pub AHB1SMENR: u32,
4434 pub AHB2SMENR: u32,
4435 pub AHB3SMENR: u32,
4436 pub APB1SMENR1: u32,
4437 pub APB1SMENR2: u32,
4438 pub APB2SMENR: u32,
4439 pub CCIPR: u32,
4440 pub BDCR: u32,
4441 pub CSR: u32,
4442 pub CRRCR: u32,
4443 pub HSECR: u32,
4444 pub EXTCFGR: u32,
4445 pub C2AHB1ENR: u32,
4446 pub C2AHB2ENR: u32,
4447 pub C2AHB3ENR: u32,
4448 pub C2APB1ENR1: u32,
4449 pub C2APB1ENR2: u32,
4450 pub C2APB2ENR: u32,
4451 pub C2APB3ENR: u32,
4452 pub C2AHB1SMENR: u32,
4453 pub C2AHB2SMENR: u32,
4454 pub C2AHB3SMENR: u32,
4455 pub C2APB1SMENR1: u32,
4456 pub C2APB1SMENR2: u32,
4457 pub C2APB2SMENR: u32,
4458 pub C2APB3SMENR: u32,
4459}
4460#[cfg(not(feature = "nosync"))]
4461pub struct Instance {
4462 pub(crate) addr: u32,
4463 pub(crate) _marker: PhantomData<*const RegisterBlock>,
4464}
4465#[cfg(not(feature = "nosync"))]
4466impl ::core::ops::Deref for Instance {
4467 type Target = RegisterBlock;
4468 #[inline(always)]
4469 fn deref(&self) -> &RegisterBlock {
4470 unsafe { &*(self.addr as *const _) }
4471 }
4472}
4473#[cfg(feature = "rtic")]
4474unsafe impl Send for Instance {}
4475
4476/// Access functions for the RCC peripheral instance
4477pub mod RCC {
4478 use super::ResetValues;
4479
4480 #[cfg(not(feature = "nosync"))]
4481 use super::Instance;
4482
4483 #[cfg(not(feature = "nosync"))]
4484 const INSTANCE: Instance = Instance {
4485 addr: 0x58000000,
4486 _marker: ::core::marker::PhantomData,
4487 };
4488
4489 /// Reset values for each field in RCC
4490 pub const reset: ResetValues = ResetValues {
4491 CR: 0x00000061,
4492 ICSCR: 0x40000000,
4493 CFGR: 0x00070000,
4494 PLLCFGR: 0x22040100,
4495 PLLSAI1CFGR: 0x22040100,
4496 CIER: 0x00000000,
4497 CIFR: 0x00000000,
4498 CICR: 0x00000000,
4499 SMPSCR: 0x00000301,
4500 AHB1RSTR: 0x00000000,
4501 AHB2RSTR: 0x00000000,
4502 AHB3RSTR: 0x00000000,
4503 APB1RSTR1: 0x00000000,
4504 APB1RSTR2: 0x00000000,
4505 APB2RSTR: 0x00000000,
4506 APB3RSTR: 0x00000000,
4507 AHB1ENR: 0x00000100,
4508 AHB2ENR: 0x00000000,
4509 AHB3ENR: 0x02080000,
4510 APB1ENR1: 0x00000400,
4511 APB1ENR2: 0x00000000,
4512 APB2ENR: 0x00000000,
4513 AHB1SMENR: 0x00011207,
4514 AHB2SMENR: 0x0001209F,
4515 AHB3SMENR: 0x03070100,
4516 APB1SMENR1: 0x85A04E01,
4517 APB1SMENR2: 0x00000021,
4518 APB2SMENR: 0x00265800,
4519 CCIPR: 0x00000000,
4520 BDCR: 0x00000000,
4521 CSR: 0x0C000000,
4522 CRRCR: 0x00000000,
4523 HSECR: 0x00000030,
4524 EXTCFGR: 0x00030000,
4525 C2AHB1ENR: 0x00000000,
4526 C2AHB2ENR: 0x00000000,
4527 C2AHB3ENR: 0x02080000,
4528 C2APB1ENR1: 0x00000400,
4529 C2APB1ENR2: 0x00000000,
4530 C2APB2ENR: 0x00000000,
4531 C2APB3ENR: 0x00000000,
4532 C2AHB1SMENR: 0x00011207,
4533 C2AHB2SMENR: 0x0001209F,
4534 C2AHB3SMENR: 0x03070000,
4535 C2APB1SMENR1: 0x85A04601,
4536 C2APB1SMENR2: 0x00000021,
4537 C2APB2SMENR: 0x00265800,
4538 C2APB3SMENR: 0x00000003,
4539 };
4540
4541 #[cfg(not(feature = "nosync"))]
4542 #[allow(renamed_and_removed_lints)]
4543 #[allow(private_no_mangle_statics)]
4544 #[no_mangle]
4545 static mut RCC_TAKEN: bool = false;
4546
4547 /// Safe access to RCC
4548 ///
4549 /// This function returns `Some(Instance)` if this instance is not
4550 /// currently taken, and `None` if it is. This ensures that if you
4551 /// do get `Some(Instance)`, you are ensured unique access to
4552 /// the peripheral and there cannot be data races (unless other
4553 /// code uses `unsafe`, of course). You can then pass the
4554 /// `Instance` around to other functions as required. When you're
4555 /// done with it, you can call `release(instance)` to return it.
4556 ///
4557 /// `Instance` itself dereferences to a `RegisterBlock`, which
4558 /// provides access to the peripheral's registers.
4559 #[cfg(not(feature = "nosync"))]
4560 #[inline]
4561 pub fn take() -> Option<Instance> {
4562 external_cortex_m::interrupt::free(|_| unsafe {
4563 if RCC_TAKEN {
4564 None
4565 } else {
4566 RCC_TAKEN = true;
4567 Some(INSTANCE)
4568 }
4569 })
4570 }
4571
4572 /// Release exclusive access to RCC
4573 ///
4574 /// This function allows you to return an `Instance` so that it
4575 /// is available to `take()` again. This function will panic if
4576 /// you return a different `Instance` or if this instance is not
4577 /// already taken.
4578 #[cfg(not(feature = "nosync"))]
4579 #[inline]
4580 pub fn release(inst: Instance) {
4581 external_cortex_m::interrupt::free(|_| unsafe {
4582 if RCC_TAKEN && inst.addr == INSTANCE.addr {
4583 RCC_TAKEN = false;
4584 } else {
4585 panic!("Released a peripheral which was not taken");
4586 }
4587 });
4588 }
4589
4590 /// Unsafely steal RCC
4591 ///
4592 /// This function is similar to take() but forcibly takes the
4593 /// Instance, marking it as taken irregardless of its previous
4594 /// state.
4595 #[cfg(not(feature = "nosync"))]
4596 #[inline]
4597 pub unsafe fn steal() -> Instance {
4598 RCC_TAKEN = true;
4599 INSTANCE
4600 }
4601}
4602
4603/// Raw pointer to RCC
4604///
4605/// Dereferencing this is unsafe because you are not ensured unique
4606/// access to the peripheral, so you may encounter data races with
4607/// other users of this peripheral. It is up to you to ensure you
4608/// will not cause data races.
4609///
4610/// This constant is provided for ease of use in unsafe code: you can
4611/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
4612pub const RCC: *const RegisterBlock = 0x58000000 as *const _;