stm32ral/stm32mp/instances/
tim2.rs

1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! TIM2
4//!
5//! Used by: stm32mp153, stm32mp157
6
7#[cfg(not(feature = "nosync"))]
8pub use crate::stm32mp::peripherals::tim2::Instance;
9pub use crate::stm32mp::peripherals::tim2::{RegisterBlock, ResetValues};
10pub use crate::stm32mp::peripherals::tim2::{
11    TIM2_ARR, TIM2_BDTR, TIM2_CCER, TIM2_CCMR1ALTERNATE2, TIM2_CCMR2ALTERNATE18, TIM2_CCMR3,
12    TIM2_CCR1, TIM2_CCR2, TIM2_CCR3, TIM2_CCR4, TIM2_CCR5, TIM2_CCR6, TIM2_CNT, TIM2_CR1, TIM2_CR2,
13    TIM2_DCR, TIM2_DIER, TIM2_DMAR, TIM2_EGR, TIM2_PSC, TIM2_RCR, TIM2_SMCR, TIM2_SR,
14};
15
16/// Access functions for the TIM2 peripheral instance
17pub mod TIM2 {
18    use super::ResetValues;
19
20    #[cfg(not(feature = "nosync"))]
21    use super::Instance;
22
23    #[cfg(not(feature = "nosync"))]
24    const INSTANCE: Instance = Instance {
25        addr: 0x40000000,
26        _marker: ::core::marker::PhantomData,
27    };
28
29    /// Reset values for each field in TIM2
30    pub const reset: ResetValues = ResetValues {
31        TIM2_CR1: 0x00000000,
32        TIM2_CR2: 0x00000000,
33        TIM2_SMCR: 0x00000000,
34        TIM2_DIER: 0x00000000,
35        TIM2_SR: 0x00000000,
36        TIM2_EGR: 0x00000000,
37        TIM2_CCMR1ALTERNATE2: 0x00000000,
38        TIM2_CCMR2ALTERNATE18: 0x00000000,
39        TIM2_CCER: 0x00000000,
40        TIM2_CNT: 0x00000000,
41        TIM2_PSC: 0x00000000,
42        TIM2_ARR: 0x0000FFFF,
43        TIM2_RCR: 0x00000000,
44        TIM2_CCR1: 0x00000000,
45        TIM2_CCR2: 0x00000000,
46        TIM2_CCR3: 0x00000000,
47        TIM2_CCR4: 0x00000000,
48        TIM2_BDTR: 0x00000000,
49        TIM2_DCR: 0x00000000,
50        TIM2_DMAR: 0x00000000,
51        TIM2_CCMR3: 0x00000000,
52        TIM2_CCR5: 0x00000000,
53        TIM2_CCR6: 0x00000000,
54    };
55
56    #[cfg(not(feature = "nosync"))]
57    #[allow(renamed_and_removed_lints)]
58    #[allow(private_no_mangle_statics)]
59    #[no_mangle]
60    static mut TIM2_TAKEN: bool = false;
61
62    /// Safe access to TIM2
63    ///
64    /// This function returns `Some(Instance)` if this instance is not
65    /// currently taken, and `None` if it is. This ensures that if you
66    /// do get `Some(Instance)`, you are ensured unique access to
67    /// the peripheral and there cannot be data races (unless other
68    /// code uses `unsafe`, of course). You can then pass the
69    /// `Instance` around to other functions as required. When you're
70    /// done with it, you can call `release(instance)` to return it.
71    ///
72    /// `Instance` itself dereferences to a `RegisterBlock`, which
73    /// provides access to the peripheral's registers.
74    #[cfg(not(feature = "nosync"))]
75    #[inline]
76    pub fn take() -> Option<Instance> {
77        external_cortex_m::interrupt::free(|_| unsafe {
78            if TIM2_TAKEN {
79                None
80            } else {
81                TIM2_TAKEN = true;
82                Some(INSTANCE)
83            }
84        })
85    }
86
87    /// Release exclusive access to TIM2
88    ///
89    /// This function allows you to return an `Instance` so that it
90    /// is available to `take()` again. This function will panic if
91    /// you return a different `Instance` or if this instance is not
92    /// already taken.
93    #[cfg(not(feature = "nosync"))]
94    #[inline]
95    pub fn release(inst: Instance) {
96        external_cortex_m::interrupt::free(|_| unsafe {
97            if TIM2_TAKEN && inst.addr == INSTANCE.addr {
98                TIM2_TAKEN = false;
99            } else {
100                panic!("Released a peripheral which was not taken");
101            }
102        });
103    }
104
105    /// Unsafely steal TIM2
106    ///
107    /// This function is similar to take() but forcibly takes the
108    /// Instance, marking it as taken irregardless of its previous
109    /// state.
110    #[cfg(not(feature = "nosync"))]
111    #[inline]
112    pub unsafe fn steal() -> Instance {
113        TIM2_TAKEN = true;
114        INSTANCE
115    }
116}
117
118/// Raw pointer to TIM2
119///
120/// Dereferencing this is unsafe because you are not ensured unique
121/// access to the peripheral, so you may encounter data races with
122/// other users of this peripheral. It is up to you to ensure you
123/// will not cause data races.
124///
125/// This constant is provided for ease of use in unsafe code: you can
126/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
127pub const TIM2: *const RegisterBlock = 0x40000000 as *const _;
stm32ral/stm32mp/instances/tim2.rs

stm32ral/stm32mp/instances/
tim2.rs
