stm32ral/stm32l5/stm32l562/aes.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Advanced encryption standard hardware accelerator 1
4
5use crate::{RORegister, RWRegister, WORegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// control register
10pub mod CR {
11
12 /// Number of padding bytes in last block of payload
13 pub mod NPBLB {
14 /// Offset (20 bits)
15 pub const offset: u32 = 20;
16 /// Mask (4 bits: 0b1111 << 20)
17 pub const mask: u32 = 0b1111 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25
26 /// Key size selection
27 pub mod KEYSIZE {
28 /// Offset (18 bits)
29 pub const offset: u32 = 18;
30 /// Mask (1 bit: 1 << 18)
31 pub const mask: u32 = 1 << offset;
32 /// Read-only values (empty)
33 pub mod R {}
34 /// Write-only values (empty)
35 pub mod W {}
36 /// Read-write values (empty)
37 pub mod RW {}
38 }
39
40 /// AES chaining mode Bit2
41 pub mod CHMOD2 {
42 /// Offset (16 bits)
43 pub const offset: u32 = 16;
44 /// Mask (1 bit: 1 << 16)
45 pub const mask: u32 = 1 << offset;
46 /// Read-only values (empty)
47 pub mod R {}
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53
54 /// Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected
55 pub mod GCMPH {
56 /// Offset (13 bits)
57 pub const offset: u32 = 13;
58 /// Mask (2 bits: 0b11 << 13)
59 pub const mask: u32 = 0b11 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// Enable DMA management of data output phase
69 pub mod DMAOUTEN {
70 /// Offset (12 bits)
71 pub const offset: u32 = 12;
72 /// Mask (1 bit: 1 << 12)
73 pub const mask: u32 = 1 << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// Enable DMA management of data input phase
83 pub mod DMAINEN {
84 /// Offset (11 bits)
85 pub const offset: u32 = 11;
86 /// Mask (1 bit: 1 << 11)
87 pub const mask: u32 = 1 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 /// Read-write values (empty)
93 pub mod RW {}
94 }
95
96 /// Error interrupt enable
97 pub mod ERRIE {
98 /// Offset (10 bits)
99 pub const offset: u32 = 10;
100 /// Mask (1 bit: 1 << 10)
101 pub const mask: u32 = 1 << offset;
102 /// Read-only values (empty)
103 pub mod R {}
104 /// Write-only values (empty)
105 pub mod W {}
106 /// Read-write values (empty)
107 pub mod RW {}
108 }
109
110 /// CCF flag interrupt enable
111 pub mod CCFIE {
112 /// Offset (9 bits)
113 pub const offset: u32 = 9;
114 /// Mask (1 bit: 1 << 9)
115 pub const mask: u32 = 1 << offset;
116 /// Read-only values (empty)
117 pub mod R {}
118 /// Write-only values (empty)
119 pub mod W {}
120 /// Read-write values (empty)
121 pub mod RW {}
122 }
123
124 /// Error clear
125 pub mod ERRC {
126 /// Offset (8 bits)
127 pub const offset: u32 = 8;
128 /// Mask (1 bit: 1 << 8)
129 pub const mask: u32 = 1 << offset;
130 /// Read-only values (empty)
131 pub mod R {}
132 /// Write-only values (empty)
133 pub mod W {}
134 /// Read-write values (empty)
135 pub mod RW {}
136 }
137
138 /// Computation Complete Flag Clear
139 pub mod CCFC {
140 /// Offset (7 bits)
141 pub const offset: u32 = 7;
142 /// Mask (1 bit: 1 << 7)
143 pub const mask: u32 = 1 << offset;
144 /// Read-only values (empty)
145 pub mod R {}
146 /// Write-only values (empty)
147 pub mod W {}
148 /// Read-write values (empty)
149 pub mod RW {}
150 }
151
152 /// AES chaining mode selection Bit1 Bit0
153 pub mod CHMOD {
154 /// Offset (5 bits)
155 pub const offset: u32 = 5;
156 /// Mask (2 bits: 0b11 << 5)
157 pub const mask: u32 = 0b11 << offset;
158 /// Read-only values (empty)
159 pub mod R {}
160 /// Write-only values (empty)
161 pub mod W {}
162 /// Read-write values (empty)
163 pub mod RW {}
164 }
165
166 /// AES operating mode
167 pub mod MODE {
168 /// Offset (3 bits)
169 pub const offset: u32 = 3;
170 /// Mask (2 bits: 0b11 << 3)
171 pub const mask: u32 = 0b11 << offset;
172 /// Read-only values (empty)
173 pub mod R {}
174 /// Write-only values (empty)
175 pub mod W {}
176 /// Read-write values (empty)
177 pub mod RW {}
178 }
179
180 /// Data type selection (for data in and data out to/from the cryptographic block)
181 pub mod DATATYPE {
182 /// Offset (1 bits)
183 pub const offset: u32 = 1;
184 /// Mask (2 bits: 0b11 << 1)
185 pub const mask: u32 = 0b11 << offset;
186 /// Read-only values (empty)
187 pub mod R {}
188 /// Write-only values (empty)
189 pub mod W {}
190 /// Read-write values (empty)
191 pub mod RW {}
192 }
193
194 /// AES enable
195 pub mod EN {
196 /// Offset (0 bits)
197 pub const offset: u32 = 0;
198 /// Mask (1 bit: 1 << 0)
199 pub const mask: u32 = 1 << offset;
200 /// Read-only values (empty)
201 pub mod R {}
202 /// Write-only values (empty)
203 pub mod W {}
204 /// Read-write values (empty)
205 pub mod RW {}
206 }
207}
208
209/// status register
210pub mod SR {
211
212 /// Busy flag
213 pub mod BUSY {
214 /// Offset (3 bits)
215 pub const offset: u32 = 3;
216 /// Mask (1 bit: 1 << 3)
217 pub const mask: u32 = 1 << offset;
218 /// Read-only values (empty)
219 pub mod R {}
220 /// Write-only values (empty)
221 pub mod W {}
222 /// Read-write values (empty)
223 pub mod RW {}
224 }
225
226 /// Write error flag
227 pub mod WRERR {
228 /// Offset (2 bits)
229 pub const offset: u32 = 2;
230 /// Mask (1 bit: 1 << 2)
231 pub const mask: u32 = 1 << offset;
232 /// Read-only values (empty)
233 pub mod R {}
234 /// Write-only values (empty)
235 pub mod W {}
236 /// Read-write values (empty)
237 pub mod RW {}
238 }
239
240 /// Read error flag
241 pub mod RDERR {
242 /// Offset (1 bits)
243 pub const offset: u32 = 1;
244 /// Mask (1 bit: 1 << 1)
245 pub const mask: u32 = 1 << offset;
246 /// Read-only values (empty)
247 pub mod R {}
248 /// Write-only values (empty)
249 pub mod W {}
250 /// Read-write values (empty)
251 pub mod RW {}
252 }
253
254 /// Computation complete flag
255 pub mod CCF {
256 /// Offset (0 bits)
257 pub const offset: u32 = 0;
258 /// Mask (1 bit: 1 << 0)
259 pub const mask: u32 = 1 << offset;
260 /// Read-only values (empty)
261 pub mod R {}
262 /// Write-only values (empty)
263 pub mod W {}
264 /// Read-write values (empty)
265 pub mod RW {}
266 }
267}
268
269/// data input register
270pub mod DINR {
271
272 /// Data Input Register
273 pub mod DIN {
274 /// Offset (0 bits)
275 pub const offset: u32 = 0;
276 /// Mask (32 bits: 0xffffffff << 0)
277 pub const mask: u32 = 0xffffffff << offset;
278 /// Read-only values (empty)
279 pub mod R {}
280 /// Write-only values (empty)
281 pub mod W {}
282 /// Read-write values (empty)
283 pub mod RW {}
284 }
285}
286
287/// data output register
288pub mod DOUTR {
289
290 /// Data output register
291 pub mod DOUT {
292 /// Offset (0 bits)
293 pub const offset: u32 = 0;
294 /// Mask (32 bits: 0xffffffff << 0)
295 pub const mask: u32 = 0xffffffff << offset;
296 /// Read-only values (empty)
297 pub mod R {}
298 /// Write-only values (empty)
299 pub mod W {}
300 /// Read-write values (empty)
301 pub mod RW {}
302 }
303}
304
305/// key register 0
306pub mod KEYR0 {
307
308 /// Cryptographic key, bits\[31:0\]
309 pub mod KEY {
310 /// Offset (0 bits)
311 pub const offset: u32 = 0;
312 /// Mask (32 bits: 0xffffffff << 0)
313 pub const mask: u32 = 0xffffffff << offset;
314 /// Read-only values (empty)
315 pub mod R {}
316 /// Write-only values (empty)
317 pub mod W {}
318 /// Read-write values (empty)
319 pub mod RW {}
320 }
321}
322
323/// key register 1
324pub mod KEYR1 {
325 pub use super::KEYR0::KEY;
326}
327
328/// key register 2
329pub mod KEYR2 {
330 pub use super::KEYR0::KEY;
331}
332
333/// key register 3
334pub mod KEYR3 {
335 pub use super::KEYR0::KEY;
336}
337
338/// initialization vector register 0
339pub mod IVR0 {
340
341 /// initialization vector register (LSB IVR \[31:0\])
342 pub mod IVI {
343 /// Offset (0 bits)
344 pub const offset: u32 = 0;
345 /// Mask (32 bits: 0xffffffff << 0)
346 pub const mask: u32 = 0xffffffff << offset;
347 /// Read-only values (empty)
348 pub mod R {}
349 /// Write-only values (empty)
350 pub mod W {}
351 /// Read-write values (empty)
352 pub mod RW {}
353 }
354}
355
356/// initialization vector register 1
357pub mod IVR1 {
358 pub use super::IVR0::IVI;
359}
360
361/// initialization vector register 2
362pub mod IVR2 {
363 pub use super::IVR0::IVI;
364}
365
366/// initialization vector register 3
367pub mod IVR3 {
368 pub use super::IVR0::IVI;
369}
370
371/// key register 4
372pub mod KEYR4 {
373 pub use super::KEYR0::KEY;
374}
375
376/// key register 5
377pub mod KEYR5 {
378 pub use super::KEYR0::KEY;
379}
380
381/// key register 6
382pub mod KEYR6 {
383 pub use super::KEYR0::KEY;
384}
385
386/// key register 7
387pub mod KEYR7 {
388 pub use super::KEYR0::KEY;
389}
390
391/// AES suspend register 0
392pub mod SUSP0R {
393
394 /// AES suspend register 0
395 pub mod AES_SUSP0R {
396 /// Offset (0 bits)
397 pub const offset: u32 = 0;
398 /// Mask (32 bits: 0xffffffff << 0)
399 pub const mask: u32 = 0xffffffff << offset;
400 /// Read-only values (empty)
401 pub mod R {}
402 /// Write-only values (empty)
403 pub mod W {}
404 /// Read-write values (empty)
405 pub mod RW {}
406 }
407}
408
409/// AES suspend register 1
410pub mod SUSP1R {
411
412 /// AES suspend register 1
413 pub mod AES_SUSP1R {
414 /// Offset (0 bits)
415 pub const offset: u32 = 0;
416 /// Mask (32 bits: 0xffffffff << 0)
417 pub const mask: u32 = 0xffffffff << offset;
418 /// Read-only values (empty)
419 pub mod R {}
420 /// Write-only values (empty)
421 pub mod W {}
422 /// Read-write values (empty)
423 pub mod RW {}
424 }
425}
426
427/// AES suspend register 2
428pub mod SUSP2R {
429
430 /// AES suspend register 2
431 pub mod AES_SUSP2R {
432 /// Offset (0 bits)
433 pub const offset: u32 = 0;
434 /// Mask (32 bits: 0xffffffff << 0)
435 pub const mask: u32 = 0xffffffff << offset;
436 /// Read-only values (empty)
437 pub mod R {}
438 /// Write-only values (empty)
439 pub mod W {}
440 /// Read-write values (empty)
441 pub mod RW {}
442 }
443}
444
445/// AES suspend register 3
446pub mod SUSP3R {
447
448 /// AES suspend register 3
449 pub mod AES_SUSP3R {
450 /// Offset (0 bits)
451 pub const offset: u32 = 0;
452 /// Mask (32 bits: 0xffffffff << 0)
453 pub const mask: u32 = 0xffffffff << offset;
454 /// Read-only values (empty)
455 pub mod R {}
456 /// Write-only values (empty)
457 pub mod W {}
458 /// Read-write values (empty)
459 pub mod RW {}
460 }
461}
462
463/// AES suspend register 4
464pub mod SUSP4R {
465
466 /// AES suspend register 4
467 pub mod AES_SUSP4R {
468 /// Offset (0 bits)
469 pub const offset: u32 = 0;
470 /// Mask (32 bits: 0xffffffff << 0)
471 pub const mask: u32 = 0xffffffff << offset;
472 /// Read-only values (empty)
473 pub mod R {}
474 /// Write-only values (empty)
475 pub mod W {}
476 /// Read-write values (empty)
477 pub mod RW {}
478 }
479}
480
481/// AES suspend register 5
482pub mod SUSP5R {
483
484 /// AES suspend register 5
485 pub mod AES_SUSP5R {
486 /// Offset (0 bits)
487 pub const offset: u32 = 0;
488 /// Mask (32 bits: 0xffffffff << 0)
489 pub const mask: u32 = 0xffffffff << offset;
490 /// Read-only values (empty)
491 pub mod R {}
492 /// Write-only values (empty)
493 pub mod W {}
494 /// Read-write values (empty)
495 pub mod RW {}
496 }
497}
498
499/// AES suspend register 6
500pub mod SUSP6R {
501
502 /// AES suspend register 6
503 pub mod AES_SUSP6R {
504 /// Offset (0 bits)
505 pub const offset: u32 = 0;
506 /// Mask (32 bits: 0xffffffff << 0)
507 pub const mask: u32 = 0xffffffff << offset;
508 /// Read-only values (empty)
509 pub mod R {}
510 /// Write-only values (empty)
511 pub mod W {}
512 /// Read-write values (empty)
513 pub mod RW {}
514 }
515}
516
517/// AES suspend register 7
518pub mod SUSP7R {
519
520 /// AES suspend register 7
521 pub mod AES_SUSP7R {
522 /// Offset (0 bits)
523 pub const offset: u32 = 0;
524 /// Mask (32 bits: 0xffffffff << 0)
525 pub const mask: u32 = 0xffffffff << offset;
526 /// Read-only values (empty)
527 pub mod R {}
528 /// Write-only values (empty)
529 pub mod W {}
530 /// Read-write values (empty)
531 pub mod RW {}
532 }
533}
534#[repr(C)]
535pub struct RegisterBlock {
536 /// control register
537 pub CR: RWRegister<u32>,
538
539 /// status register
540 pub SR: RORegister<u32>,
541
542 /// data input register
543 pub DINR: RWRegister<u32>,
544
545 /// data output register
546 pub DOUTR: RORegister<u32>,
547
548 /// key register 0
549 pub KEYR0: WORegister<u32>,
550
551 /// key register 1
552 pub KEYR1: WORegister<u32>,
553
554 /// key register 2
555 pub KEYR2: WORegister<u32>,
556
557 /// key register 3
558 pub KEYR3: WORegister<u32>,
559
560 /// initialization vector register 0
561 pub IVR0: RWRegister<u32>,
562
563 /// initialization vector register 1
564 pub IVR1: RWRegister<u32>,
565
566 /// initialization vector register 2
567 pub IVR2: RWRegister<u32>,
568
569 /// initialization vector register 3
570 pub IVR3: RWRegister<u32>,
571
572 /// key register 4
573 pub KEYR4: WORegister<u32>,
574
575 /// key register 5
576 pub KEYR5: WORegister<u32>,
577
578 /// key register 6
579 pub KEYR6: WORegister<u32>,
580
581 /// key register 7
582 pub KEYR7: WORegister<u32>,
583
584 /// AES suspend register 0
585 pub SUSP0R: RWRegister<u32>,
586
587 /// AES suspend register 1
588 pub SUSP1R: RWRegister<u32>,
589
590 /// AES suspend register 2
591 pub SUSP2R: RWRegister<u32>,
592
593 /// AES suspend register 3
594 pub SUSP3R: RWRegister<u32>,
595
596 /// AES suspend register 4
597 pub SUSP4R: RWRegister<u32>,
598
599 /// AES suspend register 5
600 pub SUSP5R: RWRegister<u32>,
601
602 /// AES suspend register 6
603 pub SUSP6R: RWRegister<u32>,
604
605 /// AES suspend register 7
606 pub SUSP7R: RWRegister<u32>,
607}
608pub struct ResetValues {
609 pub CR: u32,
610 pub SR: u32,
611 pub DINR: u32,
612 pub DOUTR: u32,
613 pub KEYR0: u32,
614 pub KEYR1: u32,
615 pub KEYR2: u32,
616 pub KEYR3: u32,
617 pub IVR0: u32,
618 pub IVR1: u32,
619 pub IVR2: u32,
620 pub IVR3: u32,
621 pub KEYR4: u32,
622 pub KEYR5: u32,
623 pub KEYR6: u32,
624 pub KEYR7: u32,
625 pub SUSP0R: u32,
626 pub SUSP1R: u32,
627 pub SUSP2R: u32,
628 pub SUSP3R: u32,
629 pub SUSP4R: u32,
630 pub SUSP5R: u32,
631 pub SUSP6R: u32,
632 pub SUSP7R: u32,
633}
634#[cfg(not(feature = "nosync"))]
635pub struct Instance {
636 pub(crate) addr: u32,
637 pub(crate) _marker: PhantomData<*const RegisterBlock>,
638}
639#[cfg(not(feature = "nosync"))]
640impl ::core::ops::Deref for Instance {
641 type Target = RegisterBlock;
642 #[inline(always)]
643 fn deref(&self) -> &RegisterBlock {
644 unsafe { &*(self.addr as *const _) }
645 }
646}
647#[cfg(feature = "rtic")]
648unsafe impl Send for Instance {}
649
650/// Access functions for the AES peripheral instance
651pub mod AES {
652 use super::ResetValues;
653
654 #[cfg(not(feature = "nosync"))]
655 use super::Instance;
656
657 #[cfg(not(feature = "nosync"))]
658 const INSTANCE: Instance = Instance {
659 addr: 0x420c0000,
660 _marker: ::core::marker::PhantomData,
661 };
662
663 /// Reset values for each field in AES
664 pub const reset: ResetValues = ResetValues {
665 CR: 0x00000000,
666 SR: 0x00000000,
667 DINR: 0x00000000,
668 DOUTR: 0x00000000,
669 KEYR0: 0x00000000,
670 KEYR1: 0x00000000,
671 KEYR2: 0x00000000,
672 KEYR3: 0x00000000,
673 IVR0: 0x00000000,
674 IVR1: 0x00000000,
675 IVR2: 0x00000000,
676 IVR3: 0x00000000,
677 KEYR4: 0x00000000,
678 KEYR5: 0x00000000,
679 KEYR6: 0x00000000,
680 KEYR7: 0x00000000,
681 SUSP0R: 0x00000000,
682 SUSP1R: 0x00000000,
683 SUSP2R: 0x00000000,
684 SUSP3R: 0x00000000,
685 SUSP4R: 0x00000000,
686 SUSP5R: 0x00000000,
687 SUSP6R: 0x00000000,
688 SUSP7R: 0x00000000,
689 };
690
691 #[cfg(not(feature = "nosync"))]
692 #[allow(renamed_and_removed_lints)]
693 #[allow(private_no_mangle_statics)]
694 #[no_mangle]
695 static mut AES_TAKEN: bool = false;
696
697 /// Safe access to AES
698 ///
699 /// This function returns `Some(Instance)` if this instance is not
700 /// currently taken, and `None` if it is. This ensures that if you
701 /// do get `Some(Instance)`, you are ensured unique access to
702 /// the peripheral and there cannot be data races (unless other
703 /// code uses `unsafe`, of course). You can then pass the
704 /// `Instance` around to other functions as required. When you're
705 /// done with it, you can call `release(instance)` to return it.
706 ///
707 /// `Instance` itself dereferences to a `RegisterBlock`, which
708 /// provides access to the peripheral's registers.
709 #[cfg(not(feature = "nosync"))]
710 #[inline]
711 pub fn take() -> Option<Instance> {
712 external_cortex_m::interrupt::free(|_| unsafe {
713 if AES_TAKEN {
714 None
715 } else {
716 AES_TAKEN = true;
717 Some(INSTANCE)
718 }
719 })
720 }
721
722 /// Release exclusive access to AES
723 ///
724 /// This function allows you to return an `Instance` so that it
725 /// is available to `take()` again. This function will panic if
726 /// you return a different `Instance` or if this instance is not
727 /// already taken.
728 #[cfg(not(feature = "nosync"))]
729 #[inline]
730 pub fn release(inst: Instance) {
731 external_cortex_m::interrupt::free(|_| unsafe {
732 if AES_TAKEN && inst.addr == INSTANCE.addr {
733 AES_TAKEN = false;
734 } else {
735 panic!("Released a peripheral which was not taken");
736 }
737 });
738 }
739
740 /// Unsafely steal AES
741 ///
742 /// This function is similar to take() but forcibly takes the
743 /// Instance, marking it as taken irregardless of its previous
744 /// state.
745 #[cfg(not(feature = "nosync"))]
746 #[inline]
747 pub unsafe fn steal() -> Instance {
748 AES_TAKEN = true;
749 INSTANCE
750 }
751}
752
753/// Raw pointer to AES
754///
755/// Dereferencing this is unsafe because you are not ensured unique
756/// access to the peripheral, so you may encounter data races with
757/// other users of this peripheral. It is up to you to ensure you
758/// will not cause data races.
759///
760/// This constant is provided for ease of use in unsafe code: you can
761/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
762pub const AES: *const RegisterBlock = 0x420c0000 as *const _;
763
764/// Access functions for the SEC_AES peripheral instance
765pub mod SEC_AES {
766 use super::ResetValues;
767
768 #[cfg(not(feature = "nosync"))]
769 use super::Instance;
770
771 #[cfg(not(feature = "nosync"))]
772 const INSTANCE: Instance = Instance {
773 addr: 0x520c0000,
774 _marker: ::core::marker::PhantomData,
775 };
776
777 /// Reset values for each field in SEC_AES
778 pub const reset: ResetValues = ResetValues {
779 CR: 0x00000000,
780 SR: 0x00000000,
781 DINR: 0x00000000,
782 DOUTR: 0x00000000,
783 KEYR0: 0x00000000,
784 KEYR1: 0x00000000,
785 KEYR2: 0x00000000,
786 KEYR3: 0x00000000,
787 IVR0: 0x00000000,
788 IVR1: 0x00000000,
789 IVR2: 0x00000000,
790 IVR3: 0x00000000,
791 KEYR4: 0x00000000,
792 KEYR5: 0x00000000,
793 KEYR6: 0x00000000,
794 KEYR7: 0x00000000,
795 SUSP0R: 0x00000000,
796 SUSP1R: 0x00000000,
797 SUSP2R: 0x00000000,
798 SUSP3R: 0x00000000,
799 SUSP4R: 0x00000000,
800 SUSP5R: 0x00000000,
801 SUSP6R: 0x00000000,
802 SUSP7R: 0x00000000,
803 };
804
805 #[cfg(not(feature = "nosync"))]
806 #[allow(renamed_and_removed_lints)]
807 #[allow(private_no_mangle_statics)]
808 #[no_mangle]
809 static mut SEC_AES_TAKEN: bool = false;
810
811 /// Safe access to SEC_AES
812 ///
813 /// This function returns `Some(Instance)` if this instance is not
814 /// currently taken, and `None` if it is. This ensures that if you
815 /// do get `Some(Instance)`, you are ensured unique access to
816 /// the peripheral and there cannot be data races (unless other
817 /// code uses `unsafe`, of course). You can then pass the
818 /// `Instance` around to other functions as required. When you're
819 /// done with it, you can call `release(instance)` to return it.
820 ///
821 /// `Instance` itself dereferences to a `RegisterBlock`, which
822 /// provides access to the peripheral's registers.
823 #[cfg(not(feature = "nosync"))]
824 #[inline]
825 pub fn take() -> Option<Instance> {
826 external_cortex_m::interrupt::free(|_| unsafe {
827 if SEC_AES_TAKEN {
828 None
829 } else {
830 SEC_AES_TAKEN = true;
831 Some(INSTANCE)
832 }
833 })
834 }
835
836 /// Release exclusive access to SEC_AES
837 ///
838 /// This function allows you to return an `Instance` so that it
839 /// is available to `take()` again. This function will panic if
840 /// you return a different `Instance` or if this instance is not
841 /// already taken.
842 #[cfg(not(feature = "nosync"))]
843 #[inline]
844 pub fn release(inst: Instance) {
845 external_cortex_m::interrupt::free(|_| unsafe {
846 if SEC_AES_TAKEN && inst.addr == INSTANCE.addr {
847 SEC_AES_TAKEN = false;
848 } else {
849 panic!("Released a peripheral which was not taken");
850 }
851 });
852 }
853
854 /// Unsafely steal SEC_AES
855 ///
856 /// This function is similar to take() but forcibly takes the
857 /// Instance, marking it as taken irregardless of its previous
858 /// state.
859 #[cfg(not(feature = "nosync"))]
860 #[inline]
861 pub unsafe fn steal() -> Instance {
862 SEC_AES_TAKEN = true;
863 INSTANCE
864 }
865}
866
867/// Raw pointer to SEC_AES
868///
869/// Dereferencing this is unsafe because you are not ensured unique
870/// access to the peripheral, so you may encounter data races with
871/// other users of this peripheral. It is up to you to ensure you
872/// will not cause data races.
873///
874/// This constant is provided for ease of use in unsafe code: you can
875/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
876pub const SEC_AES: *const RegisterBlock = 0x520c0000 as *const _;