stm32ral/stm32l4/stm32l4x5/adc_common.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Analog-to-Digital Converter
4
5use crate::{RORegister, RWRegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// ADC Common status register
10pub mod CSR {
11
12 /// ADDRDY_MST
13 pub mod ADDRDY_MST {
14 /// Offset (0 bits)
15 pub const offset: u32 = 0;
16 /// Mask (1 bit: 1 << 0)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25
26 /// EOSMP_MST
27 pub mod EOSMP_MST {
28 /// Offset (1 bits)
29 pub const offset: u32 = 1;
30 /// Mask (1 bit: 1 << 1)
31 pub const mask: u32 = 1 << offset;
32 /// Read-only values (empty)
33 pub mod R {}
34 /// Write-only values (empty)
35 pub mod W {}
36 /// Read-write values (empty)
37 pub mod RW {}
38 }
39
40 /// EOC_MST
41 pub mod EOC_MST {
42 /// Offset (2 bits)
43 pub const offset: u32 = 2;
44 /// Mask (1 bit: 1 << 2)
45 pub const mask: u32 = 1 << offset;
46 /// Read-only values (empty)
47 pub mod R {}
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53
54 /// EOS_MST
55 pub mod EOS_MST {
56 /// Offset (3 bits)
57 pub const offset: u32 = 3;
58 /// Mask (1 bit: 1 << 3)
59 pub const mask: u32 = 1 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// OVR_MST
69 pub mod OVR_MST {
70 /// Offset (4 bits)
71 pub const offset: u32 = 4;
72 /// Mask (1 bit: 1 << 4)
73 pub const mask: u32 = 1 << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// JEOC_MST
83 pub mod JEOC_MST {
84 /// Offset (5 bits)
85 pub const offset: u32 = 5;
86 /// Mask (1 bit: 1 << 5)
87 pub const mask: u32 = 1 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 /// Read-write values (empty)
93 pub mod RW {}
94 }
95
96 /// JEOS_MST
97 pub mod JEOS_MST {
98 /// Offset (6 bits)
99 pub const offset: u32 = 6;
100 /// Mask (1 bit: 1 << 6)
101 pub const mask: u32 = 1 << offset;
102 /// Read-only values (empty)
103 pub mod R {}
104 /// Write-only values (empty)
105 pub mod W {}
106 /// Read-write values (empty)
107 pub mod RW {}
108 }
109
110 /// AWD1_MST
111 pub mod AWD1_MST {
112 /// Offset (7 bits)
113 pub const offset: u32 = 7;
114 /// Mask (1 bit: 1 << 7)
115 pub const mask: u32 = 1 << offset;
116 /// Read-only values (empty)
117 pub mod R {}
118 /// Write-only values (empty)
119 pub mod W {}
120 /// Read-write values (empty)
121 pub mod RW {}
122 }
123
124 /// AWD2_MST
125 pub mod AWD2_MST {
126 /// Offset (8 bits)
127 pub const offset: u32 = 8;
128 /// Mask (1 bit: 1 << 8)
129 pub const mask: u32 = 1 << offset;
130 /// Read-only values (empty)
131 pub mod R {}
132 /// Write-only values (empty)
133 pub mod W {}
134 /// Read-write values (empty)
135 pub mod RW {}
136 }
137
138 /// AWD3_MST
139 pub mod AWD3_MST {
140 /// Offset (9 bits)
141 pub const offset: u32 = 9;
142 /// Mask (1 bit: 1 << 9)
143 pub const mask: u32 = 1 << offset;
144 /// Read-only values (empty)
145 pub mod R {}
146 /// Write-only values (empty)
147 pub mod W {}
148 /// Read-write values (empty)
149 pub mod RW {}
150 }
151
152 /// JQOVF_MST
153 pub mod JQOVF_MST {
154 /// Offset (10 bits)
155 pub const offset: u32 = 10;
156 /// Mask (1 bit: 1 << 10)
157 pub const mask: u32 = 1 << offset;
158 /// Read-only values (empty)
159 pub mod R {}
160 /// Write-only values (empty)
161 pub mod W {}
162 /// Read-write values (empty)
163 pub mod RW {}
164 }
165
166 /// ADRDY_SLV
167 pub mod ADRDY_SLV {
168 /// Offset (16 bits)
169 pub const offset: u32 = 16;
170 /// Mask (1 bit: 1 << 16)
171 pub const mask: u32 = 1 << offset;
172 /// Read-only values (empty)
173 pub mod R {}
174 /// Write-only values (empty)
175 pub mod W {}
176 /// Read-write values (empty)
177 pub mod RW {}
178 }
179
180 /// EOSMP_SLV
181 pub mod EOSMP_SLV {
182 /// Offset (17 bits)
183 pub const offset: u32 = 17;
184 /// Mask (1 bit: 1 << 17)
185 pub const mask: u32 = 1 << offset;
186 /// Read-only values (empty)
187 pub mod R {}
188 /// Write-only values (empty)
189 pub mod W {}
190 /// Read-write values (empty)
191 pub mod RW {}
192 }
193
194 /// End of regular conversion of the slave ADC
195 pub mod EOC_SLV {
196 /// Offset (18 bits)
197 pub const offset: u32 = 18;
198 /// Mask (1 bit: 1 << 18)
199 pub const mask: u32 = 1 << offset;
200 /// Read-only values (empty)
201 pub mod R {}
202 /// Write-only values (empty)
203 pub mod W {}
204 /// Read-write values (empty)
205 pub mod RW {}
206 }
207
208 /// End of regular sequence flag of the slave ADC
209 pub mod EOS_SLV {
210 /// Offset (19 bits)
211 pub const offset: u32 = 19;
212 /// Mask (1 bit: 1 << 19)
213 pub const mask: u32 = 1 << offset;
214 /// Read-only values (empty)
215 pub mod R {}
216 /// Write-only values (empty)
217 pub mod W {}
218 /// Read-write values (empty)
219 pub mod RW {}
220 }
221
222 /// Overrun flag of the slave ADC
223 pub mod OVR_SLV {
224 /// Offset (20 bits)
225 pub const offset: u32 = 20;
226 /// Mask (1 bit: 1 << 20)
227 pub const mask: u32 = 1 << offset;
228 /// Read-only values (empty)
229 pub mod R {}
230 /// Write-only values (empty)
231 pub mod W {}
232 /// Read-write values (empty)
233 pub mod RW {}
234 }
235
236 /// End of injected conversion flag of the slave ADC
237 pub mod JEOC_SLV {
238 /// Offset (21 bits)
239 pub const offset: u32 = 21;
240 /// Mask (1 bit: 1 << 21)
241 pub const mask: u32 = 1 << offset;
242 /// Read-only values (empty)
243 pub mod R {}
244 /// Write-only values (empty)
245 pub mod W {}
246 /// Read-write values (empty)
247 pub mod RW {}
248 }
249
250 /// End of injected sequence flag of the slave ADC
251 pub mod JEOS_SLV {
252 /// Offset (22 bits)
253 pub const offset: u32 = 22;
254 /// Mask (1 bit: 1 << 22)
255 pub const mask: u32 = 1 << offset;
256 /// Read-only values (empty)
257 pub mod R {}
258 /// Write-only values (empty)
259 pub mod W {}
260 /// Read-write values (empty)
261 pub mod RW {}
262 }
263
264 /// Analog watchdog 1 flag of the slave ADC
265 pub mod AWD1_SLV {
266 /// Offset (23 bits)
267 pub const offset: u32 = 23;
268 /// Mask (1 bit: 1 << 23)
269 pub const mask: u32 = 1 << offset;
270 /// Read-only values (empty)
271 pub mod R {}
272 /// Write-only values (empty)
273 pub mod W {}
274 /// Read-write values (empty)
275 pub mod RW {}
276 }
277
278 /// Analog watchdog 2 flag of the slave ADC
279 pub mod AWD2_SLV {
280 /// Offset (24 bits)
281 pub const offset: u32 = 24;
282 /// Mask (1 bit: 1 << 24)
283 pub const mask: u32 = 1 << offset;
284 /// Read-only values (empty)
285 pub mod R {}
286 /// Write-only values (empty)
287 pub mod W {}
288 /// Read-write values (empty)
289 pub mod RW {}
290 }
291
292 /// Analog watchdog 3 flag of the slave ADC
293 pub mod AWD3_SLV {
294 /// Offset (25 bits)
295 pub const offset: u32 = 25;
296 /// Mask (1 bit: 1 << 25)
297 pub const mask: u32 = 1 << offset;
298 /// Read-only values (empty)
299 pub mod R {}
300 /// Write-only values (empty)
301 pub mod W {}
302 /// Read-write values (empty)
303 pub mod RW {}
304 }
305
306 /// Injected Context Queue Overflow flag of the slave ADC
307 pub mod JQOVF_SLV {
308 /// Offset (26 bits)
309 pub const offset: u32 = 26;
310 /// Mask (1 bit: 1 << 26)
311 pub const mask: u32 = 1 << offset;
312 /// Read-only values (empty)
313 pub mod R {}
314 /// Write-only values (empty)
315 pub mod W {}
316 /// Read-write values (empty)
317 pub mod RW {}
318 }
319}
320
321/// ADC common control register
322pub mod CCR {
323
324 /// Dual ADC mode selection
325 pub mod DUAL {
326 /// Offset (0 bits)
327 pub const offset: u32 = 0;
328 /// Mask (5 bits: 0b11111 << 0)
329 pub const mask: u32 = 0b11111 << offset;
330 /// Read-only values (empty)
331 pub mod R {}
332 /// Write-only values (empty)
333 pub mod W {}
334 /// Read-write values (empty)
335 pub mod RW {}
336 }
337
338 /// Delay between 2 sampling phases
339 pub mod DELAY {
340 /// Offset (8 bits)
341 pub const offset: u32 = 8;
342 /// Mask (4 bits: 0b1111 << 8)
343 pub const mask: u32 = 0b1111 << offset;
344 /// Read-only values (empty)
345 pub mod R {}
346 /// Write-only values (empty)
347 pub mod W {}
348 /// Read-write values (empty)
349 pub mod RW {}
350 }
351
352 /// DMA configuration (for multi-ADC mode)
353 pub mod DMACFG {
354 /// Offset (13 bits)
355 pub const offset: u32 = 13;
356 /// Mask (1 bit: 1 << 13)
357 pub const mask: u32 = 1 << offset;
358 /// Read-only values (empty)
359 pub mod R {}
360 /// Write-only values (empty)
361 pub mod W {}
362 /// Read-write values (empty)
363 pub mod RW {}
364 }
365
366 /// Direct memory access mode for multi ADC mode
367 pub mod MDMA {
368 /// Offset (14 bits)
369 pub const offset: u32 = 14;
370 /// Mask (2 bits: 0b11 << 14)
371 pub const mask: u32 = 0b11 << offset;
372 /// Read-only values (empty)
373 pub mod R {}
374 /// Write-only values (empty)
375 pub mod W {}
376 /// Read-write values (empty)
377 pub mod RW {}
378 }
379
380 /// ADC clock mode
381 pub mod CKMODE {
382 /// Offset (16 bits)
383 pub const offset: u32 = 16;
384 /// Mask (2 bits: 0b11 << 16)
385 pub const mask: u32 = 0b11 << offset;
386 /// Read-only values (empty)
387 pub mod R {}
388 /// Write-only values (empty)
389 pub mod W {}
390 /// Read-write values (empty)
391 pub mod RW {}
392 }
393
394 /// VREFINT enable
395 pub mod VREFEN {
396 /// Offset (22 bits)
397 pub const offset: u32 = 22;
398 /// Mask (1 bit: 1 << 22)
399 pub const mask: u32 = 1 << offset;
400 /// Read-only values (empty)
401 pub mod R {}
402 /// Write-only values (empty)
403 pub mod W {}
404 /// Read-write values (empty)
405 pub mod RW {}
406 }
407
408 /// CH18 selection (Vbat)
409 pub mod CH18SEL {
410 /// Offset (23 bits)
411 pub const offset: u32 = 23;
412 /// Mask (1 bit: 1 << 23)
413 pub const mask: u32 = 1 << offset;
414 /// Read-only values (empty)
415 pub mod R {}
416 /// Write-only values (empty)
417 pub mod W {}
418 /// Read-write values (empty)
419 pub mod RW {}
420 }
421
422 /// CH17 selection (temperature)
423 pub mod CH17SEL {
424 /// Offset (24 bits)
425 pub const offset: u32 = 24;
426 /// Mask (1 bit: 1 << 24)
427 pub const mask: u32 = 1 << offset;
428 /// Read-only values (empty)
429 pub mod R {}
430 /// Write-only values (empty)
431 pub mod W {}
432 /// Read-write values (empty)
433 pub mod RW {}
434 }
435
436 /// ADC prescaler
437 pub mod PRESC {
438 /// Offset (18 bits)
439 pub const offset: u32 = 18;
440 /// Mask (4 bits: 0b1111 << 18)
441 pub const mask: u32 = 0b1111 << offset;
442 /// Read-only values (empty)
443 pub mod R {}
444 /// Write-only values (empty)
445 pub mod W {}
446 /// Read-write values (empty)
447 pub mod RW {}
448 }
449}
450
451/// ADC common regular data register for dual and triple modes
452pub mod CDR {
453
454 /// Regular data of the slave ADC
455 pub mod RDATA_SLV {
456 /// Offset (16 bits)
457 pub const offset: u32 = 16;
458 /// Mask (16 bits: 0xffff << 16)
459 pub const mask: u32 = 0xffff << offset;
460 /// Read-only values (empty)
461 pub mod R {}
462 /// Write-only values (empty)
463 pub mod W {}
464 /// Read-write values (empty)
465 pub mod RW {}
466 }
467
468 /// Regular data of the master ADC
469 pub mod RDATA_MST {
470 /// Offset (0 bits)
471 pub const offset: u32 = 0;
472 /// Mask (16 bits: 0xffff << 0)
473 pub const mask: u32 = 0xffff << offset;
474 /// Read-only values (empty)
475 pub mod R {}
476 /// Write-only values (empty)
477 pub mod W {}
478 /// Read-write values (empty)
479 pub mod RW {}
480 }
481}
482#[repr(C)]
483pub struct RegisterBlock {
484 /// ADC Common status register
485 pub CSR: RORegister<u32>,
486
487 _reserved1: [u8; 4],
488
489 /// ADC common control register
490 pub CCR: RWRegister<u32>,
491
492 /// ADC common regular data register for dual and triple modes
493 pub CDR: RORegister<u32>,
494}
495pub struct ResetValues {
496 pub CSR: u32,
497 pub CCR: u32,
498 pub CDR: u32,
499}
500#[cfg(not(feature = "nosync"))]
501pub struct Instance {
502 pub(crate) addr: u32,
503 pub(crate) _marker: PhantomData<*const RegisterBlock>,
504}
505#[cfg(not(feature = "nosync"))]
506impl ::core::ops::Deref for Instance {
507 type Target = RegisterBlock;
508 #[inline(always)]
509 fn deref(&self) -> &RegisterBlock {
510 unsafe { &*(self.addr as *const _) }
511 }
512}
513#[cfg(feature = "rtic")]
514unsafe impl Send for Instance {}
515
516/// Access functions for the ADC_Common peripheral instance
517pub mod ADC_Common {
518 use super::ResetValues;
519
520 #[cfg(not(feature = "nosync"))]
521 use super::Instance;
522
523 #[cfg(not(feature = "nosync"))]
524 const INSTANCE: Instance = Instance {
525 addr: 0x50040300,
526 _marker: ::core::marker::PhantomData,
527 };
528
529 /// Reset values for each field in ADC_Common
530 pub const reset: ResetValues = ResetValues {
531 CSR: 0x00000000,
532 CCR: 0x00000000,
533 CDR: 0x00000000,
534 };
535
536 #[cfg(not(feature = "nosync"))]
537 #[allow(renamed_and_removed_lints)]
538 #[allow(private_no_mangle_statics)]
539 #[no_mangle]
540 static mut ADC_Common_TAKEN: bool = false;
541
542 /// Safe access to ADC_Common
543 ///
544 /// This function returns `Some(Instance)` if this instance is not
545 /// currently taken, and `None` if it is. This ensures that if you
546 /// do get `Some(Instance)`, you are ensured unique access to
547 /// the peripheral and there cannot be data races (unless other
548 /// code uses `unsafe`, of course). You can then pass the
549 /// `Instance` around to other functions as required. When you're
550 /// done with it, you can call `release(instance)` to return it.
551 ///
552 /// `Instance` itself dereferences to a `RegisterBlock`, which
553 /// provides access to the peripheral's registers.
554 #[cfg(not(feature = "nosync"))]
555 #[inline]
556 pub fn take() -> Option<Instance> {
557 external_cortex_m::interrupt::free(|_| unsafe {
558 if ADC_Common_TAKEN {
559 None
560 } else {
561 ADC_Common_TAKEN = true;
562 Some(INSTANCE)
563 }
564 })
565 }
566
567 /// Release exclusive access to ADC_Common
568 ///
569 /// This function allows you to return an `Instance` so that it
570 /// is available to `take()` again. This function will panic if
571 /// you return a different `Instance` or if this instance is not
572 /// already taken.
573 #[cfg(not(feature = "nosync"))]
574 #[inline]
575 pub fn release(inst: Instance) {
576 external_cortex_m::interrupt::free(|_| unsafe {
577 if ADC_Common_TAKEN && inst.addr == INSTANCE.addr {
578 ADC_Common_TAKEN = false;
579 } else {
580 panic!("Released a peripheral which was not taken");
581 }
582 });
583 }
584
585 /// Unsafely steal ADC_Common
586 ///
587 /// This function is similar to take() but forcibly takes the
588 /// Instance, marking it as taken irregardless of its previous
589 /// state.
590 #[cfg(not(feature = "nosync"))]
591 #[inline]
592 pub unsafe fn steal() -> Instance {
593 ADC_Common_TAKEN = true;
594 INSTANCE
595 }
596}
597
598/// Raw pointer to ADC_Common
599///
600/// Dereferencing this is unsafe because you are not ensured unique
601/// access to the peripheral, so you may encounter data races with
602/// other users of this peripheral. It is up to you to ensure you
603/// will not cause data races.
604///
605/// This constant is provided for ease of use in unsafe code: you can
606/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
607pub const ADC_Common: *const RegisterBlock = 0x50040300 as *const _;