stm32ral/stm32l4/peripherals/tim8.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Advanced-timers
4//!
5//! Used by: stm32l4r9, stm32l4x5, stm32l4x6
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Clock division
15 pub mod CKD {
16 /// Offset (8 bits)
17 pub const offset: u32 = 8;
18 /// Mask (2 bits: 0b11 << 8)
19 pub const mask: u32 = 0b11 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b00: t_DTS = t_CK_INT
28 pub const Div1: u32 = 0b00;
29
30 /// 0b01: t_DTS = 2 × t_CK_INT
31 pub const Div2: u32 = 0b01;
32
33 /// 0b10: t_DTS = 4 × t_CK_INT
34 pub const Div4: u32 = 0b10;
35 }
36 }
37
38 /// Auto-reload preload enable
39 pub mod ARPE {
40 /// Offset (7 bits)
41 pub const offset: u32 = 7;
42 /// Mask (1 bit: 1 << 7)
43 pub const mask: u32 = 1 << offset;
44 /// Read-only values (empty)
45 pub mod R {}
46 /// Write-only values (empty)
47 pub mod W {}
48 /// Read-write values
49 pub mod RW {
50
51 /// 0b0: TIMx_APRR register is not buffered
52 pub const Disabled: u32 = 0b0;
53
54 /// 0b1: TIMx_APRR register is buffered
55 pub const Enabled: u32 = 0b1;
56 }
57 }
58
59 /// Center-aligned mode selection
60 pub mod CMS {
61 /// Offset (5 bits)
62 pub const offset: u32 = 5;
63 /// Mask (2 bits: 0b11 << 5)
64 pub const mask: u32 = 0b11 << offset;
65 /// Read-only values (empty)
66 pub mod R {}
67 /// Write-only values (empty)
68 pub mod W {}
69 /// Read-write values
70 pub mod RW {
71
72 /// 0b00: The counter counts up or down depending on the direction bit
73 pub const EdgeAligned: u32 = 0b00;
74
75 /// 0b01: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
76 pub const CenterAligned1: u32 = 0b01;
77
78 /// 0b10: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
79 pub const CenterAligned2: u32 = 0b10;
80
81 /// 0b11: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
82 pub const CenterAligned3: u32 = 0b11;
83 }
84 }
85
86 /// Direction
87 pub mod DIR {
88 /// Offset (4 bits)
89 pub const offset: u32 = 4;
90 /// Mask (1 bit: 1 << 4)
91 pub const mask: u32 = 1 << offset;
92 /// Read-only values (empty)
93 pub mod R {}
94 /// Write-only values (empty)
95 pub mod W {}
96 /// Read-write values
97 pub mod RW {
98
99 /// 0b0: Counter used as upcounter
100 pub const Up: u32 = 0b0;
101
102 /// 0b1: Counter used as downcounter
103 pub const Down: u32 = 0b1;
104 }
105 }
106
107 /// One-pulse mode
108 pub mod OPM {
109 /// Offset (3 bits)
110 pub const offset: u32 = 3;
111 /// Mask (1 bit: 1 << 3)
112 pub const mask: u32 = 1 << offset;
113 /// Read-only values (empty)
114 pub mod R {}
115 /// Write-only values (empty)
116 pub mod W {}
117 /// Read-write values
118 pub mod RW {
119
120 /// 0b0: Counter is not stopped at update event
121 pub const Disabled: u32 = 0b0;
122
123 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
124 pub const Enabled: u32 = 0b1;
125 }
126 }
127
128 /// Update request source
129 pub mod URS {
130 /// Offset (2 bits)
131 pub const offset: u32 = 2;
132 /// Mask (1 bit: 1 << 2)
133 pub const mask: u32 = 1 << offset;
134 /// Read-only values (empty)
135 pub mod R {}
136 /// Write-only values (empty)
137 pub mod W {}
138 /// Read-write values
139 pub mod RW {
140
141 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
142 pub const AnyEvent: u32 = 0b0;
143
144 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
145 pub const CounterOnly: u32 = 0b1;
146 }
147 }
148
149 /// Update disable
150 pub mod UDIS {
151 /// Offset (1 bits)
152 pub const offset: u32 = 1;
153 /// Mask (1 bit: 1 << 1)
154 pub const mask: u32 = 1 << offset;
155 /// Read-only values (empty)
156 pub mod R {}
157 /// Write-only values (empty)
158 pub mod W {}
159 /// Read-write values
160 pub mod RW {
161
162 /// 0b0: Update event enabled
163 pub const Enabled: u32 = 0b0;
164
165 /// 0b1: Update event disabled
166 pub const Disabled: u32 = 0b1;
167 }
168 }
169
170 /// Counter enable
171 pub mod CEN {
172 /// Offset (0 bits)
173 pub const offset: u32 = 0;
174 /// Mask (1 bit: 1 << 0)
175 pub const mask: u32 = 1 << offset;
176 /// Read-only values (empty)
177 pub mod R {}
178 /// Write-only values (empty)
179 pub mod W {}
180 /// Read-write values
181 pub mod RW {
182
183 /// 0b0: Counter disabled
184 pub const Disabled: u32 = 0b0;
185
186 /// 0b1: Counter enabled
187 pub const Enabled: u32 = 0b1;
188 }
189 }
190}
191
192/// control register 2
193pub mod CR2 {
194
195 /// Output Idle state 4
196 pub mod OIS4 {
197 /// Offset (14 bits)
198 pub const offset: u32 = 14;
199 /// Mask (1 bit: 1 << 14)
200 pub const mask: u32 = 1 << offset;
201 /// Read-only values (empty)
202 pub mod R {}
203 /// Write-only values (empty)
204 pub mod W {}
205 /// Read-write values (empty)
206 pub mod RW {}
207 }
208
209 /// Output Idle state 3
210 pub mod OIS3N {
211 /// Offset (13 bits)
212 pub const offset: u32 = 13;
213 /// Mask (1 bit: 1 << 13)
214 pub const mask: u32 = 1 << offset;
215 /// Read-only values (empty)
216 pub mod R {}
217 /// Write-only values (empty)
218 pub mod W {}
219 /// Read-write values (empty)
220 pub mod RW {}
221 }
222
223 /// Output Idle state 3
224 pub mod OIS3 {
225 /// Offset (12 bits)
226 pub const offset: u32 = 12;
227 /// Mask (1 bit: 1 << 12)
228 pub const mask: u32 = 1 << offset;
229 /// Read-only values (empty)
230 pub mod R {}
231 /// Write-only values (empty)
232 pub mod W {}
233 /// Read-write values (empty)
234 pub mod RW {}
235 }
236
237 /// Output Idle state 2
238 pub mod OIS2N {
239 /// Offset (11 bits)
240 pub const offset: u32 = 11;
241 /// Mask (1 bit: 1 << 11)
242 pub const mask: u32 = 1 << offset;
243 /// Read-only values (empty)
244 pub mod R {}
245 /// Write-only values (empty)
246 pub mod W {}
247 /// Read-write values (empty)
248 pub mod RW {}
249 }
250
251 /// Output Idle state 2
252 pub mod OIS2 {
253 /// Offset (10 bits)
254 pub const offset: u32 = 10;
255 /// Mask (1 bit: 1 << 10)
256 pub const mask: u32 = 1 << offset;
257 /// Read-only values (empty)
258 pub mod R {}
259 /// Write-only values (empty)
260 pub mod W {}
261 /// Read-write values (empty)
262 pub mod RW {}
263 }
264
265 /// Output Idle state 1
266 pub mod OIS1N {
267 /// Offset (9 bits)
268 pub const offset: u32 = 9;
269 /// Mask (1 bit: 1 << 9)
270 pub const mask: u32 = 1 << offset;
271 /// Read-only values (empty)
272 pub mod R {}
273 /// Write-only values (empty)
274 pub mod W {}
275 /// Read-write values (empty)
276 pub mod RW {}
277 }
278
279 /// Output Idle state 1
280 pub mod OIS1 {
281 /// Offset (8 bits)
282 pub const offset: u32 = 8;
283 /// Mask (1 bit: 1 << 8)
284 pub const mask: u32 = 1 << offset;
285 /// Read-only values (empty)
286 pub mod R {}
287 /// Write-only values (empty)
288 pub mod W {}
289 /// Read-write values (empty)
290 pub mod RW {}
291 }
292
293 /// TI1 selection
294 pub mod TI1S {
295 /// Offset (7 bits)
296 pub const offset: u32 = 7;
297 /// Mask (1 bit: 1 << 7)
298 pub const mask: u32 = 1 << offset;
299 /// Read-only values (empty)
300 pub mod R {}
301 /// Write-only values (empty)
302 pub mod W {}
303 /// Read-write values
304 pub mod RW {
305
306 /// 0b0: The TIMx_CH1 pin is connected to TI1 input
307 pub const Normal: u32 = 0b0;
308
309 /// 0b1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
310 pub const XOR: u32 = 0b1;
311 }
312 }
313
314 /// Master mode selection
315 pub mod MMS {
316 /// Offset (4 bits)
317 pub const offset: u32 = 4;
318 /// Mask (3 bits: 0b111 << 4)
319 pub const mask: u32 = 0b111 << offset;
320 /// Read-only values (empty)
321 pub mod R {}
322 /// Write-only values (empty)
323 pub mod W {}
324 /// Read-write values
325 pub mod RW {
326
327 /// 0b000: The UG bit from the TIMx_EGR register is used as trigger output
328 pub const Reset: u32 = 0b000;
329
330 /// 0b001: The counter enable signal, CNT_EN, is used as trigger output
331 pub const Enable: u32 = 0b001;
332
333 /// 0b010: The update event is selected as trigger output
334 pub const Update: u32 = 0b010;
335
336 /// 0b011: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
337 pub const ComparePulse: u32 = 0b011;
338
339 /// 0b100: OC1REF signal is used as trigger output
340 pub const CompareOC1: u32 = 0b100;
341
342 /// 0b101: OC2REF signal is used as trigger output
343 pub const CompareOC2: u32 = 0b101;
344
345 /// 0b110: OC3REF signal is used as trigger output
346 pub const CompareOC3: u32 = 0b110;
347
348 /// 0b111: OC4REF signal is used as trigger output
349 pub const CompareOC4: u32 = 0b111;
350 }
351 }
352
353 /// Capture/compare DMA selection
354 pub mod CCDS {
355 /// Offset (3 bits)
356 pub const offset: u32 = 3;
357 /// Mask (1 bit: 1 << 3)
358 pub const mask: u32 = 1 << offset;
359 /// Read-only values (empty)
360 pub mod R {}
361 /// Write-only values (empty)
362 pub mod W {}
363 /// Read-write values
364 pub mod RW {
365
366 /// 0b0: CCx DMA request sent when CCx event occurs
367 pub const OnCompare: u32 = 0b0;
368
369 /// 0b1: CCx DMA request sent when update event occurs
370 pub const OnUpdate: u32 = 0b1;
371 }
372 }
373
374 /// Capture/compare control update selection
375 pub mod CCUS {
376 /// Offset (2 bits)
377 pub const offset: u32 = 2;
378 /// Mask (1 bit: 1 << 2)
379 pub const mask: u32 = 1 << offset;
380 /// Read-only values (empty)
381 pub mod R {}
382 /// Write-only values (empty)
383 pub mod W {}
384 /// Read-write values (empty)
385 pub mod RW {}
386 }
387
388 /// Capture/compare preloaded control
389 pub mod CCPC {
390 /// Offset (0 bits)
391 pub const offset: u32 = 0;
392 /// Mask (1 bit: 1 << 0)
393 pub const mask: u32 = 1 << offset;
394 /// Read-only values (empty)
395 pub mod R {}
396 /// Write-only values (empty)
397 pub mod W {}
398 /// Read-write values (empty)
399 pub mod RW {}
400 }
401}
402
403/// slave mode control register
404pub mod SMCR {
405
406 /// External trigger polarity
407 pub mod ETP {
408 /// Offset (15 bits)
409 pub const offset: u32 = 15;
410 /// Mask (1 bit: 1 << 15)
411 pub const mask: u32 = 1 << offset;
412 /// Read-only values (empty)
413 pub mod R {}
414 /// Write-only values (empty)
415 pub mod W {}
416 /// Read-write values
417 pub mod RW {
418
419 /// 0b0: ETR is noninverted, active at high level or rising edge
420 pub const NotInverted: u32 = 0b0;
421
422 /// 0b1: ETR is inverted, active at low level or falling edge
423 pub const Inverted: u32 = 0b1;
424 }
425 }
426
427 /// External clock enable
428 pub mod ECE {
429 /// Offset (14 bits)
430 pub const offset: u32 = 14;
431 /// Mask (1 bit: 1 << 14)
432 pub const mask: u32 = 1 << offset;
433 /// Read-only values (empty)
434 pub mod R {}
435 /// Write-only values (empty)
436 pub mod W {}
437 /// Read-write values
438 pub mod RW {
439
440 /// 0b0: External clock mode 2 disabled
441 pub const Disabled: u32 = 0b0;
442
443 /// 0b1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
444 pub const Enabled: u32 = 0b1;
445 }
446 }
447
448 /// External trigger prescaler
449 pub mod ETPS {
450 /// Offset (12 bits)
451 pub const offset: u32 = 12;
452 /// Mask (2 bits: 0b11 << 12)
453 pub const mask: u32 = 0b11 << offset;
454 /// Read-only values (empty)
455 pub mod R {}
456 /// Write-only values (empty)
457 pub mod W {}
458 /// Read-write values
459 pub mod RW {
460
461 /// 0b00: Prescaler OFF
462 pub const Div1: u32 = 0b00;
463
464 /// 0b01: ETRP frequency divided by 2
465 pub const Div2: u32 = 0b01;
466
467 /// 0b10: ETRP frequency divided by 4
468 pub const Div4: u32 = 0b10;
469
470 /// 0b11: ETRP frequency divided by 8
471 pub const Div8: u32 = 0b11;
472 }
473 }
474
475 /// External trigger filter
476 pub mod ETF {
477 /// Offset (8 bits)
478 pub const offset: u32 = 8;
479 /// Mask (4 bits: 0b1111 << 8)
480 pub const mask: u32 = 0b1111 << offset;
481 /// Read-only values (empty)
482 pub mod R {}
483 /// Write-only values (empty)
484 pub mod W {}
485 /// Read-write values
486 pub mod RW {
487
488 /// 0b0000: No filter, sampling is done at fDTS
489 pub const NoFilter: u32 = 0b0000;
490
491 /// 0b0001: fSAMPLING=fCK_INT, N=2
492 pub const FCK_INT_N2: u32 = 0b0001;
493
494 /// 0b0010: fSAMPLING=fCK_INT, N=4
495 pub const FCK_INT_N4: u32 = 0b0010;
496
497 /// 0b0011: fSAMPLING=fCK_INT, N=8
498 pub const FCK_INT_N8: u32 = 0b0011;
499
500 /// 0b0100: fSAMPLING=fDTS/2, N=6
501 pub const FDTS_Div2_N6: u32 = 0b0100;
502
503 /// 0b0101: fSAMPLING=fDTS/2, N=8
504 pub const FDTS_Div2_N8: u32 = 0b0101;
505
506 /// 0b0110: fSAMPLING=fDTS/4, N=6
507 pub const FDTS_Div4_N6: u32 = 0b0110;
508
509 /// 0b0111: fSAMPLING=fDTS/4, N=8
510 pub const FDTS_Div4_N8: u32 = 0b0111;
511
512 /// 0b1000: fSAMPLING=fDTS/8, N=6
513 pub const FDTS_Div8_N6: u32 = 0b1000;
514
515 /// 0b1001: fSAMPLING=fDTS/8, N=8
516 pub const FDTS_Div8_N8: u32 = 0b1001;
517
518 /// 0b1010: fSAMPLING=fDTS/16, N=5
519 pub const FDTS_Div16_N5: u32 = 0b1010;
520
521 /// 0b1011: fSAMPLING=fDTS/16, N=6
522 pub const FDTS_Div16_N6: u32 = 0b1011;
523
524 /// 0b1100: fSAMPLING=fDTS/16, N=8
525 pub const FDTS_Div16_N8: u32 = 0b1100;
526
527 /// 0b1101: fSAMPLING=fDTS/32, N=5
528 pub const FDTS_Div32_N5: u32 = 0b1101;
529
530 /// 0b1110: fSAMPLING=fDTS/32, N=6
531 pub const FDTS_Div32_N6: u32 = 0b1110;
532
533 /// 0b1111: fSAMPLING=fDTS/32, N=8
534 pub const FDTS_Div32_N8: u32 = 0b1111;
535 }
536 }
537
538 /// Master/Slave mode
539 pub mod MSM {
540 /// Offset (7 bits)
541 pub const offset: u32 = 7;
542 /// Mask (1 bit: 1 << 7)
543 pub const mask: u32 = 1 << offset;
544 /// Read-only values (empty)
545 pub mod R {}
546 /// Write-only values (empty)
547 pub mod W {}
548 /// Read-write values
549 pub mod RW {
550
551 /// 0b0: No action
552 pub const NoSync: u32 = 0b0;
553
554 /// 0b1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
555 pub const Sync: u32 = 0b1;
556 }
557 }
558
559 /// Trigger selection
560 pub mod TS {
561 /// Offset (4 bits)
562 pub const offset: u32 = 4;
563 /// Mask (3 bits: 0b111 << 4)
564 pub const mask: u32 = 0b111 << offset;
565 /// Read-only values (empty)
566 pub mod R {}
567 /// Write-only values (empty)
568 pub mod W {}
569 /// Read-write values
570 pub mod RW {
571
572 /// 0b000: Internal Trigger 0 (ITR0)
573 pub const ITR0: u32 = 0b000;
574
575 /// 0b001: Internal Trigger 1 (ITR1)
576 pub const ITR1: u32 = 0b001;
577
578 /// 0b010: Internal Trigger 2 (ITR2)
579 pub const ITR2: u32 = 0b010;
580
581 /// 0b100: TI1 Edge Detector (TI1F_ED)
582 pub const TI1F_ED: u32 = 0b100;
583
584 /// 0b101: Filtered Timer Input 1 (TI1FP1)
585 pub const TI1FP1: u32 = 0b101;
586
587 /// 0b110: Filtered Timer Input 2 (TI2FP2)
588 pub const TI2FP2: u32 = 0b110;
589
590 /// 0b111: External Trigger input (ETRF)
591 pub const ETRF: u32 = 0b111;
592 }
593 }
594
595 /// Slave mode selection
596 pub mod SMS {
597 /// Offset (0 bits)
598 pub const offset: u32 = 0;
599 /// Mask (3 bits: 0b111 << 0)
600 pub const mask: u32 = 0b111 << offset;
601 /// Read-only values (empty)
602 pub mod R {}
603 /// Write-only values (empty)
604 pub mod W {}
605 /// Read-write values
606 pub mod RW {
607
608 /// 0b000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
609 pub const Disabled: u32 = 0b000;
610
611 /// 0b001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
612 pub const Encoder_Mode_1: u32 = 0b001;
613
614 /// 0b010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
615 pub const Encoder_Mode_2: u32 = 0b010;
616
617 /// 0b011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
618 pub const Encoder_Mode_3: u32 = 0b011;
619
620 /// 0b100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
621 pub const Reset_Mode: u32 = 0b100;
622
623 /// 0b101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
624 pub const Gated_Mode: u32 = 0b101;
625
626 /// 0b110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
627 pub const Trigger_Mode: u32 = 0b110;
628
629 /// 0b111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
630 pub const Ext_Clock_Mode: u32 = 0b111;
631 }
632 }
633}
634
635/// DMA/Interrupt enable register
636pub mod DIER {
637
638 /// Trigger DMA request enable
639 pub mod TDE {
640 /// Offset (14 bits)
641 pub const offset: u32 = 14;
642 /// Mask (1 bit: 1 << 14)
643 pub const mask: u32 = 1 << offset;
644 /// Read-only values (empty)
645 pub mod R {}
646 /// Write-only values (empty)
647 pub mod W {}
648 /// Read-write values
649 pub mod RW {
650
651 /// 0b0: Trigger DMA request disabled
652 pub const Disabled: u32 = 0b0;
653
654 /// 0b1: Trigger DMA request enabled
655 pub const Enabled: u32 = 0b1;
656 }
657 }
658
659 /// COM DMA request enable
660 pub mod COMDE {
661 /// Offset (13 bits)
662 pub const offset: u32 = 13;
663 /// Mask (1 bit: 1 << 13)
664 pub const mask: u32 = 1 << offset;
665 /// Read-only values (empty)
666 pub mod R {}
667 /// Write-only values (empty)
668 pub mod W {}
669 /// Read-write values (empty)
670 pub mod RW {}
671 }
672
673 /// Capture/Compare 4 DMA request enable
674 pub mod CC4DE {
675 /// Offset (12 bits)
676 pub const offset: u32 = 12;
677 /// Mask (1 bit: 1 << 12)
678 pub const mask: u32 = 1 << offset;
679 /// Read-only values (empty)
680 pub mod R {}
681 /// Write-only values (empty)
682 pub mod W {}
683 /// Read-write values
684 pub mod RW {
685
686 /// 0b0: CCx DMA request disabled
687 pub const Disabled: u32 = 0b0;
688
689 /// 0b1: CCx DMA request enabled
690 pub const Enabled: u32 = 0b1;
691 }
692 }
693
694 /// Capture/Compare 3 DMA request enable
695 pub mod CC3DE {
696 /// Offset (11 bits)
697 pub const offset: u32 = 11;
698 /// Mask (1 bit: 1 << 11)
699 pub const mask: u32 = 1 << offset;
700 /// Read-only values (empty)
701 pub mod R {}
702 /// Write-only values (empty)
703 pub mod W {}
704 pub use super::CC4DE::RW;
705 }
706
707 /// Capture/Compare 2 DMA request enable
708 pub mod CC2DE {
709 /// Offset (10 bits)
710 pub const offset: u32 = 10;
711 /// Mask (1 bit: 1 << 10)
712 pub const mask: u32 = 1 << offset;
713 /// Read-only values (empty)
714 pub mod R {}
715 /// Write-only values (empty)
716 pub mod W {}
717 pub use super::CC4DE::RW;
718 }
719
720 /// Capture/Compare 1 DMA request enable
721 pub mod CC1DE {
722 /// Offset (9 bits)
723 pub const offset: u32 = 9;
724 /// Mask (1 bit: 1 << 9)
725 pub const mask: u32 = 1 << offset;
726 /// Read-only values (empty)
727 pub mod R {}
728 /// Write-only values (empty)
729 pub mod W {}
730 pub use super::CC4DE::RW;
731 }
732
733 /// Update DMA request enable
734 pub mod UDE {
735 /// Offset (8 bits)
736 pub const offset: u32 = 8;
737 /// Mask (1 bit: 1 << 8)
738 pub const mask: u32 = 1 << offset;
739 /// Read-only values (empty)
740 pub mod R {}
741 /// Write-only values (empty)
742 pub mod W {}
743 /// Read-write values
744 pub mod RW {
745
746 /// 0b0: Update DMA request disabled
747 pub const Disabled: u32 = 0b0;
748
749 /// 0b1: Update DMA request enabled
750 pub const Enabled: u32 = 0b1;
751 }
752 }
753
754 /// Trigger interrupt enable
755 pub mod TIE {
756 /// Offset (6 bits)
757 pub const offset: u32 = 6;
758 /// Mask (1 bit: 1 << 6)
759 pub const mask: u32 = 1 << offset;
760 /// Read-only values (empty)
761 pub mod R {}
762 /// Write-only values (empty)
763 pub mod W {}
764 /// Read-write values
765 pub mod RW {
766
767 /// 0b0: Trigger interrupt disabled
768 pub const Disabled: u32 = 0b0;
769
770 /// 0b1: Trigger interrupt enabled
771 pub const Enabled: u32 = 0b1;
772 }
773 }
774
775 /// Capture/Compare 4 interrupt enable
776 pub mod CC4IE {
777 /// Offset (4 bits)
778 pub const offset: u32 = 4;
779 /// Mask (1 bit: 1 << 4)
780 pub const mask: u32 = 1 << offset;
781 /// Read-only values (empty)
782 pub mod R {}
783 /// Write-only values (empty)
784 pub mod W {}
785 /// Read-write values
786 pub mod RW {
787
788 /// 0b0: CCx interrupt disabled
789 pub const Disabled: u32 = 0b0;
790
791 /// 0b1: CCx interrupt enabled
792 pub const Enabled: u32 = 0b1;
793 }
794 }
795
796 /// Capture/Compare 3 interrupt enable
797 pub mod CC3IE {
798 /// Offset (3 bits)
799 pub const offset: u32 = 3;
800 /// Mask (1 bit: 1 << 3)
801 pub const mask: u32 = 1 << offset;
802 /// Read-only values (empty)
803 pub mod R {}
804 /// Write-only values (empty)
805 pub mod W {}
806 pub use super::CC4IE::RW;
807 }
808
809 /// Capture/Compare 2 interrupt enable
810 pub mod CC2IE {
811 /// Offset (2 bits)
812 pub const offset: u32 = 2;
813 /// Mask (1 bit: 1 << 2)
814 pub const mask: u32 = 1 << offset;
815 /// Read-only values (empty)
816 pub mod R {}
817 /// Write-only values (empty)
818 pub mod W {}
819 pub use super::CC4IE::RW;
820 }
821
822 /// Capture/Compare 1 interrupt enable
823 pub mod CC1IE {
824 /// Offset (1 bits)
825 pub const offset: u32 = 1;
826 /// Mask (1 bit: 1 << 1)
827 pub const mask: u32 = 1 << offset;
828 /// Read-only values (empty)
829 pub mod R {}
830 /// Write-only values (empty)
831 pub mod W {}
832 pub use super::CC4IE::RW;
833 }
834
835 /// Update interrupt enable
836 pub mod UIE {
837 /// Offset (0 bits)
838 pub const offset: u32 = 0;
839 /// Mask (1 bit: 1 << 0)
840 pub const mask: u32 = 1 << offset;
841 /// Read-only values (empty)
842 pub mod R {}
843 /// Write-only values (empty)
844 pub mod W {}
845 /// Read-write values
846 pub mod RW {
847
848 /// 0b0: Update interrupt disabled
849 pub const Disabled: u32 = 0b0;
850
851 /// 0b1: Update interrupt enabled
852 pub const Enabled: u32 = 0b1;
853 }
854 }
855
856 /// Break interrupt enable
857 pub mod BIE {
858 /// Offset (7 bits)
859 pub const offset: u32 = 7;
860 /// Mask (1 bit: 1 << 7)
861 pub const mask: u32 = 1 << offset;
862 /// Read-only values (empty)
863 pub mod R {}
864 /// Write-only values (empty)
865 pub mod W {}
866 /// Read-write values (empty)
867 pub mod RW {}
868 }
869
870 /// COM interrupt enable
871 pub mod COMIE {
872 /// Offset (5 bits)
873 pub const offset: u32 = 5;
874 /// Mask (1 bit: 1 << 5)
875 pub const mask: u32 = 1 << offset;
876 /// Read-only values (empty)
877 pub mod R {}
878 /// Write-only values (empty)
879 pub mod W {}
880 /// Read-write values (empty)
881 pub mod RW {}
882 }
883}
884
885/// status register
886pub mod SR {
887
888 /// Capture/Compare 4 overcapture flag
889 pub mod CC4OF {
890 /// Offset (12 bits)
891 pub const offset: u32 = 12;
892 /// Mask (1 bit: 1 << 12)
893 pub const mask: u32 = 1 << offset;
894 /// Read-only values
895 pub mod R {
896
897 /// 0b1: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
898 pub const Overcapture: u32 = 0b1;
899 }
900 /// Write-only values
901 pub mod W {
902
903 /// 0b0: Clear flag
904 pub const Clear: u32 = 0b0;
905 }
906 /// Read-write values (empty)
907 pub mod RW {}
908 }
909
910 /// Capture/Compare 3 overcapture flag
911 pub mod CC3OF {
912 /// Offset (11 bits)
913 pub const offset: u32 = 11;
914 /// Mask (1 bit: 1 << 11)
915 pub const mask: u32 = 1 << offset;
916 pub use super::CC4OF::R;
917 pub use super::CC4OF::W;
918 /// Read-write values (empty)
919 pub mod RW {}
920 }
921
922 /// Capture/compare 2 overcapture flag
923 pub mod CC2OF {
924 /// Offset (10 bits)
925 pub const offset: u32 = 10;
926 /// Mask (1 bit: 1 << 10)
927 pub const mask: u32 = 1 << offset;
928 pub use super::CC4OF::R;
929 pub use super::CC4OF::W;
930 /// Read-write values (empty)
931 pub mod RW {}
932 }
933
934 /// Capture/Compare 1 overcapture flag
935 pub mod CC1OF {
936 /// Offset (9 bits)
937 pub const offset: u32 = 9;
938 /// Mask (1 bit: 1 << 9)
939 pub const mask: u32 = 1 << offset;
940 pub use super::CC4OF::R;
941 pub use super::CC4OF::W;
942 /// Read-write values (empty)
943 pub mod RW {}
944 }
945
946 /// Break interrupt flag
947 pub mod BIF {
948 /// Offset (7 bits)
949 pub const offset: u32 = 7;
950 /// Mask (1 bit: 1 << 7)
951 pub const mask: u32 = 1 << offset;
952 /// Read-only values (empty)
953 pub mod R {}
954 /// Write-only values (empty)
955 pub mod W {}
956 /// Read-write values (empty)
957 pub mod RW {}
958 }
959
960 /// Trigger interrupt flag
961 pub mod TIF {
962 /// Offset (6 bits)
963 pub const offset: u32 = 6;
964 /// Mask (1 bit: 1 << 6)
965 pub const mask: u32 = 1 << offset;
966 /// Read-only values
967 pub mod R {
968
969 /// 0b0: No trigger event occurred
970 pub const NoTrigger: u32 = 0b0;
971
972 /// 0b1: Trigger interrupt pending
973 pub const Trigger: u32 = 0b1;
974 }
975 pub use super::CC4OF::W;
976 /// Read-write values (empty)
977 pub mod RW {}
978 }
979
980 /// COM interrupt flag
981 pub mod COMIF {
982 /// Offset (5 bits)
983 pub const offset: u32 = 5;
984 /// Mask (1 bit: 1 << 5)
985 pub const mask: u32 = 1 << offset;
986 /// Read-only values (empty)
987 pub mod R {}
988 /// Write-only values (empty)
989 pub mod W {}
990 /// Read-write values (empty)
991 pub mod RW {}
992 }
993
994 /// Capture/Compare 4 interrupt flag
995 pub mod CC4IF {
996 /// Offset (4 bits)
997 pub const offset: u32 = 4;
998 /// Mask (1 bit: 1 << 4)
999 pub const mask: u32 = 1 << offset;
1000 /// Read-only values
1001 pub mod R {
1002
1003 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1004 pub const Match: u32 = 0b1;
1005 }
1006 pub use super::CC4OF::W;
1007 /// Read-write values (empty)
1008 pub mod RW {}
1009 }
1010
1011 /// Capture/Compare 3 interrupt flag
1012 pub mod CC3IF {
1013 /// Offset (3 bits)
1014 pub const offset: u32 = 3;
1015 /// Mask (1 bit: 1 << 3)
1016 pub const mask: u32 = 1 << offset;
1017 /// Read-only values
1018 pub mod R {
1019
1020 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1021 pub const Match: u32 = 0b1;
1022 }
1023 pub use super::CC4OF::W;
1024 /// Read-write values (empty)
1025 pub mod RW {}
1026 }
1027
1028 /// Capture/Compare 2 interrupt flag
1029 pub mod CC2IF {
1030 /// Offset (2 bits)
1031 pub const offset: u32 = 2;
1032 /// Mask (1 bit: 1 << 2)
1033 pub const mask: u32 = 1 << offset;
1034 /// Read-only values
1035 pub mod R {
1036
1037 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1038 pub const Match: u32 = 0b1;
1039 }
1040 pub use super::CC4OF::W;
1041 /// Read-write values (empty)
1042 pub mod RW {}
1043 }
1044
1045 /// Capture/compare 1 interrupt flag
1046 pub mod CC1IF {
1047 /// Offset (1 bits)
1048 pub const offset: u32 = 1;
1049 /// Mask (1 bit: 1 << 1)
1050 pub const mask: u32 = 1 << offset;
1051 /// Read-only values
1052 pub mod R {
1053
1054 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
1055 pub const Match: u32 = 0b1;
1056 }
1057 pub use super::CC4OF::W;
1058 /// Read-write values (empty)
1059 pub mod RW {}
1060 }
1061
1062 /// Update interrupt flag
1063 pub mod UIF {
1064 /// Offset (0 bits)
1065 pub const offset: u32 = 0;
1066 /// Mask (1 bit: 1 << 0)
1067 pub const mask: u32 = 1 << offset;
1068 /// Read-only values (empty)
1069 pub mod R {}
1070 /// Write-only values (empty)
1071 pub mod W {}
1072 /// Read-write values
1073 pub mod RW {
1074
1075 /// 0b0: No update occurred
1076 pub const Clear: u32 = 0b0;
1077
1078 /// 0b1: Update interrupt pending.
1079 pub const UpdatePending: u32 = 0b1;
1080 }
1081 }
1082}
1083
1084/// event generation register
1085pub mod EGR {
1086
1087 /// Break generation
1088 pub mod BG {
1089 /// Offset (7 bits)
1090 pub const offset: u32 = 7;
1091 /// Mask (1 bit: 1 << 7)
1092 pub const mask: u32 = 1 << offset;
1093 /// Read-only values (empty)
1094 pub mod R {}
1095 /// Write-only values (empty)
1096 pub mod W {}
1097 /// Read-write values (empty)
1098 pub mod RW {}
1099 }
1100
1101 /// Trigger generation
1102 pub mod TG {
1103 /// Offset (6 bits)
1104 pub const offset: u32 = 6;
1105 /// Mask (1 bit: 1 << 6)
1106 pub const mask: u32 = 1 << offset;
1107 /// Read-only values (empty)
1108 pub mod R {}
1109 /// Write-only values
1110 pub mod W {
1111
1112 /// 0b1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
1113 pub const Trigger: u32 = 0b1;
1114 }
1115 /// Read-write values (empty)
1116 pub mod RW {}
1117 }
1118
1119 /// Capture/Compare control update generation
1120 pub mod COMG {
1121 /// Offset (5 bits)
1122 pub const offset: u32 = 5;
1123 /// Mask (1 bit: 1 << 5)
1124 pub const mask: u32 = 1 << offset;
1125 /// Read-only values (empty)
1126 pub mod R {}
1127 /// Write-only values (empty)
1128 pub mod W {}
1129 /// Read-write values (empty)
1130 pub mod RW {}
1131 }
1132
1133 /// Capture/compare 4 generation
1134 pub mod CC4G {
1135 /// Offset (4 bits)
1136 pub const offset: u32 = 4;
1137 /// Mask (1 bit: 1 << 4)
1138 pub const mask: u32 = 1 << offset;
1139 /// Read-only values (empty)
1140 pub mod R {}
1141 /// Write-only values
1142 pub mod W {
1143
1144 /// 0b1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
1145 pub const Trigger: u32 = 0b1;
1146 }
1147 /// Read-write values (empty)
1148 pub mod RW {}
1149 }
1150
1151 /// Capture/compare 3 generation
1152 pub mod CC3G {
1153 /// Offset (3 bits)
1154 pub const offset: u32 = 3;
1155 /// Mask (1 bit: 1 << 3)
1156 pub const mask: u32 = 1 << offset;
1157 /// Read-only values (empty)
1158 pub mod R {}
1159 pub use super::CC4G::W;
1160 /// Read-write values (empty)
1161 pub mod RW {}
1162 }
1163
1164 /// Capture/compare 2 generation
1165 pub mod CC2G {
1166 /// Offset (2 bits)
1167 pub const offset: u32 = 2;
1168 /// Mask (1 bit: 1 << 2)
1169 pub const mask: u32 = 1 << offset;
1170 /// Read-only values (empty)
1171 pub mod R {}
1172 pub use super::CC4G::W;
1173 /// Read-write values (empty)
1174 pub mod RW {}
1175 }
1176
1177 /// Capture/compare 1 generation
1178 pub mod CC1G {
1179 /// Offset (1 bits)
1180 pub const offset: u32 = 1;
1181 /// Mask (1 bit: 1 << 1)
1182 pub const mask: u32 = 1 << offset;
1183 /// Read-only values (empty)
1184 pub mod R {}
1185 pub use super::CC4G::W;
1186 /// Read-write values (empty)
1187 pub mod RW {}
1188 }
1189
1190 /// Update generation
1191 pub mod UG {
1192 /// Offset (0 bits)
1193 pub const offset: u32 = 0;
1194 /// Mask (1 bit: 1 << 0)
1195 pub const mask: u32 = 1 << offset;
1196 /// Read-only values (empty)
1197 pub mod R {}
1198 /// Write-only values
1199 pub mod W {
1200
1201 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
1202 pub const Update: u32 = 0b1;
1203 }
1204 /// Read-write values (empty)
1205 pub mod RW {}
1206 }
1207}
1208
1209/// CCMR1_Output and CCMR1_Input
1210/// CCMR1_Output: capture/compare mode register 1 (output mode)
1211/// CCMR1_Input: capture/compare mode register 1 (input mode)
1212pub mod CCMR1 {
1213
1214 /// Output Compare 2 clear enable
1215 pub mod OC2CE {
1216 /// Offset (15 bits)
1217 pub const offset: u32 = 15;
1218 /// Mask (1 bit: 1 << 15)
1219 pub const mask: u32 = 1 << offset;
1220 /// Read-only values (empty)
1221 pub mod R {}
1222 /// Write-only values (empty)
1223 pub mod W {}
1224 /// Read-write values (empty)
1225 pub mod RW {}
1226 }
1227
1228 /// Output Compare 2 mode
1229 pub mod OC2M {
1230 /// Offset (12 bits)
1231 pub const offset: u32 = 12;
1232 /// Mask (3 bits: 0b111 << 12)
1233 pub const mask: u32 = 0b111 << offset;
1234 /// Read-only values (empty)
1235 pub mod R {}
1236 /// Write-only values (empty)
1237 pub mod W {}
1238 /// Read-write values
1239 pub mod RW {
1240
1241 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1242 pub const Frozen: u32 = 0b000;
1243
1244 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1245 pub const ActiveOnMatch: u32 = 0b001;
1246
1247 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
1248 pub const InactiveOnMatch: u32 = 0b010;
1249
1250 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
1251 pub const Toggle: u32 = 0b011;
1252
1253 /// 0b100: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
1254 pub const ForceInactive: u32 = 0b100;
1255
1256 /// 0b101: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
1257 pub const ForceActive: u32 = 0b101;
1258
1259 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
1260 pub const PwmMode1: u32 = 0b110;
1261
1262 /// 0b111: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
1263 pub const PwmMode2: u32 = 0b111;
1264 }
1265 }
1266
1267 /// Output Compare 2 preload enable
1268 pub mod OC2PE {
1269 /// Offset (11 bits)
1270 pub const offset: u32 = 11;
1271 /// Mask (1 bit: 1 << 11)
1272 pub const mask: u32 = 1 << offset;
1273 /// Read-only values (empty)
1274 pub mod R {}
1275 /// Write-only values (empty)
1276 pub mod W {}
1277 /// Read-write values
1278 pub mod RW {
1279
1280 /// 0b0: Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately
1281 pub const Disabled: u32 = 0b0;
1282
1283 /// 0b1: Preload register on CCR2 enabled. Preload value is loaded into active register on each update event
1284 pub const Enabled: u32 = 0b1;
1285 }
1286 }
1287
1288 /// Output Compare 2 fast enable
1289 pub mod OC2FE {
1290 /// Offset (10 bits)
1291 pub const offset: u32 = 10;
1292 /// Mask (1 bit: 1 << 10)
1293 pub const mask: u32 = 1 << offset;
1294 /// Read-only values (empty)
1295 pub mod R {}
1296 /// Write-only values (empty)
1297 pub mod W {}
1298 /// Read-write values (empty)
1299 pub mod RW {}
1300 }
1301
1302 /// Capture/Compare 2 selection
1303 pub mod CC2S {
1304 /// Offset (8 bits)
1305 pub const offset: u32 = 8;
1306 /// Mask (2 bits: 0b11 << 8)
1307 pub const mask: u32 = 0b11 << offset;
1308 /// Read-only values (empty)
1309 pub mod R {}
1310 /// Write-only values (empty)
1311 pub mod W {}
1312 /// Read-write values
1313 pub mod RW {
1314
1315 /// 0b00: CC2 channel is configured as output
1316 pub const Output: u32 = 0b00;
1317 }
1318 }
1319
1320 /// Output Compare 1 clear enable
1321 pub mod OC1CE {
1322 /// Offset (7 bits)
1323 pub const offset: u32 = 7;
1324 /// Mask (1 bit: 1 << 7)
1325 pub const mask: u32 = 1 << offset;
1326 /// Read-only values (empty)
1327 pub mod R {}
1328 /// Write-only values (empty)
1329 pub mod W {}
1330 /// Read-write values (empty)
1331 pub mod RW {}
1332 }
1333
1334 /// Output Compare 1 mode
1335 pub mod OC1M {
1336 /// Offset (4 bits)
1337 pub const offset: u32 = 4;
1338 /// Mask (3 bits: 0b111 << 4)
1339 pub const mask: u32 = 0b111 << offset;
1340 /// Read-only values (empty)
1341 pub mod R {}
1342 /// Write-only values (empty)
1343 pub mod W {}
1344 pub use super::OC2M::RW;
1345 }
1346
1347 /// Output Compare 1 preload enable
1348 pub mod OC1PE {
1349 /// Offset (3 bits)
1350 pub const offset: u32 = 3;
1351 /// Mask (1 bit: 1 << 3)
1352 pub const mask: u32 = 1 << offset;
1353 /// Read-only values (empty)
1354 pub mod R {}
1355 /// Write-only values (empty)
1356 pub mod W {}
1357 /// Read-write values
1358 pub mod RW {
1359
1360 /// 0b0: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1361 pub const Disabled: u32 = 0b0;
1362
1363 /// 0b1: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1364 pub const Enabled: u32 = 0b1;
1365 }
1366 }
1367
1368 /// Output Compare 1 fast enable
1369 pub mod OC1FE {
1370 /// Offset (2 bits)
1371 pub const offset: u32 = 2;
1372 /// Mask (1 bit: 1 << 2)
1373 pub const mask: u32 = 1 << offset;
1374 /// Read-only values (empty)
1375 pub mod R {}
1376 /// Write-only values (empty)
1377 pub mod W {}
1378 /// Read-write values (empty)
1379 pub mod RW {}
1380 }
1381
1382 /// Capture/Compare 1 selection
1383 pub mod CC1S {
1384 /// Offset (0 bits)
1385 pub const offset: u32 = 0;
1386 /// Mask (2 bits: 0b11 << 0)
1387 pub const mask: u32 = 0b11 << offset;
1388 /// Read-only values (empty)
1389 pub mod R {}
1390 /// Write-only values (empty)
1391 pub mod W {}
1392 /// Read-write values
1393 pub mod RW {
1394
1395 /// 0b00: CC1 channel is configured as output
1396 pub const Output: u32 = 0b00;
1397 }
1398 }
1399
1400 /// Output Compare 1 mode, bit 3
1401 pub mod OC1M_3 {
1402 /// Offset (16 bits)
1403 pub const offset: u32 = 16;
1404 /// Mask (1 bit: 1 << 16)
1405 pub const mask: u32 = 1 << offset;
1406 /// Read-only values (empty)
1407 pub mod R {}
1408 /// Write-only values (empty)
1409 pub mod W {}
1410 /// Read-write values
1411 pub mod RW {
1412
1413 /// 0b0: Normal output compare mode (modes 0-7)
1414 pub const Normal: u32 = 0b0;
1415
1416 /// 0b1: Extended output compare mode (modes 7-15)
1417 pub const Extended: u32 = 0b1;
1418 }
1419 }
1420
1421 /// Output Compare 2 mode, bit 3
1422 pub mod OC2M_3 {
1423 /// Offset (24 bits)
1424 pub const offset: u32 = 24;
1425 /// Mask (1 bit: 1 << 24)
1426 pub const mask: u32 = 1 << offset;
1427 /// Read-only values (empty)
1428 pub mod R {}
1429 /// Write-only values (empty)
1430 pub mod W {}
1431 pub use super::OC1M_3::RW;
1432 }
1433
1434 /// Input capture 2 filter
1435 pub mod IC2F {
1436 /// Offset (12 bits)
1437 pub const offset: u32 = 12;
1438 /// Mask (4 bits: 0b1111 << 12)
1439 pub const mask: u32 = 0b1111 << offset;
1440 /// Read-only values (empty)
1441 pub mod R {}
1442 /// Write-only values (empty)
1443 pub mod W {}
1444 /// Read-write values (empty)
1445 pub mod RW {}
1446 }
1447
1448 /// Input capture 2 prescaler
1449 pub mod IC2PSC {
1450 /// Offset (10 bits)
1451 pub const offset: u32 = 10;
1452 /// Mask (2 bits: 0b11 << 10)
1453 pub const mask: u32 = 0b11 << offset;
1454 /// Read-only values (empty)
1455 pub mod R {}
1456 /// Write-only values (empty)
1457 pub mod W {}
1458 /// Read-write values (empty)
1459 pub mod RW {}
1460 }
1461
1462 /// Input capture 1 filter
1463 pub mod IC1F {
1464 /// Offset (4 bits)
1465 pub const offset: u32 = 4;
1466 /// Mask (4 bits: 0b1111 << 4)
1467 pub const mask: u32 = 0b1111 << offset;
1468 /// Read-only values (empty)
1469 pub mod R {}
1470 /// Write-only values (empty)
1471 pub mod W {}
1472 /// Read-write values
1473 pub mod RW {
1474
1475 /// 0b0000: No filter, sampling is done at fDTS
1476 pub const NoFilter: u32 = 0b0000;
1477
1478 /// 0b0001: fSAMPLING=fCK_INT, N=2
1479 pub const FCK_INT_N2: u32 = 0b0001;
1480
1481 /// 0b0010: fSAMPLING=fCK_INT, N=4
1482 pub const FCK_INT_N4: u32 = 0b0010;
1483
1484 /// 0b0011: fSAMPLING=fCK_INT, N=8
1485 pub const FCK_INT_N8: u32 = 0b0011;
1486
1487 /// 0b0100: fSAMPLING=fDTS/2, N=6
1488 pub const FDTS_Div2_N6: u32 = 0b0100;
1489
1490 /// 0b0101: fSAMPLING=fDTS/2, N=8
1491 pub const FDTS_Div2_N8: u32 = 0b0101;
1492
1493 /// 0b0110: fSAMPLING=fDTS/4, N=6
1494 pub const FDTS_Div4_N6: u32 = 0b0110;
1495
1496 /// 0b0111: fSAMPLING=fDTS/4, N=8
1497 pub const FDTS_Div4_N8: u32 = 0b0111;
1498
1499 /// 0b1000: fSAMPLING=fDTS/8, N=6
1500 pub const FDTS_Div8_N6: u32 = 0b1000;
1501
1502 /// 0b1001: fSAMPLING=fDTS/8, N=8
1503 pub const FDTS_Div8_N8: u32 = 0b1001;
1504
1505 /// 0b1010: fSAMPLING=fDTS/16, N=5
1506 pub const FDTS_Div16_N5: u32 = 0b1010;
1507
1508 /// 0b1011: fSAMPLING=fDTS/16, N=6
1509 pub const FDTS_Div16_N6: u32 = 0b1011;
1510
1511 /// 0b1100: fSAMPLING=fDTS/16, N=8
1512 pub const FDTS_Div16_N8: u32 = 0b1100;
1513
1514 /// 0b1101: fSAMPLING=fDTS/32, N=5
1515 pub const FDTS_Div32_N5: u32 = 0b1101;
1516
1517 /// 0b1110: fSAMPLING=fDTS/32, N=6
1518 pub const FDTS_Div32_N6: u32 = 0b1110;
1519
1520 /// 0b1111: fSAMPLING=fDTS/32, N=8
1521 pub const FDTS_Div32_N8: u32 = 0b1111;
1522 }
1523 }
1524
1525 /// Input capture 1 prescaler
1526 pub mod IC1PSC {
1527 /// Offset (2 bits)
1528 pub const offset: u32 = 2;
1529 /// Mask (2 bits: 0b11 << 2)
1530 pub const mask: u32 = 0b11 << offset;
1531 /// Read-only values (empty)
1532 pub mod R {}
1533 /// Write-only values (empty)
1534 pub mod W {}
1535 /// Read-write values (empty)
1536 pub mod RW {}
1537 }
1538}
1539
1540/// CCMR2_Output and CCMR2_Input
1541/// CCMR2_Output: capture/compare mode register 2 (output mode)
1542/// CCMR2_Input: capture/compare mode register 2 (input mode)
1543pub mod CCMR2 {
1544
1545 /// Output compare 4 clear enable
1546 pub mod OC4CE {
1547 /// Offset (15 bits)
1548 pub const offset: u32 = 15;
1549 /// Mask (1 bit: 1 << 15)
1550 pub const mask: u32 = 1 << offset;
1551 /// Read-only values (empty)
1552 pub mod R {}
1553 /// Write-only values (empty)
1554 pub mod W {}
1555 /// Read-write values (empty)
1556 pub mod RW {}
1557 }
1558
1559 /// Output compare 4 mode
1560 pub mod OC4M {
1561 /// Offset (12 bits)
1562 pub const offset: u32 = 12;
1563 /// Mask (3 bits: 0b111 << 12)
1564 pub const mask: u32 = 0b111 << offset;
1565 /// Read-only values (empty)
1566 pub mod R {}
1567 /// Write-only values (empty)
1568 pub mod W {}
1569 /// Read-write values
1570 pub mod RW {
1571
1572 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1573 pub const Frozen: u32 = 0b000;
1574
1575 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
1576 pub const ActiveOnMatch: u32 = 0b001;
1577
1578 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
1579 pub const InactiveOnMatch: u32 = 0b010;
1580
1581 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
1582 pub const Toggle: u32 = 0b011;
1583
1584 /// 0b100: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
1585 pub const ForceInactive: u32 = 0b100;
1586
1587 /// 0b101: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
1588 pub const ForceActive: u32 = 0b101;
1589
1590 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
1591 pub const PwmMode1: u32 = 0b110;
1592
1593 /// 0b111: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
1594 pub const PwmMode2: u32 = 0b111;
1595 }
1596 }
1597
1598 /// Output compare 4 preload enable
1599 pub mod OC4PE {
1600 /// Offset (11 bits)
1601 pub const offset: u32 = 11;
1602 /// Mask (1 bit: 1 << 11)
1603 pub const mask: u32 = 1 << offset;
1604 /// Read-only values (empty)
1605 pub mod R {}
1606 /// Write-only values (empty)
1607 pub mod W {}
1608 /// Read-write values
1609 pub mod RW {
1610
1611 /// 0b0: Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately
1612 pub const Disabled: u32 = 0b0;
1613
1614 /// 0b1: Preload register on CCR4 enabled. Preload value is loaded into active register on each update event
1615 pub const Enabled: u32 = 0b1;
1616 }
1617 }
1618
1619 /// Output compare 4 fast enable
1620 pub mod OC4FE {
1621 /// Offset (10 bits)
1622 pub const offset: u32 = 10;
1623 /// Mask (1 bit: 1 << 10)
1624 pub const mask: u32 = 1 << offset;
1625 /// Read-only values (empty)
1626 pub mod R {}
1627 /// Write-only values (empty)
1628 pub mod W {}
1629 /// Read-write values (empty)
1630 pub mod RW {}
1631 }
1632
1633 /// Capture/Compare 4 selection
1634 pub mod CC4S {
1635 /// Offset (8 bits)
1636 pub const offset: u32 = 8;
1637 /// Mask (2 bits: 0b11 << 8)
1638 pub const mask: u32 = 0b11 << offset;
1639 /// Read-only values (empty)
1640 pub mod R {}
1641 /// Write-only values (empty)
1642 pub mod W {}
1643 /// Read-write values
1644 pub mod RW {
1645
1646 /// 0b00: CC4 channel is configured as output
1647 pub const Output: u32 = 0b00;
1648 }
1649 }
1650
1651 /// Output compare 3 clear enable
1652 pub mod OC3CE {
1653 /// Offset (7 bits)
1654 pub const offset: u32 = 7;
1655 /// Mask (1 bit: 1 << 7)
1656 pub const mask: u32 = 1 << offset;
1657 /// Read-only values (empty)
1658 pub mod R {}
1659 /// Write-only values (empty)
1660 pub mod W {}
1661 /// Read-write values (empty)
1662 pub mod RW {}
1663 }
1664
1665 /// Output compare 3 mode
1666 pub mod OC3M {
1667 /// Offset (4 bits)
1668 pub const offset: u32 = 4;
1669 /// Mask (3 bits: 0b111 << 4)
1670 pub const mask: u32 = 0b111 << offset;
1671 /// Read-only values (empty)
1672 pub mod R {}
1673 /// Write-only values (empty)
1674 pub mod W {}
1675 pub use super::OC4M::RW;
1676 }
1677
1678 /// Output compare 3 preload enable
1679 pub mod OC3PE {
1680 /// Offset (3 bits)
1681 pub const offset: u32 = 3;
1682 /// Mask (1 bit: 1 << 3)
1683 pub const mask: u32 = 1 << offset;
1684 /// Read-only values (empty)
1685 pub mod R {}
1686 /// Write-only values (empty)
1687 pub mod W {}
1688 /// Read-write values
1689 pub mod RW {
1690
1691 /// 0b0: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1692 pub const Disabled: u32 = 0b0;
1693
1694 /// 0b1: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1695 pub const Enabled: u32 = 0b1;
1696 }
1697 }
1698
1699 /// Output compare 3 fast enable
1700 pub mod OC3FE {
1701 /// Offset (2 bits)
1702 pub const offset: u32 = 2;
1703 /// Mask (1 bit: 1 << 2)
1704 pub const mask: u32 = 1 << offset;
1705 /// Read-only values (empty)
1706 pub mod R {}
1707 /// Write-only values (empty)
1708 pub mod W {}
1709 /// Read-write values (empty)
1710 pub mod RW {}
1711 }
1712
1713 /// Capture/Compare 3 selection
1714 pub mod CC3S {
1715 /// Offset (0 bits)
1716 pub const offset: u32 = 0;
1717 /// Mask (2 bits: 0b11 << 0)
1718 pub const mask: u32 = 0b11 << offset;
1719 /// Read-only values (empty)
1720 pub mod R {}
1721 /// Write-only values (empty)
1722 pub mod W {}
1723 /// Read-write values
1724 pub mod RW {
1725
1726 /// 0b00: CC3 channel is configured as output
1727 pub const Output: u32 = 0b00;
1728 }
1729 }
1730
1731 /// Output Compare 3 mode, bit 3
1732 pub mod OC3M_3 {
1733 /// Offset (16 bits)
1734 pub const offset: u32 = 16;
1735 /// Mask (1 bit: 1 << 16)
1736 pub const mask: u32 = 1 << offset;
1737 /// Read-only values (empty)
1738 pub mod R {}
1739 /// Write-only values (empty)
1740 pub mod W {}
1741 /// Read-write values
1742 pub mod RW {
1743
1744 /// 0b0: Normal output compare mode (modes 0-7)
1745 pub const Normal: u32 = 0b0;
1746
1747 /// 0b1: Extended output compare mode (modes 7-15)
1748 pub const Extended: u32 = 0b1;
1749 }
1750 }
1751
1752 /// Output Compare 4 mode, bit 3
1753 pub mod OC4M_3 {
1754 /// Offset (24 bits)
1755 pub const offset: u32 = 24;
1756 /// Mask (1 bit: 1 << 24)
1757 pub const mask: u32 = 1 << offset;
1758 /// Read-only values (empty)
1759 pub mod R {}
1760 /// Write-only values (empty)
1761 pub mod W {}
1762 pub use super::OC3M_3::RW;
1763 }
1764
1765 /// Input capture 4 filter
1766 pub mod IC4F {
1767 /// Offset (12 bits)
1768 pub const offset: u32 = 12;
1769 /// Mask (4 bits: 0b1111 << 12)
1770 pub const mask: u32 = 0b1111 << offset;
1771 /// Read-only values (empty)
1772 pub mod R {}
1773 /// Write-only values (empty)
1774 pub mod W {}
1775 /// Read-write values (empty)
1776 pub mod RW {}
1777 }
1778
1779 /// Input capture 4 prescaler
1780 pub mod IC4PSC {
1781 /// Offset (10 bits)
1782 pub const offset: u32 = 10;
1783 /// Mask (2 bits: 0b11 << 10)
1784 pub const mask: u32 = 0b11 << offset;
1785 /// Read-only values (empty)
1786 pub mod R {}
1787 /// Write-only values (empty)
1788 pub mod W {}
1789 /// Read-write values (empty)
1790 pub mod RW {}
1791 }
1792
1793 /// Input capture 3 filter
1794 pub mod IC3F {
1795 /// Offset (4 bits)
1796 pub const offset: u32 = 4;
1797 /// Mask (4 bits: 0b1111 << 4)
1798 pub const mask: u32 = 0b1111 << offset;
1799 /// Read-only values (empty)
1800 pub mod R {}
1801 /// Write-only values (empty)
1802 pub mod W {}
1803 /// Read-write values (empty)
1804 pub mod RW {}
1805 }
1806
1807 /// Input capture 3 prescaler
1808 pub mod IC3PSC {
1809 /// Offset (2 bits)
1810 pub const offset: u32 = 2;
1811 /// Mask (2 bits: 0b11 << 2)
1812 pub const mask: u32 = 0b11 << offset;
1813 /// Read-only values (empty)
1814 pub mod R {}
1815 /// Write-only values (empty)
1816 pub mod W {}
1817 /// Read-write values (empty)
1818 pub mod RW {}
1819 }
1820}
1821
1822/// capture/compare enable register
1823pub mod CCER {
1824
1825 /// Capture/Compare 3 output Polarity
1826 pub mod CC4P {
1827 /// Offset (13 bits)
1828 pub const offset: u32 = 13;
1829 /// Mask (1 bit: 1 << 13)
1830 pub const mask: u32 = 1 << offset;
1831 /// Read-only values (empty)
1832 pub mod R {}
1833 /// Write-only values (empty)
1834 pub mod W {}
1835 /// Read-write values (empty)
1836 pub mod RW {}
1837 }
1838
1839 /// Capture/Compare 4 output enable
1840 pub mod CC4E {
1841 /// Offset (12 bits)
1842 pub const offset: u32 = 12;
1843 /// Mask (1 bit: 1 << 12)
1844 pub const mask: u32 = 1 << offset;
1845 /// Read-only values (empty)
1846 pub mod R {}
1847 /// Write-only values (empty)
1848 pub mod W {}
1849 /// Read-write values (empty)
1850 pub mod RW {}
1851 }
1852
1853 /// Capture/Compare 3 output Polarity
1854 pub mod CC3NP {
1855 /// Offset (11 bits)
1856 pub const offset: u32 = 11;
1857 /// Mask (1 bit: 1 << 11)
1858 pub const mask: u32 = 1 << offset;
1859 /// Read-only values (empty)
1860 pub mod R {}
1861 /// Write-only values (empty)
1862 pub mod W {}
1863 /// Read-write values (empty)
1864 pub mod RW {}
1865 }
1866
1867 /// Capture/Compare 3 complementary output enable
1868 pub mod CC3NE {
1869 /// Offset (10 bits)
1870 pub const offset: u32 = 10;
1871 /// Mask (1 bit: 1 << 10)
1872 pub const mask: u32 = 1 << offset;
1873 /// Read-only values (empty)
1874 pub mod R {}
1875 /// Write-only values (empty)
1876 pub mod W {}
1877 /// Read-write values (empty)
1878 pub mod RW {}
1879 }
1880
1881 /// Capture/Compare 3 output Polarity
1882 pub mod CC3P {
1883 /// Offset (9 bits)
1884 pub const offset: u32 = 9;
1885 /// Mask (1 bit: 1 << 9)
1886 pub const mask: u32 = 1 << offset;
1887 /// Read-only values (empty)
1888 pub mod R {}
1889 /// Write-only values (empty)
1890 pub mod W {}
1891 /// Read-write values (empty)
1892 pub mod RW {}
1893 }
1894
1895 /// Capture/Compare 3 output enable
1896 pub mod CC3E {
1897 /// Offset (8 bits)
1898 pub const offset: u32 = 8;
1899 /// Mask (1 bit: 1 << 8)
1900 pub const mask: u32 = 1 << offset;
1901 /// Read-only values (empty)
1902 pub mod R {}
1903 /// Write-only values (empty)
1904 pub mod W {}
1905 /// Read-write values (empty)
1906 pub mod RW {}
1907 }
1908
1909 /// Capture/Compare 2 output Polarity
1910 pub mod CC2NP {
1911 /// Offset (7 bits)
1912 pub const offset: u32 = 7;
1913 /// Mask (1 bit: 1 << 7)
1914 pub const mask: u32 = 1 << offset;
1915 /// Read-only values (empty)
1916 pub mod R {}
1917 /// Write-only values (empty)
1918 pub mod W {}
1919 /// Read-write values (empty)
1920 pub mod RW {}
1921 }
1922
1923 /// Capture/Compare 2 complementary output enable
1924 pub mod CC2NE {
1925 /// Offset (6 bits)
1926 pub const offset: u32 = 6;
1927 /// Mask (1 bit: 1 << 6)
1928 pub const mask: u32 = 1 << offset;
1929 /// Read-only values (empty)
1930 pub mod R {}
1931 /// Write-only values (empty)
1932 pub mod W {}
1933 /// Read-write values (empty)
1934 pub mod RW {}
1935 }
1936
1937 /// Capture/Compare 2 output Polarity
1938 pub mod CC2P {
1939 /// Offset (5 bits)
1940 pub const offset: u32 = 5;
1941 /// Mask (1 bit: 1 << 5)
1942 pub const mask: u32 = 1 << offset;
1943 /// Read-only values (empty)
1944 pub mod R {}
1945 /// Write-only values (empty)
1946 pub mod W {}
1947 /// Read-write values (empty)
1948 pub mod RW {}
1949 }
1950
1951 /// Capture/Compare 2 output enable
1952 pub mod CC2E {
1953 /// Offset (4 bits)
1954 pub const offset: u32 = 4;
1955 /// Mask (1 bit: 1 << 4)
1956 pub const mask: u32 = 1 << offset;
1957 /// Read-only values (empty)
1958 pub mod R {}
1959 /// Write-only values (empty)
1960 pub mod W {}
1961 /// Read-write values (empty)
1962 pub mod RW {}
1963 }
1964
1965 /// Capture/Compare 1 output Polarity
1966 pub mod CC1NP {
1967 /// Offset (3 bits)
1968 pub const offset: u32 = 3;
1969 /// Mask (1 bit: 1 << 3)
1970 pub const mask: u32 = 1 << offset;
1971 /// Read-only values (empty)
1972 pub mod R {}
1973 /// Write-only values (empty)
1974 pub mod W {}
1975 /// Read-write values (empty)
1976 pub mod RW {}
1977 }
1978
1979 /// Capture/Compare 1 complementary output enable
1980 pub mod CC1NE {
1981 /// Offset (2 bits)
1982 pub const offset: u32 = 2;
1983 /// Mask (1 bit: 1 << 2)
1984 pub const mask: u32 = 1 << offset;
1985 /// Read-only values (empty)
1986 pub mod R {}
1987 /// Write-only values (empty)
1988 pub mod W {}
1989 /// Read-write values (empty)
1990 pub mod RW {}
1991 }
1992
1993 /// Capture/Compare 1 output Polarity
1994 pub mod CC1P {
1995 /// Offset (1 bits)
1996 pub const offset: u32 = 1;
1997 /// Mask (1 bit: 1 << 1)
1998 pub const mask: u32 = 1 << offset;
1999 /// Read-only values (empty)
2000 pub mod R {}
2001 /// Write-only values (empty)
2002 pub mod W {}
2003 /// Read-write values (empty)
2004 pub mod RW {}
2005 }
2006
2007 /// Capture/Compare 1 output enable
2008 pub mod CC1E {
2009 /// Offset (0 bits)
2010 pub const offset: u32 = 0;
2011 /// Mask (1 bit: 1 << 0)
2012 pub const mask: u32 = 1 << offset;
2013 /// Read-only values (empty)
2014 pub mod R {}
2015 /// Write-only values (empty)
2016 pub mod W {}
2017 /// Read-write values (empty)
2018 pub mod RW {}
2019 }
2020}
2021
2022/// counter
2023pub mod CNT {
2024
2025 /// counter value
2026 pub mod CNT {
2027 /// Offset (0 bits)
2028 pub const offset: u32 = 0;
2029 /// Mask (16 bits: 0xffff << 0)
2030 pub const mask: u32 = 0xffff << offset;
2031 /// Read-only values (empty)
2032 pub mod R {}
2033 /// Write-only values (empty)
2034 pub mod W {}
2035 /// Read-write values (empty)
2036 pub mod RW {}
2037 }
2038}
2039
2040/// prescaler
2041pub mod PSC {
2042
2043 /// Prescaler value
2044 pub mod PSC {
2045 /// Offset (0 bits)
2046 pub const offset: u32 = 0;
2047 /// Mask (16 bits: 0xffff << 0)
2048 pub const mask: u32 = 0xffff << offset;
2049 /// Read-only values (empty)
2050 pub mod R {}
2051 /// Write-only values (empty)
2052 pub mod W {}
2053 /// Read-write values (empty)
2054 pub mod RW {}
2055 }
2056}
2057
2058/// auto-reload register
2059pub mod ARR {
2060
2061 /// Auto-reload value
2062 pub mod ARR {
2063 /// Offset (0 bits)
2064 pub const offset: u32 = 0;
2065 /// Mask (16 bits: 0xffff << 0)
2066 pub const mask: u32 = 0xffff << offset;
2067 /// Read-only values (empty)
2068 pub mod R {}
2069 /// Write-only values (empty)
2070 pub mod W {}
2071 /// Read-write values (empty)
2072 pub mod RW {}
2073 }
2074}
2075
2076/// repetition counter register
2077pub mod RCR {
2078
2079 /// Repetition counter value
2080 pub mod REP {
2081 /// Offset (0 bits)
2082 pub const offset: u32 = 0;
2083 /// Mask (8 bits: 0xff << 0)
2084 pub const mask: u32 = 0xff << offset;
2085 /// Read-only values (empty)
2086 pub mod R {}
2087 /// Write-only values (empty)
2088 pub mod W {}
2089 /// Read-write values (empty)
2090 pub mod RW {}
2091 }
2092}
2093
2094/// capture/compare register
2095pub mod CCR1 {
2096
2097 /// Capture/Compare value
2098 pub mod CCR {
2099 /// Offset (0 bits)
2100 pub const offset: u32 = 0;
2101 /// Mask (16 bits: 0xffff << 0)
2102 pub const mask: u32 = 0xffff << offset;
2103 /// Read-only values (empty)
2104 pub mod R {}
2105 /// Write-only values (empty)
2106 pub mod W {}
2107 /// Read-write values (empty)
2108 pub mod RW {}
2109 }
2110}
2111
2112/// capture/compare register
2113pub mod CCR2 {
2114 pub use super::CCR1::CCR;
2115}
2116
2117/// capture/compare register
2118pub mod CCR3 {
2119 pub use super::CCR1::CCR;
2120}
2121
2122/// capture/compare register
2123pub mod CCR4 {
2124 pub use super::CCR1::CCR;
2125}
2126
2127/// break and dead-time register
2128pub mod BDTR {
2129
2130 /// Main output enable
2131 pub mod MOE {
2132 /// Offset (15 bits)
2133 pub const offset: u32 = 15;
2134 /// Mask (1 bit: 1 << 15)
2135 pub const mask: u32 = 1 << offset;
2136 /// Read-only values (empty)
2137 pub mod R {}
2138 /// Write-only values (empty)
2139 pub mod W {}
2140 /// Read-write values
2141 pub mod RW {
2142
2143 /// 0b0: OC/OCN are disabled or forced idle depending on OSSI
2144 pub const DisabledIdle: u32 = 0b0;
2145
2146 /// 0b1: OC/OCN are enabled if CCxE/CCxNE are set
2147 pub const Enabled: u32 = 0b1;
2148 }
2149 }
2150
2151 /// Automatic output enable
2152 pub mod AOE {
2153 /// Offset (14 bits)
2154 pub const offset: u32 = 14;
2155 /// Mask (1 bit: 1 << 14)
2156 pub const mask: u32 = 1 << offset;
2157 /// Read-only values (empty)
2158 pub mod R {}
2159 /// Write-only values (empty)
2160 pub mod W {}
2161 /// Read-write values (empty)
2162 pub mod RW {}
2163 }
2164
2165 /// Break polarity
2166 pub mod BKP {
2167 /// Offset (13 bits)
2168 pub const offset: u32 = 13;
2169 /// Mask (1 bit: 1 << 13)
2170 pub const mask: u32 = 1 << offset;
2171 /// Read-only values (empty)
2172 pub mod R {}
2173 /// Write-only values (empty)
2174 pub mod W {}
2175 /// Read-write values (empty)
2176 pub mod RW {}
2177 }
2178
2179 /// Break enable
2180 pub mod BKE {
2181 /// Offset (12 bits)
2182 pub const offset: u32 = 12;
2183 /// Mask (1 bit: 1 << 12)
2184 pub const mask: u32 = 1 << offset;
2185 /// Read-only values (empty)
2186 pub mod R {}
2187 /// Write-only values (empty)
2188 pub mod W {}
2189 /// Read-write values (empty)
2190 pub mod RW {}
2191 }
2192
2193 /// Off-state selection for Run mode
2194 pub mod OSSR {
2195 /// Offset (11 bits)
2196 pub const offset: u32 = 11;
2197 /// Mask (1 bit: 1 << 11)
2198 pub const mask: u32 = 1 << offset;
2199 /// Read-only values (empty)
2200 pub mod R {}
2201 /// Write-only values (empty)
2202 pub mod W {}
2203 /// Read-write values
2204 pub mod RW {
2205
2206 /// 0b0: When inactive, OC/OCN outputs are disabled
2207 pub const Disabled: u32 = 0b0;
2208
2209 /// 0b1: When inactive, OC/OCN outputs are enabled with their inactive level
2210 pub const IdleLevel: u32 = 0b1;
2211 }
2212 }
2213
2214 /// Off-state selection for Idle mode
2215 pub mod OSSI {
2216 /// Offset (10 bits)
2217 pub const offset: u32 = 10;
2218 /// Mask (1 bit: 1 << 10)
2219 pub const mask: u32 = 1 << offset;
2220 /// Read-only values (empty)
2221 pub mod R {}
2222 /// Write-only values (empty)
2223 pub mod W {}
2224 /// Read-write values
2225 pub mod RW {
2226
2227 /// 0b0: When inactive, OC/OCN outputs are disabled
2228 pub const Disabled: u32 = 0b0;
2229
2230 /// 0b1: When inactive, OC/OCN outputs are forced to idle level
2231 pub const IdleLevel: u32 = 0b1;
2232 }
2233 }
2234
2235 /// Lock configuration
2236 pub mod LOCK {
2237 /// Offset (8 bits)
2238 pub const offset: u32 = 8;
2239 /// Mask (2 bits: 0b11 << 8)
2240 pub const mask: u32 = 0b11 << offset;
2241 /// Read-only values (empty)
2242 pub mod R {}
2243 /// Write-only values (empty)
2244 pub mod W {}
2245 /// Read-write values (empty)
2246 pub mod RW {}
2247 }
2248
2249 /// Dead-time generator setup
2250 pub mod DTG {
2251 /// Offset (0 bits)
2252 pub const offset: u32 = 0;
2253 /// Mask (8 bits: 0xff << 0)
2254 pub const mask: u32 = 0xff << offset;
2255 /// Read-only values (empty)
2256 pub mod R {}
2257 /// Write-only values (empty)
2258 pub mod W {}
2259 /// Read-write values (empty)
2260 pub mod RW {}
2261 }
2262}
2263
2264/// DMA control register
2265pub mod DCR {
2266
2267 /// DMA burst length
2268 pub mod DBL {
2269 /// Offset (8 bits)
2270 pub const offset: u32 = 8;
2271 /// Mask (5 bits: 0b11111 << 8)
2272 pub const mask: u32 = 0b11111 << offset;
2273 /// Read-only values (empty)
2274 pub mod R {}
2275 /// Write-only values (empty)
2276 pub mod W {}
2277 /// Read-write values (empty)
2278 pub mod RW {}
2279 }
2280
2281 /// DMA base address
2282 pub mod DBA {
2283 /// Offset (0 bits)
2284 pub const offset: u32 = 0;
2285 /// Mask (5 bits: 0b11111 << 0)
2286 pub const mask: u32 = 0b11111 << offset;
2287 /// Read-only values (empty)
2288 pub mod R {}
2289 /// Write-only values (empty)
2290 pub mod W {}
2291 /// Read-write values (empty)
2292 pub mod RW {}
2293 }
2294}
2295
2296/// DMA address for full transfer
2297pub mod DMAR {
2298
2299 /// DMA register for burst accesses
2300 pub mod DMAB {
2301 /// Offset (0 bits)
2302 pub const offset: u32 = 0;
2303 /// Mask (16 bits: 0xffff << 0)
2304 pub const mask: u32 = 0xffff << offset;
2305 /// Read-only values (empty)
2306 pub mod R {}
2307 /// Write-only values (empty)
2308 pub mod W {}
2309 /// Read-write values (empty)
2310 pub mod RW {}
2311 }
2312}
2313
2314/// DMA address for full transfer
2315pub mod OR1 {
2316
2317 /// External trigger remap on ADC2 analog watchdog
2318 pub mod ETR_ADC2_RMP {
2319 /// Offset (0 bits)
2320 pub const offset: u32 = 0;
2321 /// Mask (2 bits: 0b11 << 0)
2322 pub const mask: u32 = 0b11 << offset;
2323 /// Read-only values (empty)
2324 pub mod R {}
2325 /// Write-only values (empty)
2326 pub mod W {}
2327 /// Read-write values (empty)
2328 pub mod RW {}
2329 }
2330
2331 /// External trigger remap on ADC3 analog watchdog
2332 pub mod ETR_ADC3_RMP {
2333 /// Offset (2 bits)
2334 pub const offset: u32 = 2;
2335 /// Mask (2 bits: 0b11 << 2)
2336 pub const mask: u32 = 0b11 << offset;
2337 /// Read-only values (empty)
2338 pub mod R {}
2339 /// Write-only values (empty)
2340 pub mod W {}
2341 /// Read-write values (empty)
2342 pub mod RW {}
2343 }
2344
2345 /// Input Capture 1 remap
2346 pub mod TI1_RMP {
2347 /// Offset (4 bits)
2348 pub const offset: u32 = 4;
2349 /// Mask (1 bit: 1 << 4)
2350 pub const mask: u32 = 1 << offset;
2351 /// Read-only values (empty)
2352 pub mod R {}
2353 /// Write-only values (empty)
2354 pub mod W {}
2355 /// Read-write values (empty)
2356 pub mod RW {}
2357 }
2358}
2359
2360/// capture/compare mode register 2 (output mode)
2361pub mod CCMR3_Output {
2362
2363 /// Output Compare 6 mode bit 3
2364 pub mod OC6M_3 {
2365 /// Offset (24 bits)
2366 pub const offset: u32 = 24;
2367 /// Mask (1 bit: 1 << 24)
2368 pub const mask: u32 = 1 << offset;
2369 /// Read-only values (empty)
2370 pub mod R {}
2371 /// Write-only values (empty)
2372 pub mod W {}
2373 /// Read-write values
2374 pub mod RW {
2375
2376 /// 0b0: Normal output compare mode (modes 0-7)
2377 pub const Normal: u32 = 0b0;
2378
2379 /// 0b1: Extended output compare mode (modes 7-15)
2380 pub const Extended: u32 = 0b1;
2381 }
2382 }
2383
2384 /// Output Compare 5 mode bit 3
2385 pub mod OC5M_3 {
2386 /// Offset (16 bits)
2387 pub const offset: u32 = 16;
2388 /// Mask (1 bit: 1 << 16)
2389 pub const mask: u32 = 1 << offset;
2390 /// Read-only values (empty)
2391 pub mod R {}
2392 /// Write-only values (empty)
2393 pub mod W {}
2394 pub use super::OC6M_3::RW;
2395 }
2396
2397 /// Output compare 6 clear enable
2398 pub mod OC6CE {
2399 /// Offset (15 bits)
2400 pub const offset: u32 = 15;
2401 /// Mask (1 bit: 1 << 15)
2402 pub const mask: u32 = 1 << offset;
2403 /// Read-only values (empty)
2404 pub mod R {}
2405 /// Write-only values (empty)
2406 pub mod W {}
2407 /// Read-write values (empty)
2408 pub mod RW {}
2409 }
2410
2411 /// Output compare 6 mode
2412 pub mod OC6M {
2413 /// Offset (12 bits)
2414 pub const offset: u32 = 12;
2415 /// Mask (3 bits: 0b111 << 12)
2416 pub const mask: u32 = 0b111 << offset;
2417 /// Read-only values (empty)
2418 pub mod R {}
2419 /// Write-only values (empty)
2420 pub mod W {}
2421 /// Read-write values
2422 pub mod RW {
2423
2424 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
2425 pub const Frozen: u32 = 0b000;
2426
2427 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2428 pub const ActiveOnMatch: u32 = 0b001;
2429
2430 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
2431 pub const InactiveOnMatch: u32 = 0b010;
2432
2433 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
2434 pub const Toggle: u32 = 0b011;
2435
2436 /// 0b100: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
2437 pub const ForceInactive: u32 = 0b100;
2438
2439 /// 0b101: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
2440 pub const ForceActive: u32 = 0b101;
2441
2442 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
2443 pub const PwmMode1: u32 = 0b110;
2444
2445 /// 0b111: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
2446 pub const PwmMode2: u32 = 0b111;
2447 }
2448 }
2449
2450 /// Output compare 6 preload enable
2451 pub mod OC6PE {
2452 /// Offset (11 bits)
2453 pub const offset: u32 = 11;
2454 /// Mask (1 bit: 1 << 11)
2455 pub const mask: u32 = 1 << offset;
2456 /// Read-only values (empty)
2457 pub mod R {}
2458 /// Write-only values (empty)
2459 pub mod W {}
2460 /// Read-write values (empty)
2461 pub mod RW {}
2462 }
2463
2464 /// Output compare 6 fast enable
2465 pub mod OC6FE {
2466 /// Offset (10 bits)
2467 pub const offset: u32 = 10;
2468 /// Mask (1 bit: 1 << 10)
2469 pub const mask: u32 = 1 << offset;
2470 /// Read-only values (empty)
2471 pub mod R {}
2472 /// Write-only values (empty)
2473 pub mod W {}
2474 /// Read-write values (empty)
2475 pub mod RW {}
2476 }
2477
2478 /// Output compare 5 clear enable
2479 pub mod OC5CE {
2480 /// Offset (7 bits)
2481 pub const offset: u32 = 7;
2482 /// Mask (1 bit: 1 << 7)
2483 pub const mask: u32 = 1 << offset;
2484 /// Read-only values (empty)
2485 pub mod R {}
2486 /// Write-only values (empty)
2487 pub mod W {}
2488 /// Read-write values (empty)
2489 pub mod RW {}
2490 }
2491
2492 /// Output compare 5 mode
2493 pub mod OC5M {
2494 /// Offset (4 bits)
2495 pub const offset: u32 = 4;
2496 /// Mask (3 bits: 0b111 << 4)
2497 pub const mask: u32 = 0b111 << offset;
2498 /// Read-only values (empty)
2499 pub mod R {}
2500 /// Write-only values (empty)
2501 pub mod W {}
2502 pub use super::OC6M::RW;
2503 }
2504
2505 /// Output compare 5 preload enable
2506 pub mod OC5PE {
2507 /// Offset (3 bits)
2508 pub const offset: u32 = 3;
2509 /// Mask (1 bit: 1 << 3)
2510 pub const mask: u32 = 1 << offset;
2511 /// Read-only values (empty)
2512 pub mod R {}
2513 /// Write-only values (empty)
2514 pub mod W {}
2515 /// Read-write values (empty)
2516 pub mod RW {}
2517 }
2518
2519 /// Output compare 5 fast enable
2520 pub mod OC5FE {
2521 /// Offset (2 bits)
2522 pub const offset: u32 = 2;
2523 /// Mask (1 bit: 1 << 2)
2524 pub const mask: u32 = 1 << offset;
2525 /// Read-only values (empty)
2526 pub mod R {}
2527 /// Write-only values (empty)
2528 pub mod W {}
2529 /// Read-write values (empty)
2530 pub mod RW {}
2531 }
2532}
2533
2534/// capture/compare register
2535pub mod CCR5 {
2536
2537 /// Capture/Compare value
2538 pub mod CCR {
2539 /// Offset (0 bits)
2540 pub const offset: u32 = 0;
2541 /// Mask (16 bits: 0xffff << 0)
2542 pub const mask: u32 = 0xffff << offset;
2543 /// Read-only values (empty)
2544 pub mod R {}
2545 /// Write-only values (empty)
2546 pub mod W {}
2547 /// Read-write values (empty)
2548 pub mod RW {}
2549 }
2550
2551 /// Group Channel 5 and Channel 1
2552 pub mod GC5C1 {
2553 /// Offset (29 bits)
2554 pub const offset: u32 = 29;
2555 /// Mask (1 bit: 1 << 29)
2556 pub const mask: u32 = 1 << offset;
2557 /// Read-only values (empty)
2558 pub mod R {}
2559 /// Write-only values (empty)
2560 pub mod W {}
2561 /// Read-write values (empty)
2562 pub mod RW {}
2563 }
2564
2565 /// Group Channel 5 and Channel 2
2566 pub mod GC5C2 {
2567 /// Offset (30 bits)
2568 pub const offset: u32 = 30;
2569 /// Mask (1 bit: 1 << 30)
2570 pub const mask: u32 = 1 << offset;
2571 /// Read-only values (empty)
2572 pub mod R {}
2573 /// Write-only values (empty)
2574 pub mod W {}
2575 /// Read-write values (empty)
2576 pub mod RW {}
2577 }
2578
2579 /// Group Channel 5 and Channel 3
2580 pub mod GC5C3 {
2581 /// Offset (31 bits)
2582 pub const offset: u32 = 31;
2583 /// Mask (1 bit: 1 << 31)
2584 pub const mask: u32 = 1 << offset;
2585 /// Read-only values (empty)
2586 pub mod R {}
2587 /// Write-only values (empty)
2588 pub mod W {}
2589 /// Read-write values (empty)
2590 pub mod RW {}
2591 }
2592}
2593
2594/// capture/compare register
2595pub mod CCR6 {
2596 pub use super::CCR1::CCR;
2597}
2598
2599/// DMA address for full transfer
2600pub mod OR2 {
2601
2602 /// BRK BKIN input enable
2603 pub mod BKINE {
2604 /// Offset (0 bits)
2605 pub const offset: u32 = 0;
2606 /// Mask (1 bit: 1 << 0)
2607 pub const mask: u32 = 1 << offset;
2608 /// Read-only values (empty)
2609 pub mod R {}
2610 /// Write-only values (empty)
2611 pub mod W {}
2612 /// Read-write values (empty)
2613 pub mod RW {}
2614 }
2615
2616 /// BRK COMP1 enable
2617 pub mod BKCMP1E {
2618 /// Offset (1 bits)
2619 pub const offset: u32 = 1;
2620 /// Mask (1 bit: 1 << 1)
2621 pub const mask: u32 = 1 << offset;
2622 /// Read-only values (empty)
2623 pub mod R {}
2624 /// Write-only values (empty)
2625 pub mod W {}
2626 /// Read-write values (empty)
2627 pub mod RW {}
2628 }
2629
2630 /// BRK COMP2 enable
2631 pub mod BKCMP2E {
2632 /// Offset (2 bits)
2633 pub const offset: u32 = 2;
2634 /// Mask (1 bit: 1 << 2)
2635 pub const mask: u32 = 1 << offset;
2636 /// Read-only values (empty)
2637 pub mod R {}
2638 /// Write-only values (empty)
2639 pub mod W {}
2640 /// Read-write values (empty)
2641 pub mod RW {}
2642 }
2643
2644 /// BRK DFSDM_BREAK2 enable
2645 pub mod BKDFBK2E {
2646 /// Offset (8 bits)
2647 pub const offset: u32 = 8;
2648 /// Mask (1 bit: 1 << 8)
2649 pub const mask: u32 = 1 << offset;
2650 /// Read-only values (empty)
2651 pub mod R {}
2652 /// Write-only values (empty)
2653 pub mod W {}
2654 /// Read-write values (empty)
2655 pub mod RW {}
2656 }
2657
2658 /// BRK BKIN input polarity
2659 pub mod BKINP {
2660 /// Offset (9 bits)
2661 pub const offset: u32 = 9;
2662 /// Mask (1 bit: 1 << 9)
2663 pub const mask: u32 = 1 << offset;
2664 /// Read-only values (empty)
2665 pub mod R {}
2666 /// Write-only values (empty)
2667 pub mod W {}
2668 /// Read-write values (empty)
2669 pub mod RW {}
2670 }
2671
2672 /// BRK COMP1 input polarity
2673 pub mod BKCMP1P {
2674 /// Offset (10 bits)
2675 pub const offset: u32 = 10;
2676 /// Mask (1 bit: 1 << 10)
2677 pub const mask: u32 = 1 << offset;
2678 /// Read-only values (empty)
2679 pub mod R {}
2680 /// Write-only values (empty)
2681 pub mod W {}
2682 /// Read-write values (empty)
2683 pub mod RW {}
2684 }
2685
2686 /// BRK COMP2 input polarity
2687 pub mod BKCMP2P {
2688 /// Offset (11 bits)
2689 pub const offset: u32 = 11;
2690 /// Mask (1 bit: 1 << 11)
2691 pub const mask: u32 = 1 << offset;
2692 /// Read-only values (empty)
2693 pub mod R {}
2694 /// Write-only values (empty)
2695 pub mod W {}
2696 /// Read-write values (empty)
2697 pub mod RW {}
2698 }
2699
2700 /// ETR source selection
2701 pub mod ETRSEL {
2702 /// Offset (14 bits)
2703 pub const offset: u32 = 14;
2704 /// Mask (3 bits: 0b111 << 14)
2705 pub const mask: u32 = 0b111 << offset;
2706 /// Read-only values (empty)
2707 pub mod R {}
2708 /// Write-only values (empty)
2709 pub mod W {}
2710 /// Read-write values (empty)
2711 pub mod RW {}
2712 }
2713}
2714
2715/// DMA address for full transfer
2716pub mod OR3 {
2717
2718 /// BRK2 BKIN input enable
2719 pub mod BK2INE {
2720 /// Offset (0 bits)
2721 pub const offset: u32 = 0;
2722 /// Mask (1 bit: 1 << 0)
2723 pub const mask: u32 = 1 << offset;
2724 /// Read-only values (empty)
2725 pub mod R {}
2726 /// Write-only values (empty)
2727 pub mod W {}
2728 /// Read-write values (empty)
2729 pub mod RW {}
2730 }
2731
2732 /// BRK2 COMP1 enable
2733 pub mod BK2CMP1E {
2734 /// Offset (1 bits)
2735 pub const offset: u32 = 1;
2736 /// Mask (1 bit: 1 << 1)
2737 pub const mask: u32 = 1 << offset;
2738 /// Read-only values (empty)
2739 pub mod R {}
2740 /// Write-only values (empty)
2741 pub mod W {}
2742 /// Read-write values (empty)
2743 pub mod RW {}
2744 }
2745
2746 /// BRK2 COMP2 enable
2747 pub mod BK2CMP2E {
2748 /// Offset (2 bits)
2749 pub const offset: u32 = 2;
2750 /// Mask (1 bit: 1 << 2)
2751 pub const mask: u32 = 1 << offset;
2752 /// Read-only values (empty)
2753 pub mod R {}
2754 /// Write-only values (empty)
2755 pub mod W {}
2756 /// Read-write values (empty)
2757 pub mod RW {}
2758 }
2759
2760 /// BRK2 DFSDM_BREAK3 enable
2761 pub mod BK2DFBK3E {
2762 /// Offset (8 bits)
2763 pub const offset: u32 = 8;
2764 /// Mask (1 bit: 1 << 8)
2765 pub const mask: u32 = 1 << offset;
2766 /// Read-only values (empty)
2767 pub mod R {}
2768 /// Write-only values (empty)
2769 pub mod W {}
2770 /// Read-write values (empty)
2771 pub mod RW {}
2772 }
2773
2774 /// BRK2 BKIN input polarity
2775 pub mod BK2INP {
2776 /// Offset (9 bits)
2777 pub const offset: u32 = 9;
2778 /// Mask (1 bit: 1 << 9)
2779 pub const mask: u32 = 1 << offset;
2780 /// Read-only values (empty)
2781 pub mod R {}
2782 /// Write-only values (empty)
2783 pub mod W {}
2784 /// Read-write values (empty)
2785 pub mod RW {}
2786 }
2787
2788 /// BRK2 COMP1 input polarity
2789 pub mod BK2CMP1P {
2790 /// Offset (10 bits)
2791 pub const offset: u32 = 10;
2792 /// Mask (1 bit: 1 << 10)
2793 pub const mask: u32 = 1 << offset;
2794 /// Read-only values (empty)
2795 pub mod R {}
2796 /// Write-only values (empty)
2797 pub mod W {}
2798 /// Read-write values (empty)
2799 pub mod RW {}
2800 }
2801
2802 /// BRK2 COMP2 input polarity
2803 pub mod BK2CMP2P {
2804 /// Offset (11 bits)
2805 pub const offset: u32 = 11;
2806 /// Mask (1 bit: 1 << 11)
2807 pub const mask: u32 = 1 << offset;
2808 /// Read-only values (empty)
2809 pub mod R {}
2810 /// Write-only values (empty)
2811 pub mod W {}
2812 /// Read-write values (empty)
2813 pub mod RW {}
2814 }
2815}
2816#[repr(C)]
2817pub struct RegisterBlock {
2818 /// control register 1
2819 pub CR1: RWRegister<u32>,
2820
2821 /// control register 2
2822 pub CR2: RWRegister<u32>,
2823
2824 /// slave mode control register
2825 pub SMCR: RWRegister<u32>,
2826
2827 /// DMA/Interrupt enable register
2828 pub DIER: RWRegister<u32>,
2829
2830 /// status register
2831 pub SR: RWRegister<u32>,
2832
2833 /// event generation register
2834 pub EGR: WORegister<u32>,
2835
2836 /// CCMR1_Output and CCMR1_Input
2837 /// CCMR1_Output: capture/compare mode register 1 (output mode)
2838 /// CCMR1_Input: capture/compare mode register 1 (input mode)
2839 pub CCMR1: RWRegister<u32>,
2840
2841 /// CCMR2_Output and CCMR2_Input
2842 /// CCMR2_Output: capture/compare mode register 2 (output mode)
2843 /// CCMR2_Input: capture/compare mode register 2 (input mode)
2844 pub CCMR2: RWRegister<u32>,
2845
2846 /// capture/compare enable register
2847 pub CCER: RWRegister<u32>,
2848
2849 /// counter
2850 pub CNT: RWRegister<u32>,
2851
2852 /// prescaler
2853 pub PSC: RWRegister<u32>,
2854
2855 /// auto-reload register
2856 pub ARR: RWRegister<u32>,
2857
2858 /// repetition counter register
2859 pub RCR: RWRegister<u32>,
2860
2861 /// capture/compare register
2862 pub CCR1: RWRegister<u32>,
2863
2864 /// capture/compare register
2865 pub CCR2: RWRegister<u32>,
2866
2867 /// capture/compare register
2868 pub CCR3: RWRegister<u32>,
2869
2870 /// capture/compare register
2871 pub CCR4: RWRegister<u32>,
2872
2873 /// break and dead-time register
2874 pub BDTR: RWRegister<u32>,
2875
2876 /// DMA control register
2877 pub DCR: RWRegister<u32>,
2878
2879 /// DMA address for full transfer
2880 pub DMAR: RWRegister<u32>,
2881
2882 /// DMA address for full transfer
2883 pub OR1: RWRegister<u32>,
2884
2885 /// capture/compare mode register 2 (output mode)
2886 pub CCMR3_Output: RWRegister<u32>,
2887
2888 /// capture/compare register
2889 pub CCR5: RWRegister<u32>,
2890
2891 /// capture/compare register
2892 pub CCR6: RWRegister<u32>,
2893
2894 /// DMA address for full transfer
2895 pub OR2: RWRegister<u32>,
2896
2897 /// DMA address for full transfer
2898 pub OR3: RWRegister<u32>,
2899}
2900pub struct ResetValues {
2901 pub CR1: u32,
2902 pub CR2: u32,
2903 pub SMCR: u32,
2904 pub DIER: u32,
2905 pub SR: u32,
2906 pub EGR: u32,
2907 pub CCMR1: u32,
2908 pub CCMR2: u32,
2909 pub CCER: u32,
2910 pub CNT: u32,
2911 pub PSC: u32,
2912 pub ARR: u32,
2913 pub RCR: u32,
2914 pub CCR1: u32,
2915 pub CCR2: u32,
2916 pub CCR3: u32,
2917 pub CCR4: u32,
2918 pub BDTR: u32,
2919 pub DCR: u32,
2920 pub DMAR: u32,
2921 pub OR1: u32,
2922 pub CCMR3_Output: u32,
2923 pub CCR5: u32,
2924 pub CCR6: u32,
2925 pub OR2: u32,
2926 pub OR3: u32,
2927}
2928#[cfg(not(feature = "nosync"))]
2929pub struct Instance {
2930 pub(crate) addr: u32,
2931 pub(crate) _marker: PhantomData<*const RegisterBlock>,
2932}
2933#[cfg(not(feature = "nosync"))]
2934impl ::core::ops::Deref for Instance {
2935 type Target = RegisterBlock;
2936 #[inline(always)]
2937 fn deref(&self) -> &RegisterBlock {
2938 unsafe { &*(self.addr as *const _) }
2939 }
2940}
2941#[cfg(feature = "rtic")]
2942unsafe impl Send for Instance {}