stm32ral/stm32l4/peripherals/mpu_v2.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Memory protection unit
4//!
5//! Used by: stm32l4r5, stm32l4r9
6
7use crate::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// MPU type register
12pub mod TYPER {
13
14 /// Separate flag
15 pub mod SEPARATE {
16 /// Offset (0 bits)
17 pub const offset: u32 = 0;
18 /// Mask (1 bit: 1 << 0)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Number of MPU data regions
29 pub mod DREGION {
30 /// Offset (8 bits)
31 pub const offset: u32 = 8;
32 /// Mask (8 bits: 0xff << 8)
33 pub const mask: u32 = 0xff << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// Number of MPU instruction regions
43 pub mod IREGION {
44 /// Offset (16 bits)
45 pub const offset: u32 = 16;
46 /// Mask (8 bits: 0xff << 16)
47 pub const mask: u32 = 0xff << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55}
56
57/// MPU control register
58pub mod CTRL {
59
60 /// Enables the MPU
61 pub mod ENABLE {
62 /// Offset (0 bits)
63 pub const offset: u32 = 0;
64 /// Mask (1 bit: 1 << 0)
65 pub const mask: u32 = 1 << offset;
66 /// Read-only values (empty)
67 pub mod R {}
68 /// Write-only values (empty)
69 pub mod W {}
70 /// Read-write values (empty)
71 pub mod RW {}
72 }
73
74 /// Enables the operation of MPU during hard fault
75 pub mod HFNMIENA {
76 /// Offset (1 bits)
77 pub const offset: u32 = 1;
78 /// Mask (1 bit: 1 << 1)
79 pub const mask: u32 = 1 << offset;
80 /// Read-only values (empty)
81 pub mod R {}
82 /// Write-only values (empty)
83 pub mod W {}
84 /// Read-write values (empty)
85 pub mod RW {}
86 }
87
88 /// Enable priviliged software access to default memory map
89 pub mod PRIVDEFENA {
90 /// Offset (2 bits)
91 pub const offset: u32 = 2;
92 /// Mask (1 bit: 1 << 2)
93 pub const mask: u32 = 1 << offset;
94 /// Read-only values (empty)
95 pub mod R {}
96 /// Write-only values (empty)
97 pub mod W {}
98 /// Read-write values (empty)
99 pub mod RW {}
100 }
101}
102
103/// MPU region number register
104pub mod RNR {
105
106 /// MPU region
107 pub mod REGION {
108 /// Offset (0 bits)
109 pub const offset: u32 = 0;
110 /// Mask (8 bits: 0xff << 0)
111 pub const mask: u32 = 0xff << offset;
112 /// Read-only values (empty)
113 pub mod R {}
114 /// Write-only values (empty)
115 pub mod W {}
116 /// Read-write values (empty)
117 pub mod RW {}
118 }
119}
120
121/// MPU region base address register
122pub mod RBAR {
123
124 /// MPU region field
125 pub mod REGION {
126 /// Offset (0 bits)
127 pub const offset: u32 = 0;
128 /// Mask (4 bits: 0b1111 << 0)
129 pub const mask: u32 = 0b1111 << offset;
130 /// Read-only values (empty)
131 pub mod R {}
132 /// Write-only values (empty)
133 pub mod W {}
134 /// Read-write values (empty)
135 pub mod RW {}
136 }
137
138 /// MPU region number valid
139 pub mod VALID {
140 /// Offset (4 bits)
141 pub const offset: u32 = 4;
142 /// Mask (1 bit: 1 << 4)
143 pub const mask: u32 = 1 << offset;
144 /// Read-only values (empty)
145 pub mod R {}
146 /// Write-only values (empty)
147 pub mod W {}
148 /// Read-write values (empty)
149 pub mod RW {}
150 }
151
152 /// Region base address field
153 pub mod ADDR {
154 /// Offset (5 bits)
155 pub const offset: u32 = 5;
156 /// Mask (27 bits: 0x7ffffff << 5)
157 pub const mask: u32 = 0x7ffffff << offset;
158 /// Read-only values (empty)
159 pub mod R {}
160 /// Write-only values (empty)
161 pub mod W {}
162 /// Read-write values (empty)
163 pub mod RW {}
164 }
165}
166
167/// MPU region attribute and size register
168pub mod RASR {
169
170 /// Region enable bit.
171 pub mod ENABLE {
172 /// Offset (0 bits)
173 pub const offset: u32 = 0;
174 /// Mask (1 bit: 1 << 0)
175 pub const mask: u32 = 1 << offset;
176 /// Read-only values (empty)
177 pub mod R {}
178 /// Write-only values (empty)
179 pub mod W {}
180 /// Read-write values (empty)
181 pub mod RW {}
182 }
183
184 /// Size of the MPU protection region
185 pub mod SIZE {
186 /// Offset (1 bits)
187 pub const offset: u32 = 1;
188 /// Mask (5 bits: 0b11111 << 1)
189 pub const mask: u32 = 0b11111 << offset;
190 /// Read-only values (empty)
191 pub mod R {}
192 /// Write-only values (empty)
193 pub mod W {}
194 /// Read-write values (empty)
195 pub mod RW {}
196 }
197
198 /// Subregion disable bits
199 pub mod SRD {
200 /// Offset (8 bits)
201 pub const offset: u32 = 8;
202 /// Mask (8 bits: 0xff << 8)
203 pub const mask: u32 = 0xff << offset;
204 /// Read-only values (empty)
205 pub mod R {}
206 /// Write-only values (empty)
207 pub mod W {}
208 /// Read-write values (empty)
209 pub mod RW {}
210 }
211
212 /// memory attribute
213 pub mod B {
214 /// Offset (16 bits)
215 pub const offset: u32 = 16;
216 /// Mask (1 bit: 1 << 16)
217 pub const mask: u32 = 1 << offset;
218 /// Read-only values (empty)
219 pub mod R {}
220 /// Write-only values (empty)
221 pub mod W {}
222 /// Read-write values (empty)
223 pub mod RW {}
224 }
225
226 /// memory attribute
227 pub mod C {
228 /// Offset (17 bits)
229 pub const offset: u32 = 17;
230 /// Mask (1 bit: 1 << 17)
231 pub const mask: u32 = 1 << offset;
232 /// Read-only values (empty)
233 pub mod R {}
234 /// Write-only values (empty)
235 pub mod W {}
236 /// Read-write values (empty)
237 pub mod RW {}
238 }
239
240 /// Shareable memory attribute
241 pub mod S {
242 /// Offset (18 bits)
243 pub const offset: u32 = 18;
244 /// Mask (1 bit: 1 << 18)
245 pub const mask: u32 = 1 << offset;
246 /// Read-only values (empty)
247 pub mod R {}
248 /// Write-only values (empty)
249 pub mod W {}
250 /// Read-write values (empty)
251 pub mod RW {}
252 }
253
254 /// memory attribute
255 pub mod TEX {
256 /// Offset (19 bits)
257 pub const offset: u32 = 19;
258 /// Mask (3 bits: 0b111 << 19)
259 pub const mask: u32 = 0b111 << offset;
260 /// Read-only values (empty)
261 pub mod R {}
262 /// Write-only values (empty)
263 pub mod W {}
264 /// Read-write values (empty)
265 pub mod RW {}
266 }
267
268 /// Access permission
269 pub mod AP {
270 /// Offset (24 bits)
271 pub const offset: u32 = 24;
272 /// Mask (3 bits: 0b111 << 24)
273 pub const mask: u32 = 0b111 << offset;
274 /// Read-only values (empty)
275 pub mod R {}
276 /// Write-only values (empty)
277 pub mod W {}
278 /// Read-write values (empty)
279 pub mod RW {}
280 }
281
282 /// Instruction access disable bit
283 pub mod XN {
284 /// Offset (28 bits)
285 pub const offset: u32 = 28;
286 /// Mask (1 bit: 1 << 28)
287 pub const mask: u32 = 1 << offset;
288 /// Read-only values (empty)
289 pub mod R {}
290 /// Write-only values (empty)
291 pub mod W {}
292 /// Read-write values (empty)
293 pub mod RW {}
294 }
295}
296#[repr(C)]
297pub struct RegisterBlock {
298 /// MPU type register
299 pub TYPER: RORegister<u32>,
300
301 /// MPU control register
302 pub CTRL: RWRegister<u32>,
303
304 /// MPU region number register
305 pub RNR: RWRegister<u32>,
306
307 /// MPU region base address register
308 pub RBAR: RWRegister<u32>,
309
310 /// MPU region attribute and size register
311 pub RASR: RWRegister<u32>,
312}
313pub struct ResetValues {
314 pub TYPER: u32,
315 pub CTRL: u32,
316 pub RNR: u32,
317 pub RBAR: u32,
318 pub RASR: u32,
319}
320#[cfg(not(feature = "nosync"))]
321pub struct Instance {
322 pub(crate) addr: u32,
323 pub(crate) _marker: PhantomData<*const RegisterBlock>,
324}
325#[cfg(not(feature = "nosync"))]
326impl ::core::ops::Deref for Instance {
327 type Target = RegisterBlock;
328 #[inline(always)]
329 fn deref(&self) -> &RegisterBlock {
330 unsafe { &*(self.addr as *const _) }
331 }
332}
333#[cfg(feature = "rtic")]
334unsafe impl Send for Instance {}