stm32ral/stm32l1/peripherals/tim2.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General-purpose timers
4//!
5//! Used by: stm32l100, stm32l151, stm32l162
6
7use crate::RWRegister;
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Clock division
15 pub mod CKD {
16 /// Offset (8 bits)
17 pub const offset: u32 = 8;
18 /// Mask (2 bits: 0b11 << 8)
19 pub const mask: u32 = 0b11 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b00: t_DTS = t_CK_INT
28 pub const Div1: u32 = 0b00;
29
30 /// 0b01: t_DTS = 2 × t_CK_INT
31 pub const Div2: u32 = 0b01;
32
33 /// 0b10: t_DTS = 4 × t_CK_INT
34 pub const Div4: u32 = 0b10;
35 }
36 }
37
38 /// Auto-reload preload enable
39 pub mod ARPE {
40 /// Offset (7 bits)
41 pub const offset: u32 = 7;
42 /// Mask (1 bit: 1 << 7)
43 pub const mask: u32 = 1 << offset;
44 /// Read-only values (empty)
45 pub mod R {}
46 /// Write-only values (empty)
47 pub mod W {}
48 /// Read-write values
49 pub mod RW {
50
51 /// 0b0: TIMx_APRR register is not buffered
52 pub const Disabled: u32 = 0b0;
53
54 /// 0b1: TIMx_APRR register is buffered
55 pub const Enabled: u32 = 0b1;
56 }
57 }
58
59 /// Center-aligned mode selection
60 pub mod CMS {
61 /// Offset (5 bits)
62 pub const offset: u32 = 5;
63 /// Mask (2 bits: 0b11 << 5)
64 pub const mask: u32 = 0b11 << offset;
65 /// Read-only values (empty)
66 pub mod R {}
67 /// Write-only values (empty)
68 pub mod W {}
69 /// Read-write values
70 pub mod RW {
71
72 /// 0b00: The counter counts up or down depending on the direction bit
73 pub const EdgeAligned: u32 = 0b00;
74
75 /// 0b01: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
76 pub const CenterAligned1: u32 = 0b01;
77
78 /// 0b10: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
79 pub const CenterAligned2: u32 = 0b10;
80
81 /// 0b11: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
82 pub const CenterAligned3: u32 = 0b11;
83 }
84 }
85
86 /// Direction
87 pub mod DIR {
88 /// Offset (4 bits)
89 pub const offset: u32 = 4;
90 /// Mask (1 bit: 1 << 4)
91 pub const mask: u32 = 1 << offset;
92 /// Read-only values (empty)
93 pub mod R {}
94 /// Write-only values (empty)
95 pub mod W {}
96 /// Read-write values
97 pub mod RW {
98
99 /// 0b0: Counter used as upcounter
100 pub const Up: u32 = 0b0;
101
102 /// 0b1: Counter used as downcounter
103 pub const Down: u32 = 0b1;
104 }
105 }
106
107 /// One-pulse mode
108 pub mod OPM {
109 /// Offset (3 bits)
110 pub const offset: u32 = 3;
111 /// Mask (1 bit: 1 << 3)
112 pub const mask: u32 = 1 << offset;
113 /// Read-only values (empty)
114 pub mod R {}
115 /// Write-only values (empty)
116 pub mod W {}
117 /// Read-write values
118 pub mod RW {
119
120 /// 0b0: Counter is not stopped at update event
121 pub const Disabled: u32 = 0b0;
122
123 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
124 pub const Enabled: u32 = 0b1;
125 }
126 }
127
128 /// Update request source
129 pub mod URS {
130 /// Offset (2 bits)
131 pub const offset: u32 = 2;
132 /// Mask (1 bit: 1 << 2)
133 pub const mask: u32 = 1 << offset;
134 /// Read-only values (empty)
135 pub mod R {}
136 /// Write-only values (empty)
137 pub mod W {}
138 /// Read-write values
139 pub mod RW {
140
141 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
142 pub const AnyEvent: u32 = 0b0;
143
144 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
145 pub const CounterOnly: u32 = 0b1;
146 }
147 }
148
149 /// Update disable
150 pub mod UDIS {
151 /// Offset (1 bits)
152 pub const offset: u32 = 1;
153 /// Mask (1 bit: 1 << 1)
154 pub const mask: u32 = 1 << offset;
155 /// Read-only values (empty)
156 pub mod R {}
157 /// Write-only values (empty)
158 pub mod W {}
159 /// Read-write values
160 pub mod RW {
161
162 /// 0b0: Update event enabled
163 pub const Enabled: u32 = 0b0;
164
165 /// 0b1: Update event disabled
166 pub const Disabled: u32 = 0b1;
167 }
168 }
169
170 /// Counter enable
171 pub mod CEN {
172 /// Offset (0 bits)
173 pub const offset: u32 = 0;
174 /// Mask (1 bit: 1 << 0)
175 pub const mask: u32 = 1 << offset;
176 /// Read-only values (empty)
177 pub mod R {}
178 /// Write-only values (empty)
179 pub mod W {}
180 /// Read-write values
181 pub mod RW {
182
183 /// 0b0: Counter disabled
184 pub const Disabled: u32 = 0b0;
185
186 /// 0b1: Counter enabled
187 pub const Enabled: u32 = 0b1;
188 }
189 }
190}
191
192/// control register 2
193pub mod CR2 {
194
195 /// TI1 selection
196 pub mod TI1S {
197 /// Offset (7 bits)
198 pub const offset: u32 = 7;
199 /// Mask (1 bit: 1 << 7)
200 pub const mask: u32 = 1 << offset;
201 /// Read-only values (empty)
202 pub mod R {}
203 /// Write-only values (empty)
204 pub mod W {}
205 /// Read-write values
206 pub mod RW {
207
208 /// 0b0: The TIMx_CH1 pin is connected to TI1 input
209 pub const Normal: u32 = 0b0;
210
211 /// 0b1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
212 pub const XOR: u32 = 0b1;
213 }
214 }
215
216 /// Master mode selection
217 pub mod MMS {
218 /// Offset (4 bits)
219 pub const offset: u32 = 4;
220 /// Mask (3 bits: 0b111 << 4)
221 pub const mask: u32 = 0b111 << offset;
222 /// Read-only values (empty)
223 pub mod R {}
224 /// Write-only values (empty)
225 pub mod W {}
226 /// Read-write values
227 pub mod RW {
228
229 /// 0b000: The UG bit from the TIMx_EGR register is used as trigger output
230 pub const Reset: u32 = 0b000;
231
232 /// 0b001: The counter enable signal, CNT_EN, is used as trigger output
233 pub const Enable: u32 = 0b001;
234
235 /// 0b010: The update event is selected as trigger output
236 pub const Update: u32 = 0b010;
237
238 /// 0b011: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
239 pub const ComparePulse: u32 = 0b011;
240
241 /// 0b100: OC1REF signal is used as trigger output
242 pub const CompareOC1: u32 = 0b100;
243
244 /// 0b101: OC2REF signal is used as trigger output
245 pub const CompareOC2: u32 = 0b101;
246
247 /// 0b110: OC3REF signal is used as trigger output
248 pub const CompareOC3: u32 = 0b110;
249
250 /// 0b111: OC4REF signal is used as trigger output
251 pub const CompareOC4: u32 = 0b111;
252 }
253 }
254
255 /// Capture/compare DMA selection
256 pub mod CCDS {
257 /// Offset (3 bits)
258 pub const offset: u32 = 3;
259 /// Mask (1 bit: 1 << 3)
260 pub const mask: u32 = 1 << offset;
261 /// Read-only values (empty)
262 pub mod R {}
263 /// Write-only values (empty)
264 pub mod W {}
265 /// Read-write values
266 pub mod RW {
267
268 /// 0b0: CCx DMA request sent when CCx event occurs
269 pub const OnCompare: u32 = 0b0;
270
271 /// 0b1: CCx DMA request sent when update event occurs
272 pub const OnUpdate: u32 = 0b1;
273 }
274 }
275}
276
277/// slave mode control register
278pub mod SMCR {
279
280 /// External trigger polarity
281 pub mod ETP {
282 /// Offset (15 bits)
283 pub const offset: u32 = 15;
284 /// Mask (1 bit: 1 << 15)
285 pub const mask: u32 = 1 << offset;
286 /// Read-only values (empty)
287 pub mod R {}
288 /// Write-only values (empty)
289 pub mod W {}
290 /// Read-write values
291 pub mod RW {
292
293 /// 0b0: ETR is noninverted, active at high level or rising edge
294 pub const NotInverted: u32 = 0b0;
295
296 /// 0b1: ETR is inverted, active at low level or falling edge
297 pub const Inverted: u32 = 0b1;
298 }
299 }
300
301 /// External clock enable
302 pub mod ECE {
303 /// Offset (14 bits)
304 pub const offset: u32 = 14;
305 /// Mask (1 bit: 1 << 14)
306 pub const mask: u32 = 1 << offset;
307 /// Read-only values (empty)
308 pub mod R {}
309 /// Write-only values (empty)
310 pub mod W {}
311 /// Read-write values
312 pub mod RW {
313
314 /// 0b0: External clock mode 2 disabled
315 pub const Disabled: u32 = 0b0;
316
317 /// 0b1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
318 pub const Enabled: u32 = 0b1;
319 }
320 }
321
322 /// External trigger prescaler
323 pub mod ETPS {
324 /// Offset (12 bits)
325 pub const offset: u32 = 12;
326 /// Mask (2 bits: 0b11 << 12)
327 pub const mask: u32 = 0b11 << offset;
328 /// Read-only values (empty)
329 pub mod R {}
330 /// Write-only values (empty)
331 pub mod W {}
332 /// Read-write values
333 pub mod RW {
334
335 /// 0b00: Prescaler OFF
336 pub const Div1: u32 = 0b00;
337
338 /// 0b01: ETRP frequency divided by 2
339 pub const Div2: u32 = 0b01;
340
341 /// 0b10: ETRP frequency divided by 4
342 pub const Div4: u32 = 0b10;
343
344 /// 0b11: ETRP frequency divided by 8
345 pub const Div8: u32 = 0b11;
346 }
347 }
348
349 /// External trigger filter
350 pub mod ETF {
351 /// Offset (8 bits)
352 pub const offset: u32 = 8;
353 /// Mask (4 bits: 0b1111 << 8)
354 pub const mask: u32 = 0b1111 << offset;
355 /// Read-only values (empty)
356 pub mod R {}
357 /// Write-only values (empty)
358 pub mod W {}
359 /// Read-write values
360 pub mod RW {
361
362 /// 0b0000: No filter, sampling is done at fDTS
363 pub const NoFilter: u32 = 0b0000;
364
365 /// 0b0001: fSAMPLING=fCK_INT, N=2
366 pub const FCK_INT_N2: u32 = 0b0001;
367
368 /// 0b0010: fSAMPLING=fCK_INT, N=4
369 pub const FCK_INT_N4: u32 = 0b0010;
370
371 /// 0b0011: fSAMPLING=fCK_INT, N=8
372 pub const FCK_INT_N8: u32 = 0b0011;
373
374 /// 0b0100: fSAMPLING=fDTS/2, N=6
375 pub const FDTS_Div2_N6: u32 = 0b0100;
376
377 /// 0b0101: fSAMPLING=fDTS/2, N=8
378 pub const FDTS_Div2_N8: u32 = 0b0101;
379
380 /// 0b0110: fSAMPLING=fDTS/4, N=6
381 pub const FDTS_Div4_N6: u32 = 0b0110;
382
383 /// 0b0111: fSAMPLING=fDTS/4, N=8
384 pub const FDTS_Div4_N8: u32 = 0b0111;
385
386 /// 0b1000: fSAMPLING=fDTS/8, N=6
387 pub const FDTS_Div8_N6: u32 = 0b1000;
388
389 /// 0b1001: fSAMPLING=fDTS/8, N=8
390 pub const FDTS_Div8_N8: u32 = 0b1001;
391
392 /// 0b1010: fSAMPLING=fDTS/16, N=5
393 pub const FDTS_Div16_N5: u32 = 0b1010;
394
395 /// 0b1011: fSAMPLING=fDTS/16, N=6
396 pub const FDTS_Div16_N6: u32 = 0b1011;
397
398 /// 0b1100: fSAMPLING=fDTS/16, N=8
399 pub const FDTS_Div16_N8: u32 = 0b1100;
400
401 /// 0b1101: fSAMPLING=fDTS/32, N=5
402 pub const FDTS_Div32_N5: u32 = 0b1101;
403
404 /// 0b1110: fSAMPLING=fDTS/32, N=6
405 pub const FDTS_Div32_N6: u32 = 0b1110;
406
407 /// 0b1111: fSAMPLING=fDTS/32, N=8
408 pub const FDTS_Div32_N8: u32 = 0b1111;
409 }
410 }
411
412 /// Master/Slave mode
413 pub mod MSM {
414 /// Offset (7 bits)
415 pub const offset: u32 = 7;
416 /// Mask (1 bit: 1 << 7)
417 pub const mask: u32 = 1 << offset;
418 /// Read-only values (empty)
419 pub mod R {}
420 /// Write-only values (empty)
421 pub mod W {}
422 /// Read-write values
423 pub mod RW {
424
425 /// 0b0: No action
426 pub const NoSync: u32 = 0b0;
427
428 /// 0b1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
429 pub const Sync: u32 = 0b1;
430 }
431 }
432
433 /// Trigger selection
434 pub mod TS {
435 /// Offset (4 bits)
436 pub const offset: u32 = 4;
437 /// Mask (3 bits: 0b111 << 4)
438 pub const mask: u32 = 0b111 << offset;
439 /// Read-only values (empty)
440 pub mod R {}
441 /// Write-only values (empty)
442 pub mod W {}
443 /// Read-write values
444 pub mod RW {
445
446 /// 0b000: Internal Trigger 0 (ITR0)
447 pub const ITR0: u32 = 0b000;
448
449 /// 0b001: Internal Trigger 1 (ITR1)
450 pub const ITR1: u32 = 0b001;
451
452 /// 0b010: Internal Trigger 2 (ITR2)
453 pub const ITR2: u32 = 0b010;
454
455 /// 0b100: TI1 Edge Detector (TI1F_ED)
456 pub const TI1F_ED: u32 = 0b100;
457
458 /// 0b101: Filtered Timer Input 1 (TI1FP1)
459 pub const TI1FP1: u32 = 0b101;
460
461 /// 0b110: Filtered Timer Input 2 (TI2FP2)
462 pub const TI2FP2: u32 = 0b110;
463
464 /// 0b111: External Trigger input (ETRF)
465 pub const ETRF: u32 = 0b111;
466 }
467 }
468
469 /// OCREF clear selection
470 pub mod OCCS {
471 /// Offset (3 bits)
472 pub const offset: u32 = 3;
473 /// Mask (1 bit: 1 << 3)
474 pub const mask: u32 = 1 << offset;
475 /// Read-only values (empty)
476 pub mod R {}
477 /// Write-only values (empty)
478 pub mod W {}
479 /// Read-write values (empty)
480 pub mod RW {}
481 }
482
483 /// Slave mode selection
484 pub mod SMS {
485 /// Offset (0 bits)
486 pub const offset: u32 = 0;
487 /// Mask (3 bits: 0b111 << 0)
488 pub const mask: u32 = 0b111 << offset;
489 /// Read-only values (empty)
490 pub mod R {}
491 /// Write-only values (empty)
492 pub mod W {}
493 /// Read-write values
494 pub mod RW {
495
496 /// 0b000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
497 pub const Disabled: u32 = 0b000;
498
499 /// 0b001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
500 pub const Encoder_Mode_1: u32 = 0b001;
501
502 /// 0b010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
503 pub const Encoder_Mode_2: u32 = 0b010;
504
505 /// 0b011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
506 pub const Encoder_Mode_3: u32 = 0b011;
507
508 /// 0b100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
509 pub const Reset_Mode: u32 = 0b100;
510
511 /// 0b101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
512 pub const Gated_Mode: u32 = 0b101;
513
514 /// 0b110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
515 pub const Trigger_Mode: u32 = 0b110;
516
517 /// 0b111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
518 pub const Ext_Clock_Mode: u32 = 0b111;
519 }
520 }
521}
522
523/// Interrupt enable register
524pub mod DIER {
525
526 /// Trigger DMA request enable
527 pub mod TDE {
528 /// Offset (14 bits)
529 pub const offset: u32 = 14;
530 /// Mask (1 bit: 1 << 14)
531 pub const mask: u32 = 1 << offset;
532 /// Read-only values (empty)
533 pub mod R {}
534 /// Write-only values (empty)
535 pub mod W {}
536 /// Read-write values
537 pub mod RW {
538
539 /// 0b0: Trigger DMA request disabled
540 pub const Disabled: u32 = 0b0;
541
542 /// 0b1: Trigger DMA request enabled
543 pub const Enabled: u32 = 0b1;
544 }
545 }
546
547 /// Capture/Compare 4 DMA request enable
548 pub mod CC4DE {
549 /// Offset (12 bits)
550 pub const offset: u32 = 12;
551 /// Mask (1 bit: 1 << 12)
552 pub const mask: u32 = 1 << offset;
553 /// Read-only values (empty)
554 pub mod R {}
555 /// Write-only values (empty)
556 pub mod W {}
557 /// Read-write values
558 pub mod RW {
559
560 /// 0b0: CCx DMA request disabled
561 pub const Disabled: u32 = 0b0;
562
563 /// 0b1: CCx DMA request enabled
564 pub const Enabled: u32 = 0b1;
565 }
566 }
567
568 /// Capture/Compare 3 DMA request enable
569 pub mod CC3DE {
570 /// Offset (11 bits)
571 pub const offset: u32 = 11;
572 /// Mask (1 bit: 1 << 11)
573 pub const mask: u32 = 1 << offset;
574 /// Read-only values (empty)
575 pub mod R {}
576 /// Write-only values (empty)
577 pub mod W {}
578 pub use super::CC4DE::RW;
579 }
580
581 /// Capture/Compare 2 DMA request enable
582 pub mod CC2DE {
583 /// Offset (10 bits)
584 pub const offset: u32 = 10;
585 /// Mask (1 bit: 1 << 10)
586 pub const mask: u32 = 1 << offset;
587 /// Read-only values (empty)
588 pub mod R {}
589 /// Write-only values (empty)
590 pub mod W {}
591 pub use super::CC4DE::RW;
592 }
593
594 /// Capture/Compare 1 DMA request enable
595 pub mod CC1DE {
596 /// Offset (9 bits)
597 pub const offset: u32 = 9;
598 /// Mask (1 bit: 1 << 9)
599 pub const mask: u32 = 1 << offset;
600 /// Read-only values (empty)
601 pub mod R {}
602 /// Write-only values (empty)
603 pub mod W {}
604 pub use super::CC4DE::RW;
605 }
606
607 /// Update DMA request enable
608 pub mod UDE {
609 /// Offset (8 bits)
610 pub const offset: u32 = 8;
611 /// Mask (1 bit: 1 << 8)
612 pub const mask: u32 = 1 << offset;
613 /// Read-only values (empty)
614 pub mod R {}
615 /// Write-only values (empty)
616 pub mod W {}
617 /// Read-write values
618 pub mod RW {
619
620 /// 0b0: Update DMA request disabled
621 pub const Disabled: u32 = 0b0;
622
623 /// 0b1: Update DMA request enabled
624 pub const Enabled: u32 = 0b1;
625 }
626 }
627
628 /// Trigger interrupt enable
629 pub mod TIE {
630 /// Offset (6 bits)
631 pub const offset: u32 = 6;
632 /// Mask (1 bit: 1 << 6)
633 pub const mask: u32 = 1 << offset;
634 /// Read-only values (empty)
635 pub mod R {}
636 /// Write-only values (empty)
637 pub mod W {}
638 /// Read-write values
639 pub mod RW {
640
641 /// 0b0: Trigger interrupt disabled
642 pub const Disabled: u32 = 0b0;
643
644 /// 0b1: Trigger interrupt enabled
645 pub const Enabled: u32 = 0b1;
646 }
647 }
648
649 /// Capture/Compare 4 interrupt enable
650 pub mod CC4IE {
651 /// Offset (4 bits)
652 pub const offset: u32 = 4;
653 /// Mask (1 bit: 1 << 4)
654 pub const mask: u32 = 1 << offset;
655 /// Read-only values (empty)
656 pub mod R {}
657 /// Write-only values (empty)
658 pub mod W {}
659 /// Read-write values
660 pub mod RW {
661
662 /// 0b0: CCx interrupt disabled
663 pub const Disabled: u32 = 0b0;
664
665 /// 0b1: CCx interrupt enabled
666 pub const Enabled: u32 = 0b1;
667 }
668 }
669
670 /// Capture/Compare 3 interrupt enable
671 pub mod CC3IE {
672 /// Offset (3 bits)
673 pub const offset: u32 = 3;
674 /// Mask (1 bit: 1 << 3)
675 pub const mask: u32 = 1 << offset;
676 /// Read-only values (empty)
677 pub mod R {}
678 /// Write-only values (empty)
679 pub mod W {}
680 pub use super::CC4IE::RW;
681 }
682
683 /// Capture/Compare 2 interrupt enable
684 pub mod CC2IE {
685 /// Offset (2 bits)
686 pub const offset: u32 = 2;
687 /// Mask (1 bit: 1 << 2)
688 pub const mask: u32 = 1 << offset;
689 /// Read-only values (empty)
690 pub mod R {}
691 /// Write-only values (empty)
692 pub mod W {}
693 pub use super::CC4IE::RW;
694 }
695
696 /// Capture/Compare 1 interrupt enable
697 pub mod CC1IE {
698 /// Offset (1 bits)
699 pub const offset: u32 = 1;
700 /// Mask (1 bit: 1 << 1)
701 pub const mask: u32 = 1 << offset;
702 /// Read-only values (empty)
703 pub mod R {}
704 /// Write-only values (empty)
705 pub mod W {}
706 pub use super::CC4IE::RW;
707 }
708
709 /// Update interrupt enable
710 pub mod UIE {
711 /// Offset (0 bits)
712 pub const offset: u32 = 0;
713 /// Mask (1 bit: 1 << 0)
714 pub const mask: u32 = 1 << offset;
715 /// Read-only values (empty)
716 pub mod R {}
717 /// Write-only values (empty)
718 pub mod W {}
719 /// Read-write values
720 pub mod RW {
721
722 /// 0b0: Update interrupt disabled
723 pub const Disabled: u32 = 0b0;
724
725 /// 0b1: Update interrupt enabled
726 pub const Enabled: u32 = 0b1;
727 }
728 }
729}
730
731/// status register
732pub mod SR {
733
734 /// Capture/compare 1 overcapture flag
735 pub mod CC4OF {
736 /// Offset (12 bits)
737 pub const offset: u32 = 12;
738 /// Mask (1 bit: 1 << 12)
739 pub const mask: u32 = 1 << offset;
740 /// Read-only values
741 pub mod R {
742
743 /// 0b1: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
744 pub const Overcapture: u32 = 0b1;
745 }
746 /// Write-only values
747 pub mod W {
748
749 /// 0b0: Clear flag
750 pub const Clear: u32 = 0b0;
751 }
752 /// Read-write values (empty)
753 pub mod RW {}
754 }
755
756 /// Capture/compare 3 overcapture flag
757 pub mod CC3OF {
758 /// Offset (11 bits)
759 pub const offset: u32 = 11;
760 /// Mask (1 bit: 1 << 11)
761 pub const mask: u32 = 1 << offset;
762 pub use super::CC4OF::R;
763 pub use super::CC4OF::W;
764 /// Read-write values (empty)
765 pub mod RW {}
766 }
767
768 /// Capture/compare 2 overcapture flag
769 pub mod CC2OF {
770 /// Offset (10 bits)
771 pub const offset: u32 = 10;
772 /// Mask (1 bit: 1 << 10)
773 pub const mask: u32 = 1 << offset;
774 pub use super::CC4OF::R;
775 pub use super::CC4OF::W;
776 /// Read-write values (empty)
777 pub mod RW {}
778 }
779
780 /// Capture/compare 1 overcapture flag
781 pub mod CC1OF {
782 /// Offset (9 bits)
783 pub const offset: u32 = 9;
784 /// Mask (1 bit: 1 << 9)
785 pub const mask: u32 = 1 << offset;
786 pub use super::CC4OF::R;
787 pub use super::CC4OF::W;
788 /// Read-write values (empty)
789 pub mod RW {}
790 }
791
792 /// Trigger interrupt flag
793 pub mod TIF {
794 /// Offset (6 bits)
795 pub const offset: u32 = 6;
796 /// Mask (1 bit: 1 << 6)
797 pub const mask: u32 = 1 << offset;
798 /// Read-only values
799 pub mod R {
800
801 /// 0b0: No trigger event occurred
802 pub const NoTrigger: u32 = 0b0;
803
804 /// 0b1: Trigger interrupt pending
805 pub const Trigger: u32 = 0b1;
806 }
807 pub use super::CC4OF::W;
808 /// Read-write values (empty)
809 pub mod RW {}
810 }
811
812 /// Capture/Compare 4 interrupt flag
813 pub mod CC4IF {
814 /// Offset (4 bits)
815 pub const offset: u32 = 4;
816 /// Mask (1 bit: 1 << 4)
817 pub const mask: u32 = 1 << offset;
818 /// Read-only values
819 pub mod R {
820
821 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
822 pub const Match: u32 = 0b1;
823 }
824 pub use super::CC4OF::W;
825 /// Read-write values (empty)
826 pub mod RW {}
827 }
828
829 /// Capture/Compare 3 interrupt flag
830 pub mod CC3IF {
831 /// Offset (3 bits)
832 pub const offset: u32 = 3;
833 /// Mask (1 bit: 1 << 3)
834 pub const mask: u32 = 1 << offset;
835 /// Read-only values
836 pub mod R {
837
838 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
839 pub const Match: u32 = 0b1;
840 }
841 pub use super::CC4OF::W;
842 /// Read-write values (empty)
843 pub mod RW {}
844 }
845
846 /// Capture/Compare 2 interrupt flag
847 pub mod CC2IF {
848 /// Offset (2 bits)
849 pub const offset: u32 = 2;
850 /// Mask (1 bit: 1 << 2)
851 pub const mask: u32 = 1 << offset;
852 /// Read-only values
853 pub mod R {
854
855 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
856 pub const Match: u32 = 0b1;
857 }
858 pub use super::CC4OF::W;
859 /// Read-write values (empty)
860 pub mod RW {}
861 }
862
863 /// Capture/Compare 1 interrupt flag
864 pub mod CC1IF {
865 /// Offset (1 bits)
866 pub const offset: u32 = 1;
867 /// Mask (1 bit: 1 << 1)
868 pub const mask: u32 = 1 << offset;
869 /// Read-only values
870 pub mod R {
871
872 /// 0b1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
873 pub const Match: u32 = 0b1;
874 }
875 pub use super::CC4OF::W;
876 /// Read-write values (empty)
877 pub mod RW {}
878 }
879
880 /// Update interrupt flag
881 pub mod UIF {
882 /// Offset (0 bits)
883 pub const offset: u32 = 0;
884 /// Mask (1 bit: 1 << 0)
885 pub const mask: u32 = 1 << offset;
886 /// Read-only values (empty)
887 pub mod R {}
888 /// Write-only values (empty)
889 pub mod W {}
890 /// Read-write values
891 pub mod RW {
892
893 /// 0b0: No update occurred
894 pub const Clear: u32 = 0b0;
895
896 /// 0b1: Update interrupt pending.
897 pub const UpdatePending: u32 = 0b1;
898 }
899 }
900}
901
902/// event generation register
903pub mod EGR {
904
905 /// Trigger generation
906 pub mod TG {
907 /// Offset (6 bits)
908 pub const offset: u32 = 6;
909 /// Mask (1 bit: 1 << 6)
910 pub const mask: u32 = 1 << offset;
911 /// Read-only values (empty)
912 pub mod R {}
913 /// Write-only values
914 pub mod W {
915
916 /// 0b1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
917 pub const Trigger: u32 = 0b1;
918 }
919 /// Read-write values (empty)
920 pub mod RW {}
921 }
922
923 /// Capture/compare 4 generation
924 pub mod CC4G {
925 /// Offset (4 bits)
926 pub const offset: u32 = 4;
927 /// Mask (1 bit: 1 << 4)
928 pub const mask: u32 = 1 << offset;
929 /// Read-only values (empty)
930 pub mod R {}
931 /// Write-only values
932 pub mod W {
933
934 /// 0b1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
935 pub const Trigger: u32 = 0b1;
936 }
937 /// Read-write values (empty)
938 pub mod RW {}
939 }
940
941 /// Capture/compare 3 generation
942 pub mod CC3G {
943 /// Offset (3 bits)
944 pub const offset: u32 = 3;
945 /// Mask (1 bit: 1 << 3)
946 pub const mask: u32 = 1 << offset;
947 /// Read-only values (empty)
948 pub mod R {}
949 pub use super::CC4G::W;
950 /// Read-write values (empty)
951 pub mod RW {}
952 }
953
954 /// Capture/compare 2 generation
955 pub mod CC2G {
956 /// Offset (2 bits)
957 pub const offset: u32 = 2;
958 /// Mask (1 bit: 1 << 2)
959 pub const mask: u32 = 1 << offset;
960 /// Read-only values (empty)
961 pub mod R {}
962 pub use super::CC4G::W;
963 /// Read-write values (empty)
964 pub mod RW {}
965 }
966
967 /// Capture/compare 1 generation
968 pub mod CC1G {
969 /// Offset (1 bits)
970 pub const offset: u32 = 1;
971 /// Mask (1 bit: 1 << 1)
972 pub const mask: u32 = 1 << offset;
973 /// Read-only values (empty)
974 pub mod R {}
975 pub use super::CC4G::W;
976 /// Read-write values (empty)
977 pub mod RW {}
978 }
979
980 /// Update generation
981 pub mod UG {
982 /// Offset (0 bits)
983 pub const offset: u32 = 0;
984 /// Mask (1 bit: 1 << 0)
985 pub const mask: u32 = 1 << offset;
986 /// Read-only values (empty)
987 pub mod R {}
988 /// Write-only values (empty)
989 pub mod W {}
990 /// Read-write values
991 pub mod RW {
992
993 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
994 pub const Update: u32 = 0b1;
995 }
996 }
997}
998
999/// CCMR1_Output and CCMR1_Input
1000/// CCMR1_Output: capture/compare mode register 1
1001/// CCMR1_Input: capture/compare mode register 1 (input mode)
1002pub mod CCMR1 {
1003
1004 /// Output compare 2 clear enable
1005 pub mod OC2CE {
1006 /// Offset (15 bits)
1007 pub const offset: u32 = 15;
1008 /// Mask (1 bit: 1 << 15)
1009 pub const mask: u32 = 1 << offset;
1010 /// Read-only values (empty)
1011 pub mod R {}
1012 /// Write-only values (empty)
1013 pub mod W {}
1014 /// Read-write values (empty)
1015 pub mod RW {}
1016 }
1017
1018 /// Output compare 2 mode
1019 pub mod OC2M {
1020 /// Offset (12 bits)
1021 pub const offset: u32 = 12;
1022 /// Mask (3 bits: 0b111 << 12)
1023 pub const mask: u32 = 0b111 << offset;
1024 /// Read-only values (empty)
1025 pub mod R {}
1026 /// Write-only values (empty)
1027 pub mod W {}
1028 /// Read-write values
1029 pub mod RW {
1030
1031 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1032 pub const Frozen: u32 = 0b000;
1033
1034 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1035 pub const ActiveOnMatch: u32 = 0b001;
1036
1037 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
1038 pub const InactiveOnMatch: u32 = 0b010;
1039
1040 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
1041 pub const Toggle: u32 = 0b011;
1042
1043 /// 0b100: OCyREF is forced low
1044 pub const ForceInactive: u32 = 0b100;
1045
1046 /// 0b101: OCyREF is forced high
1047 pub const ForceActive: u32 = 0b101;
1048
1049 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
1050 pub const PwmMode1: u32 = 0b110;
1051
1052 /// 0b111: Inversely to PwmMode1
1053 pub const PwmMode2: u32 = 0b111;
1054 }
1055 }
1056
1057 /// Output compare 2 preload enable
1058 pub mod OC2PE {
1059 /// Offset (11 bits)
1060 pub const offset: u32 = 11;
1061 /// Mask (1 bit: 1 << 11)
1062 pub const mask: u32 = 1 << offset;
1063 /// Read-only values (empty)
1064 pub mod R {}
1065 /// Write-only values (empty)
1066 pub mod W {}
1067 /// Read-write values
1068 pub mod RW {
1069
1070 /// 0b0: Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately
1071 pub const Disabled: u32 = 0b0;
1072
1073 /// 0b1: Preload register on CCR2 enabled. Preload value is loaded into active register on each update event
1074 pub const Enabled: u32 = 0b1;
1075 }
1076 }
1077
1078 /// Output compare 2 fast enable
1079 pub mod OC2FE {
1080 /// Offset (10 bits)
1081 pub const offset: u32 = 10;
1082 /// Mask (1 bit: 1 << 10)
1083 pub const mask: u32 = 1 << offset;
1084 /// Read-only values (empty)
1085 pub mod R {}
1086 /// Write-only values (empty)
1087 pub mod W {}
1088 /// Read-write values (empty)
1089 pub mod RW {}
1090 }
1091
1092 /// Capture/Compare 2 selection
1093 pub mod CC2S {
1094 /// Offset (8 bits)
1095 pub const offset: u32 = 8;
1096 /// Mask (1 bit: 1 << 8)
1097 pub const mask: u32 = 1 << offset;
1098 /// Read-only values (empty)
1099 pub mod R {}
1100 /// Write-only values (empty)
1101 pub mod W {}
1102 /// Read-write values
1103 pub mod RW {
1104
1105 /// 0b0: CC2 channel is configured as output
1106 pub const Output: u32 = 0b0;
1107 }
1108 }
1109
1110 /// Output compare 1 clear enable
1111 pub mod OC1CE {
1112 /// Offset (7 bits)
1113 pub const offset: u32 = 7;
1114 /// Mask (1 bit: 1 << 7)
1115 pub const mask: u32 = 1 << offset;
1116 /// Read-only values (empty)
1117 pub mod R {}
1118 /// Write-only values (empty)
1119 pub mod W {}
1120 /// Read-write values (empty)
1121 pub mod RW {}
1122 }
1123
1124 /// Output compare 1 mode
1125 pub mod OC1M {
1126 /// Offset (4 bits)
1127 pub const offset: u32 = 4;
1128 /// Mask (3 bits: 0b111 << 4)
1129 pub const mask: u32 = 0b111 << offset;
1130 /// Read-only values (empty)
1131 pub mod R {}
1132 /// Write-only values (empty)
1133 pub mod W {}
1134 pub use super::OC2M::RW;
1135 }
1136
1137 /// Output compare 1 preload enable
1138 pub mod OC1PE {
1139 /// Offset (3 bits)
1140 pub const offset: u32 = 3;
1141 /// Mask (1 bit: 1 << 3)
1142 pub const mask: u32 = 1 << offset;
1143 /// Read-only values (empty)
1144 pub mod R {}
1145 /// Write-only values (empty)
1146 pub mod W {}
1147 /// Read-write values
1148 pub mod RW {
1149
1150 /// 0b0: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1151 pub const Disabled: u32 = 0b0;
1152
1153 /// 0b1: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
1154 pub const Enabled: u32 = 0b1;
1155 }
1156 }
1157
1158 /// Output compare 1 fast enable
1159 pub mod OC1FE {
1160 /// Offset (2 bits)
1161 pub const offset: u32 = 2;
1162 /// Mask (1 bit: 1 << 2)
1163 pub const mask: u32 = 1 << offset;
1164 /// Read-only values (empty)
1165 pub mod R {}
1166 /// Write-only values (empty)
1167 pub mod W {}
1168 /// Read-write values (empty)
1169 pub mod RW {}
1170 }
1171
1172 /// Capture/Compare 1 selection
1173 pub mod CC1S {
1174 /// Offset (0 bits)
1175 pub const offset: u32 = 0;
1176 /// Mask (2 bits: 0b11 << 0)
1177 pub const mask: u32 = 0b11 << offset;
1178 /// Read-only values (empty)
1179 pub mod R {}
1180 /// Write-only values (empty)
1181 pub mod W {}
1182 /// Read-write values
1183 pub mod RW {
1184
1185 /// 0b00: CC1 channel is configured as output
1186 pub const Output: u32 = 0b00;
1187 }
1188 }
1189
1190 /// Input capture 2 filter
1191 pub mod IC2F {
1192 /// Offset (12 bits)
1193 pub const offset: u32 = 12;
1194 /// Mask (4 bits: 0b1111 << 12)
1195 pub const mask: u32 = 0b1111 << offset;
1196 /// Read-only values (empty)
1197 pub mod R {}
1198 /// Write-only values (empty)
1199 pub mod W {}
1200 /// Read-write values (empty)
1201 pub mod RW {}
1202 }
1203
1204 /// Input capture 2 prescaler
1205 pub mod IC2PSC {
1206 /// Offset (10 bits)
1207 pub const offset: u32 = 10;
1208 /// Mask (2 bits: 0b11 << 10)
1209 pub const mask: u32 = 0b11 << offset;
1210 /// Read-only values (empty)
1211 pub mod R {}
1212 /// Write-only values (empty)
1213 pub mod W {}
1214 /// Read-write values (empty)
1215 pub mod RW {}
1216 }
1217
1218 /// Input capture 1 filter
1219 pub mod IC1F {
1220 /// Offset (4 bits)
1221 pub const offset: u32 = 4;
1222 /// Mask (4 bits: 0b1111 << 4)
1223 pub const mask: u32 = 0b1111 << offset;
1224 /// Read-only values (empty)
1225 pub mod R {}
1226 /// Write-only values (empty)
1227 pub mod W {}
1228 /// Read-write values
1229 pub mod RW {
1230
1231 /// 0b0000: No filter, sampling is done at fDTS
1232 pub const NoFilter: u32 = 0b0000;
1233
1234 /// 0b0001: fSAMPLING=fCK_INT, N=2
1235 pub const FCK_INT_N2: u32 = 0b0001;
1236
1237 /// 0b0010: fSAMPLING=fCK_INT, N=4
1238 pub const FCK_INT_N4: u32 = 0b0010;
1239
1240 /// 0b0011: fSAMPLING=fCK_INT, N=8
1241 pub const FCK_INT_N8: u32 = 0b0011;
1242
1243 /// 0b0100: fSAMPLING=fDTS/2, N=6
1244 pub const FDTS_Div2_N6: u32 = 0b0100;
1245
1246 /// 0b0101: fSAMPLING=fDTS/2, N=8
1247 pub const FDTS_Div2_N8: u32 = 0b0101;
1248
1249 /// 0b0110: fSAMPLING=fDTS/4, N=6
1250 pub const FDTS_Div4_N6: u32 = 0b0110;
1251
1252 /// 0b0111: fSAMPLING=fDTS/4, N=8
1253 pub const FDTS_Div4_N8: u32 = 0b0111;
1254
1255 /// 0b1000: fSAMPLING=fDTS/8, N=6
1256 pub const FDTS_Div8_N6: u32 = 0b1000;
1257
1258 /// 0b1001: fSAMPLING=fDTS/8, N=8
1259 pub const FDTS_Div8_N8: u32 = 0b1001;
1260
1261 /// 0b1010: fSAMPLING=fDTS/16, N=5
1262 pub const FDTS_Div16_N5: u32 = 0b1010;
1263
1264 /// 0b1011: fSAMPLING=fDTS/16, N=6
1265 pub const FDTS_Div16_N6: u32 = 0b1011;
1266
1267 /// 0b1100: fSAMPLING=fDTS/16, N=8
1268 pub const FDTS_Div16_N8: u32 = 0b1100;
1269
1270 /// 0b1101: fSAMPLING=fDTS/32, N=5
1271 pub const FDTS_Div32_N5: u32 = 0b1101;
1272
1273 /// 0b1110: fSAMPLING=fDTS/32, N=6
1274 pub const FDTS_Div32_N6: u32 = 0b1110;
1275
1276 /// 0b1111: fSAMPLING=fDTS/32, N=8
1277 pub const FDTS_Div32_N8: u32 = 0b1111;
1278 }
1279 }
1280
1281 /// Input capture 1 prescaler
1282 pub mod IC1PSC {
1283 /// Offset (2 bits)
1284 pub const offset: u32 = 2;
1285 /// Mask (2 bits: 0b11 << 2)
1286 pub const mask: u32 = 0b11 << offset;
1287 /// Read-only values (empty)
1288 pub mod R {}
1289 /// Write-only values (empty)
1290 pub mod W {}
1291 /// Read-write values (empty)
1292 pub mod RW {}
1293 }
1294}
1295
1296/// CCMR2_Output and CCMR2_Input
1297/// CCMR2_Output: capture/compare mode register 2
1298/// CCMR2_Input: capture/compare mode register 2 (input mode)
1299pub mod CCMR2 {
1300
1301 /// Output compare 4 clear enable
1302 pub mod OC4CE {
1303 /// Offset (15 bits)
1304 pub const offset: u32 = 15;
1305 /// Mask (1 bit: 1 << 15)
1306 pub const mask: u32 = 1 << offset;
1307 /// Read-only values (empty)
1308 pub mod R {}
1309 /// Write-only values (empty)
1310 pub mod W {}
1311 /// Read-write values (empty)
1312 pub mod RW {}
1313 }
1314
1315 /// Output compare 4 mode
1316 pub mod OC4M {
1317 /// Offset (12 bits)
1318 pub const offset: u32 = 12;
1319 /// Mask (3 bits: 0b111 << 12)
1320 pub const mask: u32 = 0b111 << offset;
1321 /// Read-only values (empty)
1322 pub mod R {}
1323 /// Write-only values (empty)
1324 pub mod W {}
1325 /// Read-write values
1326 pub mod RW {
1327
1328 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1329 pub const Frozen: u32 = 0b000;
1330
1331 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
1332 pub const ActiveOnMatch: u32 = 0b001;
1333
1334 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
1335 pub const InactiveOnMatch: u32 = 0b010;
1336
1337 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
1338 pub const Toggle: u32 = 0b011;
1339
1340 /// 0b100: OCyREF is forced low
1341 pub const ForceInactive: u32 = 0b100;
1342
1343 /// 0b101: OCyREF is forced high
1344 pub const ForceActive: u32 = 0b101;
1345
1346 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
1347 pub const PwmMode1: u32 = 0b110;
1348
1349 /// 0b111: Inversely to PwmMode1
1350 pub const PwmMode2: u32 = 0b111;
1351 }
1352 }
1353
1354 /// Output compare 4 preload enable
1355 pub mod OC4PE {
1356 /// Offset (11 bits)
1357 pub const offset: u32 = 11;
1358 /// Mask (1 bit: 1 << 11)
1359 pub const mask: u32 = 1 << offset;
1360 /// Read-only values (empty)
1361 pub mod R {}
1362 /// Write-only values (empty)
1363 pub mod W {}
1364 /// Read-write values
1365 pub mod RW {
1366
1367 /// 0b0: Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately
1368 pub const Disabled: u32 = 0b0;
1369
1370 /// 0b1: Preload register on CCR4 enabled. Preload value is loaded into active register on each update event
1371 pub const Enabled: u32 = 0b1;
1372 }
1373 }
1374
1375 /// Output compare 4 fast enable
1376 pub mod OC4FE {
1377 /// Offset (10 bits)
1378 pub const offset: u32 = 10;
1379 /// Mask (1 bit: 1 << 10)
1380 pub const mask: u32 = 1 << offset;
1381 /// Read-only values (empty)
1382 pub mod R {}
1383 /// Write-only values (empty)
1384 pub mod W {}
1385 /// Read-write values (empty)
1386 pub mod RW {}
1387 }
1388
1389 /// Capture/Compare 4 selection
1390 pub mod CC4S {
1391 /// Offset (8 bits)
1392 pub const offset: u32 = 8;
1393 /// Mask (1 bit: 1 << 8)
1394 pub const mask: u32 = 1 << offset;
1395 /// Read-only values (empty)
1396 pub mod R {}
1397 /// Write-only values (empty)
1398 pub mod W {}
1399 /// Read-write values
1400 pub mod RW {
1401
1402 /// 0b0: CC4 channel is configured as output
1403 pub const Output: u32 = 0b0;
1404 }
1405 }
1406
1407 /// Output compare 3 clear enable
1408 pub mod OC3CE {
1409 /// Offset (7 bits)
1410 pub const offset: u32 = 7;
1411 /// Mask (1 bit: 1 << 7)
1412 pub const mask: u32 = 1 << offset;
1413 /// Read-only values (empty)
1414 pub mod R {}
1415 /// Write-only values (empty)
1416 pub mod W {}
1417 /// Read-write values (empty)
1418 pub mod RW {}
1419 }
1420
1421 /// Output compare 3 mode
1422 pub mod OC3M {
1423 /// Offset (4 bits)
1424 pub const offset: u32 = 4;
1425 /// Mask (3 bits: 0b111 << 4)
1426 pub const mask: u32 = 0b111 << offset;
1427 /// Read-only values (empty)
1428 pub mod R {}
1429 /// Write-only values (empty)
1430 pub mod W {}
1431 pub use super::OC4M::RW;
1432 }
1433
1434 /// Output compare 3 preload enable
1435 pub mod OC3PE {
1436 /// Offset (3 bits)
1437 pub const offset: u32 = 3;
1438 /// Mask (1 bit: 1 << 3)
1439 pub const mask: u32 = 1 << offset;
1440 /// Read-only values (empty)
1441 pub mod R {}
1442 /// Write-only values (empty)
1443 pub mod W {}
1444 /// Read-write values
1445 pub mod RW {
1446
1447 /// 0b0: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1448 pub const Disabled: u32 = 0b0;
1449
1450 /// 0b1: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
1451 pub const Enabled: u32 = 0b1;
1452 }
1453 }
1454
1455 /// Output compare 3 fast enable
1456 pub mod OC3FE {
1457 /// Offset (2 bits)
1458 pub const offset: u32 = 2;
1459 /// Mask (1 bit: 1 << 2)
1460 pub const mask: u32 = 1 << offset;
1461 /// Read-only values (empty)
1462 pub mod R {}
1463 /// Write-only values (empty)
1464 pub mod W {}
1465 /// Read-write values (empty)
1466 pub mod RW {}
1467 }
1468
1469 /// Capture/Compare 3 selection
1470 pub mod CC3S {
1471 /// Offset (0 bits)
1472 pub const offset: u32 = 0;
1473 /// Mask (2 bits: 0b11 << 0)
1474 pub const mask: u32 = 0b11 << offset;
1475 /// Read-only values (empty)
1476 pub mod R {}
1477 /// Write-only values (empty)
1478 pub mod W {}
1479 /// Read-write values
1480 pub mod RW {
1481
1482 /// 0b00: CC3 channel is configured as output
1483 pub const Output: u32 = 0b00;
1484 }
1485 }
1486
1487 /// Input capture 4 filter
1488 pub mod IC4F {
1489 /// Offset (12 bits)
1490 pub const offset: u32 = 12;
1491 /// Mask (4 bits: 0b1111 << 12)
1492 pub const mask: u32 = 0b1111 << offset;
1493 /// Read-only values (empty)
1494 pub mod R {}
1495 /// Write-only values (empty)
1496 pub mod W {}
1497 /// Read-write values (empty)
1498 pub mod RW {}
1499 }
1500
1501 /// Input capture 4 prescaler
1502 pub mod IC4PSC {
1503 /// Offset (10 bits)
1504 pub const offset: u32 = 10;
1505 /// Mask (2 bits: 0b11 << 10)
1506 pub const mask: u32 = 0b11 << offset;
1507 /// Read-only values (empty)
1508 pub mod R {}
1509 /// Write-only values (empty)
1510 pub mod W {}
1511 /// Read-write values (empty)
1512 pub mod RW {}
1513 }
1514
1515 /// Input capture 3 filter
1516 pub mod IC3F {
1517 /// Offset (4 bits)
1518 pub const offset: u32 = 4;
1519 /// Mask (4 bits: 0b1111 << 4)
1520 pub const mask: u32 = 0b1111 << offset;
1521 /// Read-only values (empty)
1522 pub mod R {}
1523 /// Write-only values (empty)
1524 pub mod W {}
1525 /// Read-write values (empty)
1526 pub mod RW {}
1527 }
1528
1529 /// Input capture 3 prescaler
1530 pub mod IC3PSC {
1531 /// Offset (2 bits)
1532 pub const offset: u32 = 2;
1533 /// Mask (2 bits: 0b11 << 2)
1534 pub const mask: u32 = 0b11 << offset;
1535 /// Read-only values (empty)
1536 pub mod R {}
1537 /// Write-only values (empty)
1538 pub mod W {}
1539 /// Read-write values (empty)
1540 pub mod RW {}
1541 }
1542}
1543
1544/// capture/compare enable register
1545pub mod CCER {
1546
1547 /// Capture/Compare 4 output Polarity
1548 pub mod CC4NP {
1549 /// Offset (15 bits)
1550 pub const offset: u32 = 15;
1551 /// Mask (1 bit: 1 << 15)
1552 pub const mask: u32 = 1 << offset;
1553 /// Read-only values (empty)
1554 pub mod R {}
1555 /// Write-only values (empty)
1556 pub mod W {}
1557 /// Read-write values (empty)
1558 pub mod RW {}
1559 }
1560
1561 /// Capture/Compare 4 output Polarity
1562 pub mod CC4P {
1563 /// Offset (13 bits)
1564 pub const offset: u32 = 13;
1565 /// Mask (1 bit: 1 << 13)
1566 pub const mask: u32 = 1 << offset;
1567 /// Read-only values (empty)
1568 pub mod R {}
1569 /// Write-only values (empty)
1570 pub mod W {}
1571 /// Read-write values (empty)
1572 pub mod RW {}
1573 }
1574
1575 /// Capture/Compare 4 output enable
1576 pub mod CC4E {
1577 /// Offset (12 bits)
1578 pub const offset: u32 = 12;
1579 /// Mask (1 bit: 1 << 12)
1580 pub const mask: u32 = 1 << offset;
1581 /// Read-only values (empty)
1582 pub mod R {}
1583 /// Write-only values (empty)
1584 pub mod W {}
1585 /// Read-write values (empty)
1586 pub mod RW {}
1587 }
1588
1589 /// Capture/Compare 3 output Polarity
1590 pub mod CC3NP {
1591 /// Offset (11 bits)
1592 pub const offset: u32 = 11;
1593 /// Mask (1 bit: 1 << 11)
1594 pub const mask: u32 = 1 << offset;
1595 /// Read-only values (empty)
1596 pub mod R {}
1597 /// Write-only values (empty)
1598 pub mod W {}
1599 /// Read-write values (empty)
1600 pub mod RW {}
1601 }
1602
1603 /// Capture/Compare 3 output Polarity
1604 pub mod CC3P {
1605 /// Offset (9 bits)
1606 pub const offset: u32 = 9;
1607 /// Mask (1 bit: 1 << 9)
1608 pub const mask: u32 = 1 << offset;
1609 /// Read-only values (empty)
1610 pub mod R {}
1611 /// Write-only values (empty)
1612 pub mod W {}
1613 /// Read-write values (empty)
1614 pub mod RW {}
1615 }
1616
1617 /// Capture/Compare 3 output enable
1618 pub mod CC3E {
1619 /// Offset (8 bits)
1620 pub const offset: u32 = 8;
1621 /// Mask (1 bit: 1 << 8)
1622 pub const mask: u32 = 1 << offset;
1623 /// Read-only values (empty)
1624 pub mod R {}
1625 /// Write-only values (empty)
1626 pub mod W {}
1627 /// Read-write values (empty)
1628 pub mod RW {}
1629 }
1630
1631 /// Capture/Compare 2 output Polarity
1632 pub mod CC2NP {
1633 /// Offset (7 bits)
1634 pub const offset: u32 = 7;
1635 /// Mask (1 bit: 1 << 7)
1636 pub const mask: u32 = 1 << offset;
1637 /// Read-only values (empty)
1638 pub mod R {}
1639 /// Write-only values (empty)
1640 pub mod W {}
1641 /// Read-write values (empty)
1642 pub mod RW {}
1643 }
1644
1645 /// Capture/Compare 2 output Polarity
1646 pub mod CC2P {
1647 /// Offset (5 bits)
1648 pub const offset: u32 = 5;
1649 /// Mask (1 bit: 1 << 5)
1650 pub const mask: u32 = 1 << offset;
1651 /// Read-only values (empty)
1652 pub mod R {}
1653 /// Write-only values (empty)
1654 pub mod W {}
1655 /// Read-write values (empty)
1656 pub mod RW {}
1657 }
1658
1659 /// Capture/Compare 2 output enable
1660 pub mod CC2E {
1661 /// Offset (4 bits)
1662 pub const offset: u32 = 4;
1663 /// Mask (1 bit: 1 << 4)
1664 pub const mask: u32 = 1 << offset;
1665 /// Read-only values (empty)
1666 pub mod R {}
1667 /// Write-only values (empty)
1668 pub mod W {}
1669 /// Read-write values (empty)
1670 pub mod RW {}
1671 }
1672
1673 /// Capture/Compare 1 complementary output Polarity
1674 pub mod CC1NP {
1675 /// Offset (3 bits)
1676 pub const offset: u32 = 3;
1677 /// Mask (1 bit: 1 << 3)
1678 pub const mask: u32 = 1 << offset;
1679 /// Read-only values (empty)
1680 pub mod R {}
1681 /// Write-only values (empty)
1682 pub mod W {}
1683 /// Read-write values (empty)
1684 pub mod RW {}
1685 }
1686
1687 /// Capture/Compare 1 output Polarity
1688 pub mod CC1P {
1689 /// Offset (1 bits)
1690 pub const offset: u32 = 1;
1691 /// Mask (1 bit: 1 << 1)
1692 pub const mask: u32 = 1 << offset;
1693 /// Read-only values (empty)
1694 pub mod R {}
1695 /// Write-only values (empty)
1696 pub mod W {}
1697 /// Read-write values (empty)
1698 pub mod RW {}
1699 }
1700
1701 /// Capture/Compare 1 output enable
1702 pub mod CC1E {
1703 /// Offset (0 bits)
1704 pub const offset: u32 = 0;
1705 /// Mask (1 bit: 1 << 0)
1706 pub const mask: u32 = 1 << offset;
1707 /// Read-only values (empty)
1708 pub mod R {}
1709 /// Write-only values (empty)
1710 pub mod W {}
1711 /// Read-write values (empty)
1712 pub mod RW {}
1713 }
1714}
1715
1716/// counter
1717pub mod CNT {
1718
1719 /// TIM2 counter
1720 pub mod CNT {
1721 /// Offset (0 bits)
1722 pub const offset: u32 = 0;
1723 /// Mask (16 bits: 0xffff << 0)
1724 pub const mask: u32 = 0xffff << offset;
1725 /// Read-only values (empty)
1726 pub mod R {}
1727 /// Write-only values (empty)
1728 pub mod W {}
1729 /// Read-write values (empty)
1730 pub mod RW {}
1731 }
1732}
1733
1734/// prescaler
1735pub mod PSC {
1736
1737 /// TIM2 prescaler
1738 pub mod PSC {
1739 /// Offset (0 bits)
1740 pub const offset: u32 = 0;
1741 /// Mask (16 bits: 0xffff << 0)
1742 pub const mask: u32 = 0xffff << offset;
1743 /// Read-only values (empty)
1744 pub mod R {}
1745 /// Write-only values (empty)
1746 pub mod W {}
1747 /// Read-write values (empty)
1748 pub mod RW {}
1749 }
1750}
1751
1752/// auto-reload register
1753pub mod ARR {
1754
1755 /// Auto-reload value
1756 pub mod ARR {
1757 /// Offset (0 bits)
1758 pub const offset: u32 = 0;
1759 /// Mask (16 bits: 0xffff << 0)
1760 pub const mask: u32 = 0xffff << offset;
1761 /// Read-only values (empty)
1762 pub mod R {}
1763 /// Write-only values (empty)
1764 pub mod W {}
1765 /// Read-write values (empty)
1766 pub mod RW {}
1767 }
1768}
1769
1770/// capture/compare register
1771pub mod CCR1 {
1772
1773 /// Capture/Compare value
1774 pub mod CCR {
1775 /// Offset (0 bits)
1776 pub const offset: u32 = 0;
1777 /// Mask (16 bits: 0xffff << 0)
1778 pub const mask: u32 = 0xffff << offset;
1779 /// Read-only values (empty)
1780 pub mod R {}
1781 /// Write-only values (empty)
1782 pub mod W {}
1783 /// Read-write values (empty)
1784 pub mod RW {}
1785 }
1786}
1787
1788/// capture/compare register
1789pub mod CCR2 {
1790 pub use super::CCR1::CCR;
1791}
1792
1793/// capture/compare register
1794pub mod CCR3 {
1795 pub use super::CCR1::CCR;
1796}
1797
1798/// capture/compare register
1799pub mod CCR4 {
1800 pub use super::CCR1::CCR;
1801}
1802
1803/// DMA control register
1804pub mod DCR {
1805
1806 /// DMA burst length
1807 pub mod DBL {
1808 /// Offset (8 bits)
1809 pub const offset: u32 = 8;
1810 /// Mask (5 bits: 0b11111 << 8)
1811 pub const mask: u32 = 0b11111 << offset;
1812 /// Read-only values (empty)
1813 pub mod R {}
1814 /// Write-only values (empty)
1815 pub mod W {}
1816 /// Read-write values (empty)
1817 pub mod RW {}
1818 }
1819
1820 /// DMA base address
1821 pub mod DBA {
1822 /// Offset (0 bits)
1823 pub const offset: u32 = 0;
1824 /// Mask (5 bits: 0b11111 << 0)
1825 pub const mask: u32 = 0b11111 << offset;
1826 /// Read-only values (empty)
1827 pub mod R {}
1828 /// Write-only values (empty)
1829 pub mod W {}
1830 /// Read-write values (empty)
1831 pub mod RW {}
1832 }
1833}
1834
1835/// DMA address for full transfer
1836pub mod DMAR {
1837
1838 /// DMA register for burst accesses
1839 pub mod DMAB {
1840 /// Offset (0 bits)
1841 pub const offset: u32 = 0;
1842 /// Mask (16 bits: 0xffff << 0)
1843 pub const mask: u32 = 0xffff << offset;
1844 /// Read-only values (empty)
1845 pub mod R {}
1846 /// Write-only values (empty)
1847 pub mod W {}
1848 /// Read-write values (empty)
1849 pub mod RW {}
1850 }
1851}
1852#[repr(C)]
1853pub struct RegisterBlock {
1854 /// control register 1
1855 pub CR1: RWRegister<u32>,
1856
1857 /// control register 2
1858 pub CR2: RWRegister<u32>,
1859
1860 /// slave mode control register
1861 pub SMCR: RWRegister<u32>,
1862
1863 /// Interrupt enable register
1864 pub DIER: RWRegister<u32>,
1865
1866 /// status register
1867 pub SR: RWRegister<u32>,
1868
1869 /// event generation register
1870 pub EGR: RWRegister<u32>,
1871
1872 /// CCMR1_Output and CCMR1_Input
1873 /// CCMR1_Output: capture/compare mode register 1
1874 /// CCMR1_Input: capture/compare mode register 1 (input mode)
1875 pub CCMR1: RWRegister<u32>,
1876
1877 /// CCMR2_Output and CCMR2_Input
1878 /// CCMR2_Output: capture/compare mode register 2
1879 /// CCMR2_Input: capture/compare mode register 2 (input mode)
1880 pub CCMR2: RWRegister<u32>,
1881
1882 /// capture/compare enable register
1883 pub CCER: RWRegister<u32>,
1884
1885 /// counter
1886 pub CNT: RWRegister<u32>,
1887
1888 /// prescaler
1889 pub PSC: RWRegister<u32>,
1890
1891 /// auto-reload register
1892 pub ARR: RWRegister<u32>,
1893
1894 _reserved1: [u8; 4],
1895
1896 /// capture/compare register
1897 pub CCR1: RWRegister<u32>,
1898
1899 /// capture/compare register
1900 pub CCR2: RWRegister<u32>,
1901
1902 /// capture/compare register
1903 pub CCR3: RWRegister<u32>,
1904
1905 /// capture/compare register
1906 pub CCR4: RWRegister<u32>,
1907
1908 _reserved2: [u8; 4],
1909
1910 /// DMA control register
1911 pub DCR: RWRegister<u32>,
1912
1913 /// DMA address for full transfer
1914 pub DMAR: RWRegister<u32>,
1915}
1916pub struct ResetValues {
1917 pub CR1: u32,
1918 pub CR2: u32,
1919 pub SMCR: u32,
1920 pub DIER: u32,
1921 pub SR: u32,
1922 pub EGR: u32,
1923 pub CCMR1: u32,
1924 pub CCMR2: u32,
1925 pub CCER: u32,
1926 pub CNT: u32,
1927 pub PSC: u32,
1928 pub ARR: u32,
1929 pub CCR1: u32,
1930 pub CCR2: u32,
1931 pub CCR3: u32,
1932 pub CCR4: u32,
1933 pub DCR: u32,
1934 pub DMAR: u32,
1935}
1936#[cfg(not(feature = "nosync"))]
1937pub struct Instance {
1938 pub(crate) addr: u32,
1939 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1940}
1941#[cfg(not(feature = "nosync"))]
1942impl ::core::ops::Deref for Instance {
1943 type Target = RegisterBlock;
1944 #[inline(always)]
1945 fn deref(&self) -> &RegisterBlock {
1946 unsafe { &*(self.addr as *const _) }
1947 }
1948}
1949#[cfg(feature = "rtic")]
1950unsafe impl Send for Instance {}