stm32ral/stm32l1/peripherals/flash.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Flash
4//!
5//! Used by: stm32l100, stm32l151, stm32l162
6
7use crate::{RORegister, RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// Access control register
12pub mod ACR {
13
14 /// Latency
15 pub mod LATENCY {
16 /// Offset (0 bits)
17 pub const offset: u32 = 0;
18 /// Mask (1 bit: 1 << 0)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Prefetch enable
29 pub mod PRFTEN {
30 /// Offset (1 bits)
31 pub const offset: u32 = 1;
32 /// Mask (1 bit: 1 << 1)
33 pub const mask: u32 = 1 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// 64-bit access
43 pub mod ACC64 {
44 /// Offset (2 bits)
45 pub const offset: u32 = 2;
46 /// Mask (1 bit: 1 << 2)
47 pub const mask: u32 = 1 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// Flash mode during Sleep
57 pub mod SLEEP_PD {
58 /// Offset (3 bits)
59 pub const offset: u32 = 3;
60 /// Mask (1 bit: 1 << 3)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// Flash mode during Run
71 pub mod RUN_PD {
72 /// Offset (4 bits)
73 pub const offset: u32 = 4;
74 /// Mask (1 bit: 1 << 4)
75 pub const mask: u32 = 1 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83}
84
85/// Program/erase control register
86pub mod PECR {
87
88 /// FLASH_PECR and data EEPROM lock
89 pub mod PELOCK {
90 /// Offset (0 bits)
91 pub const offset: u32 = 0;
92 /// Mask (1 bit: 1 << 0)
93 pub const mask: u32 = 1 << offset;
94 /// Read-only values (empty)
95 pub mod R {}
96 /// Write-only values (empty)
97 pub mod W {}
98 /// Read-write values (empty)
99 pub mod RW {}
100 }
101
102 /// Program memory lock
103 pub mod PRGLOCK {
104 /// Offset (1 bits)
105 pub const offset: u32 = 1;
106 /// Mask (1 bit: 1 << 1)
107 pub const mask: u32 = 1 << offset;
108 /// Read-only values (empty)
109 pub mod R {}
110 /// Write-only values (empty)
111 pub mod W {}
112 /// Read-write values (empty)
113 pub mod RW {}
114 }
115
116 /// Option bytes block lock
117 pub mod OPTLOCK {
118 /// Offset (2 bits)
119 pub const offset: u32 = 2;
120 /// Mask (1 bit: 1 << 2)
121 pub const mask: u32 = 1 << offset;
122 /// Read-only values (empty)
123 pub mod R {}
124 /// Write-only values (empty)
125 pub mod W {}
126 /// Read-write values (empty)
127 pub mod RW {}
128 }
129
130 /// Program memory selection
131 pub mod PROG {
132 /// Offset (3 bits)
133 pub const offset: u32 = 3;
134 /// Mask (1 bit: 1 << 3)
135 pub const mask: u32 = 1 << offset;
136 /// Read-only values (empty)
137 pub mod R {}
138 /// Write-only values (empty)
139 pub mod W {}
140 /// Read-write values (empty)
141 pub mod RW {}
142 }
143
144 /// Data EEPROM selection
145 pub mod DATA {
146 /// Offset (4 bits)
147 pub const offset: u32 = 4;
148 /// Mask (1 bit: 1 << 4)
149 pub const mask: u32 = 1 << offset;
150 /// Read-only values (empty)
151 pub mod R {}
152 /// Write-only values (empty)
153 pub mod W {}
154 /// Read-write values (empty)
155 pub mod RW {}
156 }
157
158 /// Fixed time data write for Byte, Half Word and Word programming
159 pub mod FTDW {
160 /// Offset (8 bits)
161 pub const offset: u32 = 8;
162 /// Mask (1 bit: 1 << 8)
163 pub const mask: u32 = 1 << offset;
164 /// Read-only values (empty)
165 pub mod R {}
166 /// Write-only values (empty)
167 pub mod W {}
168 /// Read-write values (empty)
169 pub mod RW {}
170 }
171
172 /// Page or Double Word erase mode
173 pub mod ERASE {
174 /// Offset (9 bits)
175 pub const offset: u32 = 9;
176 /// Mask (1 bit: 1 << 9)
177 pub const mask: u32 = 1 << offset;
178 /// Read-only values (empty)
179 pub mod R {}
180 /// Write-only values (empty)
181 pub mod W {}
182 /// Read-write values (empty)
183 pub mod RW {}
184 }
185
186 /// Half Page/Double Word programming mode
187 pub mod FPRG {
188 /// Offset (10 bits)
189 pub const offset: u32 = 10;
190 /// Mask (1 bit: 1 << 10)
191 pub const mask: u32 = 1 << offset;
192 /// Read-only values (empty)
193 pub mod R {}
194 /// Write-only values (empty)
195 pub mod W {}
196 /// Read-write values (empty)
197 pub mod RW {}
198 }
199
200 /// Parallel bank mode
201 pub mod PARALLELBANK {
202 /// Offset (15 bits)
203 pub const offset: u32 = 15;
204 /// Mask (1 bit: 1 << 15)
205 pub const mask: u32 = 1 << offset;
206 /// Read-only values (empty)
207 pub mod R {}
208 /// Write-only values (empty)
209 pub mod W {}
210 /// Read-write values (empty)
211 pub mod RW {}
212 }
213
214 /// End of programming interrupt enable
215 pub mod EOPIE {
216 /// Offset (16 bits)
217 pub const offset: u32 = 16;
218 /// Mask (1 bit: 1 << 16)
219 pub const mask: u32 = 1 << offset;
220 /// Read-only values (empty)
221 pub mod R {}
222 /// Write-only values (empty)
223 pub mod W {}
224 /// Read-write values (empty)
225 pub mod RW {}
226 }
227
228 /// Error interrupt enable
229 pub mod ERRIE {
230 /// Offset (17 bits)
231 pub const offset: u32 = 17;
232 /// Mask (1 bit: 1 << 17)
233 pub const mask: u32 = 1 << offset;
234 /// Read-only values (empty)
235 pub mod R {}
236 /// Write-only values (empty)
237 pub mod W {}
238 /// Read-write values (empty)
239 pub mod RW {}
240 }
241
242 /// Launch the option byte loading
243 pub mod OBL_LAUNCH {
244 /// Offset (18 bits)
245 pub const offset: u32 = 18;
246 /// Mask (1 bit: 1 << 18)
247 pub const mask: u32 = 1 << offset;
248 /// Read-only values (empty)
249 pub mod R {}
250 /// Write-only values (empty)
251 pub mod W {}
252 /// Read-write values (empty)
253 pub mod RW {}
254 }
255}
256
257/// Power down key register
258pub mod PDKEYR {
259
260 /// RUN_PD in FLASH_ACR key
261 pub mod PDKEYR {
262 /// Offset (0 bits)
263 pub const offset: u32 = 0;
264 /// Mask (32 bits: 0xffffffff << 0)
265 pub const mask: u32 = 0xffffffff << offset;
266 /// Read-only values (empty)
267 pub mod R {}
268 /// Write-only values (empty)
269 pub mod W {}
270 /// Read-write values (empty)
271 pub mod RW {}
272 }
273}
274
275/// Program/erase key register
276pub mod PEKEYR {
277
278 /// FLASH_PEC and data EEPROM key
279 pub mod PEKEYR {
280 /// Offset (0 bits)
281 pub const offset: u32 = 0;
282 /// Mask (32 bits: 0xffffffff << 0)
283 pub const mask: u32 = 0xffffffff << offset;
284 /// Read-only values (empty)
285 pub mod R {}
286 /// Write-only values (empty)
287 pub mod W {}
288 /// Read-write values (empty)
289 pub mod RW {}
290 }
291}
292
293/// Program memory key register
294pub mod PRGKEYR {
295
296 /// Program memory key
297 pub mod PRGKEYR {
298 /// Offset (0 bits)
299 pub const offset: u32 = 0;
300 /// Mask (32 bits: 0xffffffff << 0)
301 pub const mask: u32 = 0xffffffff << offset;
302 /// Read-only values (empty)
303 pub mod R {}
304 /// Write-only values (empty)
305 pub mod W {}
306 /// Read-write values (empty)
307 pub mod RW {}
308 }
309}
310
311/// Option byte key register
312pub mod OPTKEYR {
313
314 /// Option byte key
315 pub mod OPTKEYR {
316 /// Offset (0 bits)
317 pub const offset: u32 = 0;
318 /// Mask (32 bits: 0xffffffff << 0)
319 pub const mask: u32 = 0xffffffff << offset;
320 /// Read-only values (empty)
321 pub mod R {}
322 /// Write-only values (empty)
323 pub mod W {}
324 /// Read-write values (empty)
325 pub mod RW {}
326 }
327}
328
329/// Status register
330pub mod SR {
331
332 /// Write/erase operations in progress
333 pub mod BSY {
334 /// Offset (0 bits)
335 pub const offset: u32 = 0;
336 /// Mask (1 bit: 1 << 0)
337 pub const mask: u32 = 1 << offset;
338 /// Read-only values (empty)
339 pub mod R {}
340 /// Write-only values (empty)
341 pub mod W {}
342 /// Read-write values (empty)
343 pub mod RW {}
344 }
345
346 /// End of operation
347 pub mod EOP {
348 /// Offset (1 bits)
349 pub const offset: u32 = 1;
350 /// Mask (1 bit: 1 << 1)
351 pub const mask: u32 = 1 << offset;
352 /// Read-only values (empty)
353 pub mod R {}
354 /// Write-only values (empty)
355 pub mod W {}
356 /// Read-write values (empty)
357 pub mod RW {}
358 }
359
360 /// End of high voltage
361 pub mod ENDHV {
362 /// Offset (2 bits)
363 pub const offset: u32 = 2;
364 /// Mask (1 bit: 1 << 2)
365 pub const mask: u32 = 1 << offset;
366 /// Read-only values (empty)
367 pub mod R {}
368 /// Write-only values (empty)
369 pub mod W {}
370 /// Read-write values (empty)
371 pub mod RW {}
372 }
373
374 /// Flash memory module ready after low power mode
375 pub mod READY {
376 /// Offset (3 bits)
377 pub const offset: u32 = 3;
378 /// Mask (1 bit: 1 << 3)
379 pub const mask: u32 = 1 << offset;
380 /// Read-only values (empty)
381 pub mod R {}
382 /// Write-only values (empty)
383 pub mod W {}
384 /// Read-write values (empty)
385 pub mod RW {}
386 }
387
388 /// Write protected error
389 pub mod WRPERR {
390 /// Offset (8 bits)
391 pub const offset: u32 = 8;
392 /// Mask (1 bit: 1 << 8)
393 pub const mask: u32 = 1 << offset;
394 /// Read-only values (empty)
395 pub mod R {}
396 /// Write-only values (empty)
397 pub mod W {}
398 /// Read-write values (empty)
399 pub mod RW {}
400 }
401
402 /// Programming alignment error
403 pub mod PGAERR {
404 /// Offset (9 bits)
405 pub const offset: u32 = 9;
406 /// Mask (1 bit: 1 << 9)
407 pub const mask: u32 = 1 << offset;
408 /// Read-only values (empty)
409 pub mod R {}
410 /// Write-only values (empty)
411 pub mod W {}
412 /// Read-write values (empty)
413 pub mod RW {}
414 }
415
416 /// Size error
417 pub mod SIZERR {
418 /// Offset (10 bits)
419 pub const offset: u32 = 10;
420 /// Mask (1 bit: 1 << 10)
421 pub const mask: u32 = 1 << offset;
422 /// Read-only values (empty)
423 pub mod R {}
424 /// Write-only values (empty)
425 pub mod W {}
426 /// Read-write values (empty)
427 pub mod RW {}
428 }
429
430 /// Option validity error
431 pub mod OPTVERR {
432 /// Offset (11 bits)
433 pub const offset: u32 = 11;
434 /// Mask (1 bit: 1 << 11)
435 pub const mask: u32 = 1 << offset;
436 /// Read-only values (empty)
437 pub mod R {}
438 /// Write-only values (empty)
439 pub mod W {}
440 /// Read-write values (empty)
441 pub mod RW {}
442 }
443
444 /// Option UserValidity Error
445 pub mod OPTVERRUSR {
446 /// Offset (12 bits)
447 pub const offset: u32 = 12;
448 /// Mask (1 bit: 1 << 12)
449 pub const mask: u32 = 1 << offset;
450 /// Read-only values (empty)
451 pub mod R {}
452 /// Write-only values (empty)
453 pub mod W {}
454 /// Read-write values (empty)
455 pub mod RW {}
456 }
457}
458
459/// Option byte register
460pub mod OBR {
461
462 /// Read protection
463 pub mod RDPRT {
464 /// Offset (0 bits)
465 pub const offset: u32 = 0;
466 /// Mask (8 bits: 0xff << 0)
467 pub const mask: u32 = 0xff << offset;
468 /// Read-only values (empty)
469 pub mod R {}
470 /// Write-only values (empty)
471 pub mod W {}
472 /// Read-write values (empty)
473 pub mod RW {}
474 }
475
476 /// BOR_LEV
477 pub mod BOR_LEV {
478 /// Offset (16 bits)
479 pub const offset: u32 = 16;
480 /// Mask (4 bits: 0b1111 << 16)
481 pub const mask: u32 = 0b1111 << offset;
482 /// Read-only values (empty)
483 pub mod R {}
484 /// Write-only values (empty)
485 pub mod W {}
486 /// Read-write values (empty)
487 pub mod RW {}
488 }
489
490 /// IWDG_SW
491 pub mod IWDG_SW {
492 /// Offset (20 bits)
493 pub const offset: u32 = 20;
494 /// Mask (1 bit: 1 << 20)
495 pub const mask: u32 = 1 << offset;
496 /// Read-only values (empty)
497 pub mod R {}
498 /// Write-only values (empty)
499 pub mod W {}
500 /// Read-write values (empty)
501 pub mod RW {}
502 }
503
504 /// nRTS_STOP
505 pub mod nRTS_STOP {
506 /// Offset (21 bits)
507 pub const offset: u32 = 21;
508 /// Mask (1 bit: 1 << 21)
509 pub const mask: u32 = 1 << offset;
510 /// Read-only values (empty)
511 pub mod R {}
512 /// Write-only values (empty)
513 pub mod W {}
514 /// Read-write values (empty)
515 pub mod RW {}
516 }
517
518 /// nRST_STDBY
519 pub mod nRST_STDBY {
520 /// Offset (22 bits)
521 pub const offset: u32 = 22;
522 /// Mask (1 bit: 1 << 22)
523 pub const mask: u32 = 1 << offset;
524 /// Read-only values (empty)
525 pub mod R {}
526 /// Write-only values (empty)
527 pub mod W {}
528 /// Read-write values (empty)
529 pub mod RW {}
530 }
531
532 /// Boot From Bank 2
533 pub mod BFB2 {
534 /// Offset (23 bits)
535 pub const offset: u32 = 23;
536 /// Mask (1 bit: 1 << 23)
537 pub const mask: u32 = 1 << offset;
538 /// Read-only values (empty)
539 pub mod R {}
540 /// Write-only values (empty)
541 pub mod W {}
542 /// Read-write values (empty)
543 pub mod RW {}
544 }
545}
546
547/// Write protection register
548pub mod WRPR1 {
549
550 /// Write protection
551 pub mod WRP1 {
552 /// Offset (0 bits)
553 pub const offset: u32 = 0;
554 /// Mask (32 bits: 0xffffffff << 0)
555 pub const mask: u32 = 0xffffffff << offset;
556 /// Read-only values (empty)
557 pub mod R {}
558 /// Write-only values (empty)
559 pub mod W {}
560 /// Read-write values (empty)
561 pub mod RW {}
562 }
563}
564
565/// Write protection register
566pub mod WRPR2 {
567
568 /// WRP2
569 pub mod WRP2 {
570 /// Offset (0 bits)
571 pub const offset: u32 = 0;
572 /// Mask (32 bits: 0xffffffff << 0)
573 pub const mask: u32 = 0xffffffff << offset;
574 /// Read-only values (empty)
575 pub mod R {}
576 /// Write-only values (empty)
577 pub mod W {}
578 /// Read-write values (empty)
579 pub mod RW {}
580 }
581}
582
583/// Write protection register
584pub mod WRPR3 {
585
586 /// WRP3
587 pub mod WRP3 {
588 /// Offset (0 bits)
589 pub const offset: u32 = 0;
590 /// Mask (32 bits: 0xffffffff << 0)
591 pub const mask: u32 = 0xffffffff << offset;
592 /// Read-only values (empty)
593 pub mod R {}
594 /// Write-only values (empty)
595 pub mod W {}
596 /// Read-write values (empty)
597 pub mod RW {}
598 }
599}
600#[repr(C)]
601pub struct RegisterBlock {
602 /// Access control register
603 pub ACR: RWRegister<u32>,
604
605 /// Program/erase control register
606 pub PECR: RWRegister<u32>,
607
608 /// Power down key register
609 pub PDKEYR: WORegister<u32>,
610
611 /// Program/erase key register
612 pub PEKEYR: WORegister<u32>,
613
614 /// Program memory key register
615 pub PRGKEYR: WORegister<u32>,
616
617 /// Option byte key register
618 pub OPTKEYR: WORegister<u32>,
619
620 /// Status register
621 pub SR: RWRegister<u32>,
622
623 /// Option byte register
624 pub OBR: RORegister<u32>,
625
626 /// Write protection register
627 pub WRPR1: RWRegister<u32>,
628
629 _reserved1: [u8; 92],
630
631 /// Write protection register
632 pub WRPR2: RWRegister<u32>,
633
634 /// Write protection register
635 pub WRPR3: RWRegister<u32>,
636}
637pub struct ResetValues {
638 pub ACR: u32,
639 pub PECR: u32,
640 pub PDKEYR: u32,
641 pub PEKEYR: u32,
642 pub PRGKEYR: u32,
643 pub OPTKEYR: u32,
644 pub SR: u32,
645 pub OBR: u32,
646 pub WRPR1: u32,
647 pub WRPR2: u32,
648 pub WRPR3: u32,
649}
650#[cfg(not(feature = "nosync"))]
651pub struct Instance {
652 pub(crate) addr: u32,
653 pub(crate) _marker: PhantomData<*const RegisterBlock>,
654}
655#[cfg(not(feature = "nosync"))]
656impl ::core::ops::Deref for Instance {
657 type Target = RegisterBlock;
658 #[inline(always)]
659 fn deref(&self) -> &RegisterBlock {
660 unsafe { &*(self.addr as *const _) }
661 }
662}
663#[cfg(feature = "rtic")]
664unsafe impl Send for Instance {}