stm32ral/stm32h7/peripherals/cryp_v2.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Cryptographic processor
4//!
5//! Used by: stm32h753, stm32h753v
6
7use crate::{RORegister, RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register
12pub mod CR {
13
14 /// Algorithm direction
15 pub mod ALGODIR {
16 /// Offset (2 bits)
17 pub const offset: u32 = 2;
18 /// Mask (1 bit: 1 << 2)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Algorithm mode
29 pub mod ALGOMODE0 {
30 /// Offset (3 bits)
31 pub const offset: u32 = 3;
32 /// Mask (3 bits: 0b111 << 3)
33 pub const mask: u32 = 0b111 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// Data type selection
43 pub mod DATATYPE {
44 /// Offset (6 bits)
45 pub const offset: u32 = 6;
46 /// Mask (2 bits: 0b11 << 6)
47 pub const mask: u32 = 0b11 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// Key size selection (AES mode only)
57 pub mod KEYSIZE {
58 /// Offset (8 bits)
59 pub const offset: u32 = 8;
60 /// Mask (2 bits: 0b11 << 8)
61 pub const mask: u32 = 0b11 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// FIFO flush
71 pub mod FFLUSH {
72 /// Offset (14 bits)
73 pub const offset: u32 = 14;
74 /// Mask (1 bit: 1 << 14)
75 pub const mask: u32 = 1 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83
84 /// Cryptographic processor enable
85 pub mod CRYPEN {
86 /// Offset (15 bits)
87 pub const offset: u32 = 15;
88 /// Mask (1 bit: 1 << 15)
89 pub const mask: u32 = 1 << offset;
90 /// Read-only values (empty)
91 pub mod R {}
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values (empty)
95 pub mod RW {}
96 }
97
98 /// GCM_CCMPH
99 pub mod GCM_CCMPH {
100 /// Offset (16 bits)
101 pub const offset: u32 = 16;
102 /// Mask (2 bits: 0b11 << 16)
103 pub const mask: u32 = 0b11 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values (empty)
109 pub mod RW {}
110 }
111
112 /// ALGOMODE
113 pub mod ALGOMODE3 {
114 /// Offset (19 bits)
115 pub const offset: u32 = 19;
116 /// Mask (1 bit: 1 << 19)
117 pub const mask: u32 = 1 << offset;
118 /// Read-only values (empty)
119 pub mod R {}
120 /// Write-only values (empty)
121 pub mod W {}
122 /// Read-write values (empty)
123 pub mod RW {}
124 }
125}
126
127/// status register
128pub mod SR {
129
130 /// Busy bit
131 pub mod BUSY {
132 /// Offset (4 bits)
133 pub const offset: u32 = 4;
134 /// Mask (1 bit: 1 << 4)
135 pub const mask: u32 = 1 << offset;
136 /// Read-only values (empty)
137 pub mod R {}
138 /// Write-only values (empty)
139 pub mod W {}
140 /// Read-write values (empty)
141 pub mod RW {}
142 }
143
144 /// Output FIFO full
145 pub mod OFFU {
146 /// Offset (3 bits)
147 pub const offset: u32 = 3;
148 /// Mask (1 bit: 1 << 3)
149 pub const mask: u32 = 1 << offset;
150 /// Read-only values (empty)
151 pub mod R {}
152 /// Write-only values (empty)
153 pub mod W {}
154 /// Read-write values (empty)
155 pub mod RW {}
156 }
157
158 /// Output FIFO not empty
159 pub mod OFNE {
160 /// Offset (2 bits)
161 pub const offset: u32 = 2;
162 /// Mask (1 bit: 1 << 2)
163 pub const mask: u32 = 1 << offset;
164 /// Read-only values (empty)
165 pub mod R {}
166 /// Write-only values (empty)
167 pub mod W {}
168 /// Read-write values (empty)
169 pub mod RW {}
170 }
171
172 /// Input FIFO not full
173 pub mod IFNF {
174 /// Offset (1 bits)
175 pub const offset: u32 = 1;
176 /// Mask (1 bit: 1 << 1)
177 pub const mask: u32 = 1 << offset;
178 /// Read-only values (empty)
179 pub mod R {}
180 /// Write-only values (empty)
181 pub mod W {}
182 /// Read-write values (empty)
183 pub mod RW {}
184 }
185
186 /// Input FIFO empty
187 pub mod IFEM {
188 /// Offset (0 bits)
189 pub const offset: u32 = 0;
190 /// Mask (1 bit: 1 << 0)
191 pub const mask: u32 = 1 << offset;
192 /// Read-only values (empty)
193 pub mod R {}
194 /// Write-only values (empty)
195 pub mod W {}
196 /// Read-write values (empty)
197 pub mod RW {}
198 }
199}
200
201/// data input register
202pub mod DIN {
203
204 /// Data input
205 pub mod DATAIN {
206 /// Offset (0 bits)
207 pub const offset: u32 = 0;
208 /// Mask (32 bits: 0xffffffff << 0)
209 pub const mask: u32 = 0xffffffff << offset;
210 /// Read-only values (empty)
211 pub mod R {}
212 /// Write-only values (empty)
213 pub mod W {}
214 /// Read-write values (empty)
215 pub mod RW {}
216 }
217}
218
219/// data output register
220pub mod DOUT {
221
222 /// Data output
223 pub mod DATAOUT {
224 /// Offset (0 bits)
225 pub const offset: u32 = 0;
226 /// Mask (32 bits: 0xffffffff << 0)
227 pub const mask: u32 = 0xffffffff << offset;
228 /// Read-only values (empty)
229 pub mod R {}
230 /// Write-only values (empty)
231 pub mod W {}
232 /// Read-write values (empty)
233 pub mod RW {}
234 }
235}
236
237/// DMA control register
238pub mod DMACR {
239
240 /// DMA output enable
241 pub mod DOEN {
242 /// Offset (1 bits)
243 pub const offset: u32 = 1;
244 /// Mask (1 bit: 1 << 1)
245 pub const mask: u32 = 1 << offset;
246 /// Read-only values (empty)
247 pub mod R {}
248 /// Write-only values (empty)
249 pub mod W {}
250 /// Read-write values (empty)
251 pub mod RW {}
252 }
253
254 /// DMA input enable
255 pub mod DIEN {
256 /// Offset (0 bits)
257 pub const offset: u32 = 0;
258 /// Mask (1 bit: 1 << 0)
259 pub const mask: u32 = 1 << offset;
260 /// Read-only values (empty)
261 pub mod R {}
262 /// Write-only values (empty)
263 pub mod W {}
264 /// Read-write values (empty)
265 pub mod RW {}
266 }
267}
268
269/// interrupt mask set/clear register
270pub mod IMSCR {
271
272 /// Output FIFO service interrupt mask
273 pub mod OUTIM {
274 /// Offset (1 bits)
275 pub const offset: u32 = 1;
276 /// Mask (1 bit: 1 << 1)
277 pub const mask: u32 = 1 << offset;
278 /// Read-only values (empty)
279 pub mod R {}
280 /// Write-only values (empty)
281 pub mod W {}
282 /// Read-write values (empty)
283 pub mod RW {}
284 }
285
286 /// Input FIFO service interrupt mask
287 pub mod INIM {
288 /// Offset (0 bits)
289 pub const offset: u32 = 0;
290 /// Mask (1 bit: 1 << 0)
291 pub const mask: u32 = 1 << offset;
292 /// Read-only values (empty)
293 pub mod R {}
294 /// Write-only values (empty)
295 pub mod W {}
296 /// Read-write values (empty)
297 pub mod RW {}
298 }
299}
300
301/// raw interrupt status register
302pub mod RISR {
303
304 /// Output FIFO service raw interrupt status
305 pub mod OUTRIS {
306 /// Offset (1 bits)
307 pub const offset: u32 = 1;
308 /// Mask (1 bit: 1 << 1)
309 pub const mask: u32 = 1 << offset;
310 /// Read-only values (empty)
311 pub mod R {}
312 /// Write-only values (empty)
313 pub mod W {}
314 /// Read-write values (empty)
315 pub mod RW {}
316 }
317
318 /// Input FIFO service raw interrupt status
319 pub mod INRIS {
320 /// Offset (0 bits)
321 pub const offset: u32 = 0;
322 /// Mask (1 bit: 1 << 0)
323 pub const mask: u32 = 1 << offset;
324 /// Read-only values (empty)
325 pub mod R {}
326 /// Write-only values (empty)
327 pub mod W {}
328 /// Read-write values (empty)
329 pub mod RW {}
330 }
331}
332
333/// masked interrupt status register
334pub mod MISR {
335
336 /// Output FIFO service masked interrupt status
337 pub mod OUTMIS {
338 /// Offset (1 bits)
339 pub const offset: u32 = 1;
340 /// Mask (1 bit: 1 << 1)
341 pub const mask: u32 = 1 << offset;
342 /// Read-only values (empty)
343 pub mod R {}
344 /// Write-only values (empty)
345 pub mod W {}
346 /// Read-write values (empty)
347 pub mod RW {}
348 }
349
350 /// Input FIFO service masked interrupt status
351 pub mod INMIS {
352 /// Offset (0 bits)
353 pub const offset: u32 = 0;
354 /// Mask (1 bit: 1 << 0)
355 pub const mask: u32 = 1 << offset;
356 /// Read-only values (empty)
357 pub mod R {}
358 /// Write-only values (empty)
359 pub mod W {}
360 /// Read-write values (empty)
361 pub mod RW {}
362 }
363}
364
365/// key registers
366pub mod K0LR {
367
368 /// K224
369 pub mod K2 {
370 /// Offset (0 bits)
371 pub const offset: u32 = 0;
372 /// Mask (32 bits: 0xffffffff << 0)
373 pub const mask: u32 = 0xffffffff << offset;
374 /// Read-only values (empty)
375 pub mod R {}
376 /// Write-only values (empty)
377 pub mod W {}
378 /// Read-write values (empty)
379 pub mod RW {}
380 }
381}
382
383/// key registers
384pub mod K0RR {
385
386 /// K192
387 pub mod K {
388 /// Offset (0 bits)
389 pub const offset: u32 = 0;
390 /// Mask (32 bits: 0xffffffff << 0)
391 pub const mask: u32 = 0xffffffff << offset;
392 /// Read-only values (empty)
393 pub mod R {}
394 /// Write-only values (empty)
395 pub mod W {}
396 /// Read-write values (empty)
397 pub mod RW {}
398 }
399}
400
401/// key registers
402pub mod K1LR {
403
404 /// K160
405 pub mod K1 {
406 /// Offset (0 bits)
407 pub const offset: u32 = 0;
408 /// Mask (32 bits: 0xffffffff << 0)
409 pub const mask: u32 = 0xffffffff << offset;
410 /// Read-only values (empty)
411 pub mod R {}
412 /// Write-only values (empty)
413 pub mod W {}
414 /// Read-write values (empty)
415 pub mod RW {}
416 }
417}
418
419/// key registers
420pub mod K1RR {
421 pub use super::K1LR::K1;
422}
423
424/// key registers
425pub mod K2LR {
426 pub use super::K0RR::K;
427}
428
429/// key registers
430pub mod K2RR {
431 pub use super::K0RR::K;
432}
433
434/// key registers
435pub mod K3LR {
436 pub use super::K0RR::K;
437}
438
439/// key registers
440pub mod K3RR {
441 pub use super::K0RR::K;
442}
443
444/// initialization vector registers
445pub mod IV0LR {
446
447 /// IV31
448 pub mod IV {
449 /// Offset (0 bits)
450 pub const offset: u32 = 0;
451 /// Mask (32 bits: 0xffffffff << 0)
452 pub const mask: u32 = 0xffffffff << offset;
453 /// Read-only values (empty)
454 pub mod R {}
455 /// Write-only values (empty)
456 pub mod W {}
457 /// Read-write values (empty)
458 pub mod RW {}
459 }
460}
461
462/// initialization vector registers
463pub mod IV0RR {
464 pub use super::IV0LR::IV;
465}
466
467/// initialization vector registers
468pub mod IV1LR {
469 pub use super::IV0LR::IV;
470}
471
472/// initialization vector registers
473pub mod IV1RR {
474 pub use super::IV0LR::IV;
475}
476
477/// context swap register
478pub mod CSGCMCCM0R {
479
480 /// CSGCMCCM0
481 pub mod CSGCMCCM0 {
482 /// Offset (0 bits)
483 pub const offset: u32 = 0;
484 /// Mask (32 bits: 0xffffffff << 0)
485 pub const mask: u32 = 0xffffffff << offset;
486 /// Read-only values (empty)
487 pub mod R {}
488 /// Write-only values (empty)
489 pub mod W {}
490 /// Read-write values (empty)
491 pub mod RW {}
492 }
493}
494
495/// context swap register
496pub mod CSGCMCCM1R {
497
498 /// CSGCMCCM1
499 pub mod CSGCMCCM1 {
500 /// Offset (0 bits)
501 pub const offset: u32 = 0;
502 /// Mask (32 bits: 0xffffffff << 0)
503 pub const mask: u32 = 0xffffffff << offset;
504 /// Read-only values (empty)
505 pub mod R {}
506 /// Write-only values (empty)
507 pub mod W {}
508 /// Read-write values (empty)
509 pub mod RW {}
510 }
511}
512
513/// context swap register
514pub mod CSGCMCCM2R {
515
516 /// CSGCMCCM2
517 pub mod CSGCMCCM2 {
518 /// Offset (0 bits)
519 pub const offset: u32 = 0;
520 /// Mask (32 bits: 0xffffffff << 0)
521 pub const mask: u32 = 0xffffffff << offset;
522 /// Read-only values (empty)
523 pub mod R {}
524 /// Write-only values (empty)
525 pub mod W {}
526 /// Read-write values (empty)
527 pub mod RW {}
528 }
529}
530
531/// context swap register
532pub mod CSGCMCCM3R {
533
534 /// CSGCMCCM3
535 pub mod CSGCMCCM3 {
536 /// Offset (0 bits)
537 pub const offset: u32 = 0;
538 /// Mask (32 bits: 0xffffffff << 0)
539 pub const mask: u32 = 0xffffffff << offset;
540 /// Read-only values (empty)
541 pub mod R {}
542 /// Write-only values (empty)
543 pub mod W {}
544 /// Read-write values (empty)
545 pub mod RW {}
546 }
547}
548
549/// context swap register
550pub mod CSGCMCCM4R {
551
552 /// CSGCMCCM4
553 pub mod CSGCMCCM4 {
554 /// Offset (0 bits)
555 pub const offset: u32 = 0;
556 /// Mask (32 bits: 0xffffffff << 0)
557 pub const mask: u32 = 0xffffffff << offset;
558 /// Read-only values (empty)
559 pub mod R {}
560 /// Write-only values (empty)
561 pub mod W {}
562 /// Read-write values (empty)
563 pub mod RW {}
564 }
565}
566
567/// context swap register
568pub mod CSGCMCCM5R {
569
570 /// CSGCMCCM5
571 pub mod CSGCMCCM5 {
572 /// Offset (0 bits)
573 pub const offset: u32 = 0;
574 /// Mask (32 bits: 0xffffffff << 0)
575 pub const mask: u32 = 0xffffffff << offset;
576 /// Read-only values (empty)
577 pub mod R {}
578 /// Write-only values (empty)
579 pub mod W {}
580 /// Read-write values (empty)
581 pub mod RW {}
582 }
583}
584
585/// context swap register
586pub mod CSGCMCCM6R {
587
588 /// CSGCMCCM6
589 pub mod CSGCMCCM6 {
590 /// Offset (0 bits)
591 pub const offset: u32 = 0;
592 /// Mask (32 bits: 0xffffffff << 0)
593 pub const mask: u32 = 0xffffffff << offset;
594 /// Read-only values (empty)
595 pub mod R {}
596 /// Write-only values (empty)
597 pub mod W {}
598 /// Read-write values (empty)
599 pub mod RW {}
600 }
601}
602
603/// context swap register
604pub mod CSGCMCCM7R {
605
606 /// CSGCMCCM7
607 pub mod CSGCMCCM7 {
608 /// Offset (0 bits)
609 pub const offset: u32 = 0;
610 /// Mask (32 bits: 0xffffffff << 0)
611 pub const mask: u32 = 0xffffffff << offset;
612 /// Read-only values (empty)
613 pub mod R {}
614 /// Write-only values (empty)
615 pub mod W {}
616 /// Read-write values (empty)
617 pub mod RW {}
618 }
619}
620
621/// context swap register
622pub mod CSGCM0R {
623
624 /// CSGCM0
625 pub mod CSGCM0 {
626 /// Offset (0 bits)
627 pub const offset: u32 = 0;
628 /// Mask (32 bits: 0xffffffff << 0)
629 pub const mask: u32 = 0xffffffff << offset;
630 /// Read-only values (empty)
631 pub mod R {}
632 /// Write-only values (empty)
633 pub mod W {}
634 /// Read-write values (empty)
635 pub mod RW {}
636 }
637}
638
639/// context swap register
640pub mod CSGCM1R {
641
642 /// CSGCM1
643 pub mod CSGCM1 {
644 /// Offset (0 bits)
645 pub const offset: u32 = 0;
646 /// Mask (32 bits: 0xffffffff << 0)
647 pub const mask: u32 = 0xffffffff << offset;
648 /// Read-only values (empty)
649 pub mod R {}
650 /// Write-only values (empty)
651 pub mod W {}
652 /// Read-write values (empty)
653 pub mod RW {}
654 }
655}
656
657/// context swap register
658pub mod CSGCM2R {
659
660 /// CSGCM2
661 pub mod CSGCM2 {
662 /// Offset (0 bits)
663 pub const offset: u32 = 0;
664 /// Mask (32 bits: 0xffffffff << 0)
665 pub const mask: u32 = 0xffffffff << offset;
666 /// Read-only values (empty)
667 pub mod R {}
668 /// Write-only values (empty)
669 pub mod W {}
670 /// Read-write values (empty)
671 pub mod RW {}
672 }
673}
674
675/// context swap register
676pub mod CSGCM3R {
677
678 /// CSGCM3
679 pub mod CSGCM3 {
680 /// Offset (0 bits)
681 pub const offset: u32 = 0;
682 /// Mask (32 bits: 0xffffffff << 0)
683 pub const mask: u32 = 0xffffffff << offset;
684 /// Read-only values (empty)
685 pub mod R {}
686 /// Write-only values (empty)
687 pub mod W {}
688 /// Read-write values (empty)
689 pub mod RW {}
690 }
691}
692
693/// context swap register
694pub mod CSGCM4R {
695
696 /// CSGCM4
697 pub mod CSGCM4 {
698 /// Offset (0 bits)
699 pub const offset: u32 = 0;
700 /// Mask (32 bits: 0xffffffff << 0)
701 pub const mask: u32 = 0xffffffff << offset;
702 /// Read-only values (empty)
703 pub mod R {}
704 /// Write-only values (empty)
705 pub mod W {}
706 /// Read-write values (empty)
707 pub mod RW {}
708 }
709}
710
711/// context swap register
712pub mod CSGCM5R {
713
714 /// CSGCM5
715 pub mod CSGCM5 {
716 /// Offset (0 bits)
717 pub const offset: u32 = 0;
718 /// Mask (32 bits: 0xffffffff << 0)
719 pub const mask: u32 = 0xffffffff << offset;
720 /// Read-only values (empty)
721 pub mod R {}
722 /// Write-only values (empty)
723 pub mod W {}
724 /// Read-write values (empty)
725 pub mod RW {}
726 }
727}
728
729/// context swap register
730pub mod CSGCM6R {
731
732 /// CSGCM6
733 pub mod CSGCM6 {
734 /// Offset (0 bits)
735 pub const offset: u32 = 0;
736 /// Mask (32 bits: 0xffffffff << 0)
737 pub const mask: u32 = 0xffffffff << offset;
738 /// Read-only values (empty)
739 pub mod R {}
740 /// Write-only values (empty)
741 pub mod W {}
742 /// Read-write values (empty)
743 pub mod RW {}
744 }
745}
746
747/// context swap register
748pub mod CSGCM7R {
749
750 /// CSGCM7
751 pub mod CSGCM7 {
752 /// Offset (0 bits)
753 pub const offset: u32 = 0;
754 /// Mask (32 bits: 0xffffffff << 0)
755 pub const mask: u32 = 0xffffffff << offset;
756 /// Read-only values (empty)
757 pub mod R {}
758 /// Write-only values (empty)
759 pub mod W {}
760 /// Read-write values (empty)
761 pub mod RW {}
762 }
763}
764#[repr(C)]
765pub struct RegisterBlock {
766 /// control register
767 pub CR: RWRegister<u32>,
768
769 /// status register
770 pub SR: RORegister<u32>,
771
772 /// data input register
773 pub DIN: RWRegister<u32>,
774
775 /// data output register
776 pub DOUT: RORegister<u32>,
777
778 /// DMA control register
779 pub DMACR: RWRegister<u32>,
780
781 /// interrupt mask set/clear register
782 pub IMSCR: RWRegister<u32>,
783
784 /// raw interrupt status register
785 pub RISR: RORegister<u32>,
786
787 /// masked interrupt status register
788 pub MISR: RORegister<u32>,
789
790 /// key registers
791 pub K0LR: WORegister<u32>,
792
793 /// key registers
794 pub K0RR: WORegister<u32>,
795
796 /// key registers
797 pub K1LR: WORegister<u32>,
798
799 /// key registers
800 pub K1RR: WORegister<u32>,
801
802 /// key registers
803 pub K2LR: WORegister<u32>,
804
805 /// key registers
806 pub K2RR: WORegister<u32>,
807
808 /// key registers
809 pub K3LR: WORegister<u32>,
810
811 /// key registers
812 pub K3RR: WORegister<u32>,
813
814 /// initialization vector registers
815 pub IV0LR: RWRegister<u32>,
816
817 /// initialization vector registers
818 pub IV0RR: RWRegister<u32>,
819
820 /// initialization vector registers
821 pub IV1LR: RWRegister<u32>,
822
823 /// initialization vector registers
824 pub IV1RR: RWRegister<u32>,
825
826 /// context swap register
827 pub CSGCMCCM0R: RWRegister<u32>,
828
829 /// context swap register
830 pub CSGCMCCM1R: RWRegister<u32>,
831
832 /// context swap register
833 pub CSGCMCCM2R: RWRegister<u32>,
834
835 /// context swap register
836 pub CSGCMCCM3R: RWRegister<u32>,
837
838 /// context swap register
839 pub CSGCMCCM4R: RWRegister<u32>,
840
841 /// context swap register
842 pub CSGCMCCM5R: RWRegister<u32>,
843
844 /// context swap register
845 pub CSGCMCCM6R: RWRegister<u32>,
846
847 /// context swap register
848 pub CSGCMCCM7R: RWRegister<u32>,
849
850 /// context swap register
851 pub CSGCM0R: RWRegister<u32>,
852
853 /// context swap register
854 pub CSGCM1R: RWRegister<u32>,
855
856 /// context swap register
857 pub CSGCM2R: RWRegister<u32>,
858
859 /// context swap register
860 pub CSGCM3R: RWRegister<u32>,
861
862 /// context swap register
863 pub CSGCM4R: RWRegister<u32>,
864
865 /// context swap register
866 pub CSGCM5R: RWRegister<u32>,
867
868 /// context swap register
869 pub CSGCM6R: RWRegister<u32>,
870
871 /// context swap register
872 pub CSGCM7R: RWRegister<u32>,
873}
874pub struct ResetValues {
875 pub CR: u32,
876 pub SR: u32,
877 pub DIN: u32,
878 pub DOUT: u32,
879 pub DMACR: u32,
880 pub IMSCR: u32,
881 pub RISR: u32,
882 pub MISR: u32,
883 pub K0LR: u32,
884 pub K0RR: u32,
885 pub K1LR: u32,
886 pub K1RR: u32,
887 pub K2LR: u32,
888 pub K2RR: u32,
889 pub K3LR: u32,
890 pub K3RR: u32,
891 pub IV0LR: u32,
892 pub IV0RR: u32,
893 pub IV1LR: u32,
894 pub IV1RR: u32,
895 pub CSGCMCCM0R: u32,
896 pub CSGCMCCM1R: u32,
897 pub CSGCMCCM2R: u32,
898 pub CSGCMCCM3R: u32,
899 pub CSGCMCCM4R: u32,
900 pub CSGCMCCM5R: u32,
901 pub CSGCMCCM6R: u32,
902 pub CSGCMCCM7R: u32,
903 pub CSGCM0R: u32,
904 pub CSGCM1R: u32,
905 pub CSGCM2R: u32,
906 pub CSGCM3R: u32,
907 pub CSGCM4R: u32,
908 pub CSGCM5R: u32,
909 pub CSGCM6R: u32,
910 pub CSGCM7R: u32,
911}
912#[cfg(not(feature = "nosync"))]
913pub struct Instance {
914 pub(crate) addr: u32,
915 pub(crate) _marker: PhantomData<*const RegisterBlock>,
916}
917#[cfg(not(feature = "nosync"))]
918impl ::core::ops::Deref for Instance {
919 type Target = RegisterBlock;
920 #[inline(always)]
921 fn deref(&self) -> &RegisterBlock {
922 unsafe { &*(self.addr as *const _) }
923 }
924}
925#[cfg(feature = "rtic")]
926unsafe impl Send for Instance {}