stm32ral/stm32g4/peripherals/rcc.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Reset and clock control
4//!
5//! Used by: stm32g431, stm32g441, stm32g471, stm32g473, stm32g474, stm32g483, stm32g484, stm32g491
6
7use crate::{RORegister, RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// Clock control register
12pub mod CR {
13
14 /// Main PLL clock ready flag
15 pub mod PLLRDY {
16 /// Offset (25 bits)
17 pub const offset: u32 = 25;
18 /// Mask (1 bit: 1 << 25)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values
21 pub mod R {
22
23 /// 0b0: Clock not ready
24 pub const NotReady: u32 = 0b0;
25
26 /// 0b1: Clock ready
27 pub const Ready: u32 = 0b1;
28 }
29 /// Write-only values (empty)
30 pub mod W {}
31 /// Read-write values (empty)
32 pub mod RW {}
33 }
34
35 /// Main PLL enable
36 pub mod PLLON {
37 /// Offset (24 bits)
38 pub const offset: u32 = 24;
39 /// Mask (1 bit: 1 << 24)
40 pub const mask: u32 = 1 << offset;
41 /// Read-only values (empty)
42 pub mod R {}
43 /// Write-only values (empty)
44 pub mod W {}
45 /// Read-write values
46 pub mod RW {
47
48 /// 0b0: Clock Off
49 pub const Off: u32 = 0b0;
50
51 /// 0b1: Clock On
52 pub const On: u32 = 0b1;
53 }
54 }
55
56 /// Clock security system enable
57 pub mod CSSON {
58 /// Offset (19 bits)
59 pub const offset: u32 = 19;
60 /// Mask (1 bit: 1 << 19)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values
65 pub mod W {
66
67 /// 0b0: Clock security system disabled (clock detector OFF)
68 pub const Off: u32 = 0b0;
69
70 /// 0b1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
71 pub const On: u32 = 0b1;
72 }
73 /// Read-write values (empty)
74 pub mod RW {}
75 }
76
77 /// HSE crystal oscillator bypass
78 pub mod HSEBYP {
79 /// Offset (18 bits)
80 pub const offset: u32 = 18;
81 /// Mask (1 bit: 1 << 18)
82 pub const mask: u32 = 1 << offset;
83 /// Read-only values (empty)
84 pub mod R {}
85 /// Write-only values (empty)
86 pub mod W {}
87 /// Read-write values
88 pub mod RW {
89
90 /// 0b0: HSE crystal oscillator not bypassed
91 pub const NotBypassed: u32 = 0b0;
92
93 /// 0b1: HSE crystal oscillator bypassed with external clock
94 pub const Bypassed: u32 = 0b1;
95 }
96 }
97
98 /// HSE clock ready flag
99 pub mod HSERDY {
100 /// Offset (17 bits)
101 pub const offset: u32 = 17;
102 /// Mask (1 bit: 1 << 17)
103 pub const mask: u32 = 1 << offset;
104 pub use super::PLLRDY::R;
105 /// Write-only values (empty)
106 pub mod W {}
107 /// Read-write values (empty)
108 pub mod RW {}
109 }
110
111 /// HSE clock enable
112 pub mod HSEON {
113 /// Offset (16 bits)
114 pub const offset: u32 = 16;
115 /// Mask (1 bit: 1 << 16)
116 pub const mask: u32 = 1 << offset;
117 /// Read-only values (empty)
118 pub mod R {}
119 /// Write-only values (empty)
120 pub mod W {}
121 pub use super::PLLON::RW;
122 }
123
124 /// HSI clock ready flag
125 pub mod HSIRDY {
126 /// Offset (10 bits)
127 pub const offset: u32 = 10;
128 /// Mask (1 bit: 1 << 10)
129 pub const mask: u32 = 1 << offset;
130 pub use super::PLLRDY::R;
131 /// Write-only values (empty)
132 pub mod W {}
133 /// Read-write values (empty)
134 pub mod RW {}
135 }
136
137 /// HSI always enable for peripheral kernels
138 pub mod HSIKERON {
139 /// Offset (9 bits)
140 pub const offset: u32 = 9;
141 /// Mask (1 bit: 1 << 9)
142 pub const mask: u32 = 1 << offset;
143 /// Read-only values (empty)
144 pub mod R {}
145 /// Write-only values (empty)
146 pub mod W {}
147 /// Read-write values (empty)
148 pub mod RW {}
149 }
150
151 /// HSI clock enable
152 pub mod HSION {
153 /// Offset (8 bits)
154 pub const offset: u32 = 8;
155 /// Mask (1 bit: 1 << 8)
156 pub const mask: u32 = 1 << offset;
157 /// Read-only values (empty)
158 pub mod R {}
159 /// Write-only values (empty)
160 pub mod W {}
161 pub use super::PLLON::RW;
162 }
163}
164
165/// Internal clock sources calibration register
166pub mod ICSCR {
167
168 /// Internal High Speed clock Calibration
169 pub mod HSICAL0 {
170 /// Offset (16 bits)
171 pub const offset: u32 = 16;
172 /// Mask (8 bits: 0xff << 16)
173 pub const mask: u32 = 0xff << offset;
174 /// Read-only values (empty)
175 pub mod R {}
176 /// Write-only values (empty)
177 pub mod W {}
178 /// Read-write values (empty)
179 pub mod RW {}
180 }
181
182 /// Internal High Speed clock trimming
183 pub mod HSITRIM {
184 /// Offset (24 bits)
185 pub const offset: u32 = 24;
186 /// Mask (7 bits: 0x7f << 24)
187 pub const mask: u32 = 0x7f << offset;
188 /// Read-only values (empty)
189 pub mod R {}
190 /// Write-only values (empty)
191 pub mod W {}
192 /// Read-write values (empty)
193 pub mod RW {}
194 }
195}
196
197/// Clock configuration register
198pub mod CFGR {
199
200 /// Microcontroller clock output prescaler
201 pub mod MCOPRE {
202 /// Offset (28 bits)
203 pub const offset: u32 = 28;
204 /// Mask (3 bits: 0b111 << 28)
205 pub const mask: u32 = 0b111 << offset;
206 /// Read-only values (empty)
207 pub mod R {}
208 /// Write-only values (empty)
209 pub mod W {}
210 /// Read-write values
211 pub mod RW {
212
213 /// 0b000: MCO divided by 1
214 pub const Div1: u32 = 0b000;
215
216 /// 0b001: MCO divided by 2
217 pub const Div2: u32 = 0b001;
218
219 /// 0b010: MCO divided by 4
220 pub const Div4: u32 = 0b010;
221
222 /// 0b011: MCO divided by 8
223 pub const Div8: u32 = 0b011;
224
225 /// 0b100: MCO divided by 16
226 pub const Div16: u32 = 0b100;
227 }
228 }
229
230 /// Microcontroller clock output
231 pub mod MCOSEL {
232 /// Offset (24 bits)
233 pub const offset: u32 = 24;
234 /// Mask (4 bits: 0b1111 << 24)
235 pub const mask: u32 = 0b1111 << offset;
236 /// Read-only values (empty)
237 pub mod R {}
238 /// Write-only values (empty)
239 pub mod W {}
240 /// Read-write values
241 pub mod RW {
242
243 /// 0b0000: MCO output disabled, no clock on MCO
244 pub const None: u32 = 0b0000;
245
246 /// 0b0001: SYSCLK system clock selected
247 pub const SYSCLK: u32 = 0b0001;
248
249 /// 0b0010: MSI clock selected
250 pub const MSI: u32 = 0b0010;
251
252 /// 0b0011: HSI clock selected
253 pub const HSI: u32 = 0b0011;
254
255 /// 0b0100: HSE clock selected
256 pub const HSE: u32 = 0b0100;
257
258 /// 0b0101: Main PLL clock selected
259 pub const PLL: u32 = 0b0101;
260
261 /// 0b0110: LSI clock selected
262 pub const LSI: u32 = 0b0110;
263
264 /// 0b0111: LSE clock selected
265 pub const LSE: u32 = 0b0111;
266
267 /// 0b1000: Internal HSI48 clock selected
268 pub const HSI48: u32 = 0b1000;
269 }
270 }
271
272 /// APB high-speed prescaler (APB2)
273 pub mod PPRE2 {
274 /// Offset (11 bits)
275 pub const offset: u32 = 11;
276 /// Mask (3 bits: 0b111 << 11)
277 pub const mask: u32 = 0b111 << offset;
278 /// Read-only values (empty)
279 pub mod R {}
280 /// Write-only values (empty)
281 pub mod W {}
282 /// Read-write values
283 pub mod RW {
284
285 /// 0b000: HCLK not divided
286 pub const Div1: u32 = 0b000;
287
288 /// 0b100: HCLK divided by 2
289 pub const Div2: u32 = 0b100;
290
291 /// 0b101: HCLK divided by 4
292 pub const Div4: u32 = 0b101;
293
294 /// 0b110: HCLK divided by 8
295 pub const Div8: u32 = 0b110;
296
297 /// 0b111: HCLK divided by 16
298 pub const Div16: u32 = 0b111;
299 }
300 }
301
302 /// PB low-speed prescaler (APB1)
303 pub mod PPRE1 {
304 /// Offset (8 bits)
305 pub const offset: u32 = 8;
306 /// Mask (3 bits: 0b111 << 8)
307 pub const mask: u32 = 0b111 << offset;
308 /// Read-only values (empty)
309 pub mod R {}
310 /// Write-only values (empty)
311 pub mod W {}
312 pub use super::PPRE2::RW;
313 }
314
315 /// AHB prescaler
316 pub mod HPRE {
317 /// Offset (4 bits)
318 pub const offset: u32 = 4;
319 /// Mask (4 bits: 0b1111 << 4)
320 pub const mask: u32 = 0b1111 << offset;
321 /// Read-only values (empty)
322 pub mod R {}
323 /// Write-only values (empty)
324 pub mod W {}
325 /// Read-write values
326 pub mod RW {
327
328 /// 0b0000: SYSCLK not divided
329 pub const Div1: u32 = 0b0000;
330
331 /// 0b1000: SYSCLK divided by 2
332 pub const Div2: u32 = 0b1000;
333
334 /// 0b1001: SYSCLK divided by 4
335 pub const Div4: u32 = 0b1001;
336
337 /// 0b1010: SYSCLK divided by 8
338 pub const Div8: u32 = 0b1010;
339
340 /// 0b1011: SYSCLK divided by 16
341 pub const Div16: u32 = 0b1011;
342
343 /// 0b1100: SYSCLK divided by 64
344 pub const Div64: u32 = 0b1100;
345
346 /// 0b1101: SYSCLK divided by 128
347 pub const Div128: u32 = 0b1101;
348
349 /// 0b1110: SYSCLK divided by 256
350 pub const Div256: u32 = 0b1110;
351
352 /// 0b1111: SYSCLK divided by 512
353 pub const Div512: u32 = 0b1111;
354 }
355 }
356
357 /// System clock switch status
358 pub mod SWS {
359 /// Offset (2 bits)
360 pub const offset: u32 = 2;
361 /// Mask (2 bits: 0b11 << 2)
362 pub const mask: u32 = 0b11 << offset;
363 /// Read-only values
364 pub mod R {
365
366 /// 0b00: MSI oscillator used as system clock
367 pub const MSI: u32 = 0b00;
368
369 /// 0b01: HSI oscillator used as system clock
370 pub const HSI: u32 = 0b01;
371
372 /// 0b10: HSE used as system clock
373 pub const HSE: u32 = 0b10;
374
375 /// 0b11: PLL used as system clock
376 pub const PLL: u32 = 0b11;
377 }
378 /// Write-only values (empty)
379 pub mod W {}
380 /// Read-write values (empty)
381 pub mod RW {}
382 }
383
384 /// System clock switch
385 pub mod SW {
386 /// Offset (0 bits)
387 pub const offset: u32 = 0;
388 /// Mask (2 bits: 0b11 << 0)
389 pub const mask: u32 = 0b11 << offset;
390 /// Read-only values (empty)
391 pub mod R {}
392 /// Write-only values (empty)
393 pub mod W {}
394 /// Read-write values
395 pub mod RW {
396
397 /// 0b00: MSI selected as system clock
398 pub const MSI: u32 = 0b00;
399
400 /// 0b01: HSI selected as system clock
401 pub const HSI: u32 = 0b01;
402
403 /// 0b10: HSE selected as system clock
404 pub const HSE: u32 = 0b10;
405
406 /// 0b11: PLL selected as system clock
407 pub const PLL: u32 = 0b11;
408 }
409 }
410}
411
412/// PLL configuration register
413pub mod PLLCFGR {
414
415 /// Main PLL division factor for PLLSAI2CLK
416 pub mod PLLPDIV {
417 /// Offset (27 bits)
418 pub const offset: u32 = 27;
419 /// Mask (5 bits: 0b11111 << 27)
420 pub const mask: u32 = 0b11111 << offset;
421 /// Read-only values (empty)
422 pub mod R {}
423 /// Write-only values (empty)
424 pub mod W {}
425 /// Read-write values
426 pub mod RW {
427
428 /// 0b00000: pll_p_ck is controlled by PLLP
429 pub const PLLP: u32 = 0b00000;
430
431 /// 0b00010: pll_p_ck = vco_ck / 2
432 pub const Div2: u32 = 0b00010;
433
434 /// 0b00011: pll_p_ck = vco_ck / 3
435 pub const Div3: u32 = 0b00011;
436
437 /// 0b00100: pll_p_ck = vco_ck / 4
438 pub const Div4: u32 = 0b00100;
439
440 /// 0b00101: pll_p_ck = vco_ck / 5
441 pub const Div5: u32 = 0b00101;
442
443 /// 0b00110: pll_p_ck = vco_ck / 6
444 pub const Div6: u32 = 0b00110;
445
446 /// 0b00111: pll_p_ck = vco_ck / 7
447 pub const Div7: u32 = 0b00111;
448
449 /// 0b01000: pll_p_ck = vco_ck / 8
450 pub const Div8: u32 = 0b01000;
451
452 /// 0b01001: pll_p_ck = vco_ck / 9
453 pub const Div9: u32 = 0b01001;
454
455 /// 0b01010: pll_p_ck = vco_ck / 10
456 pub const Div10: u32 = 0b01010;
457
458 /// 0b01011: pll_p_ck = vco_ck / 11
459 pub const Div11: u32 = 0b01011;
460
461 /// 0b01100: pll_p_ck = vco_ck / 12
462 pub const Div12: u32 = 0b01100;
463
464 /// 0b01101: pll_p_ck = vco_ck / 13
465 pub const Div13: u32 = 0b01101;
466
467 /// 0b01110: pll_p_ck = vco_ck / 14
468 pub const Div14: u32 = 0b01110;
469
470 /// 0b01111: pll_p_ck = vco_ck / 15
471 pub const Div15: u32 = 0b01111;
472
473 /// 0b10000: pll_p_ck = vco_ck / 16
474 pub const Div16: u32 = 0b10000;
475
476 /// 0b10001: pll_p_ck = vco_ck / 17
477 pub const Div17: u32 = 0b10001;
478
479 /// 0b10010: pll_p_ck = vco_ck / 18
480 pub const Div18: u32 = 0b10010;
481
482 /// 0b10011: pll_p_ck = vco_ck / 19
483 pub const Div19: u32 = 0b10011;
484
485 /// 0b10100: pll_p_ck = vco_ck / 20
486 pub const Div20: u32 = 0b10100;
487
488 /// 0b10101: pll_p_ck = vco_ck / 21
489 pub const Div21: u32 = 0b10101;
490
491 /// 0b10110: pll_p_ck = vco_ck / 22
492 pub const Div22: u32 = 0b10110;
493
494 /// 0b10111: pll_p_ck = vco_ck / 23
495 pub const Div23: u32 = 0b10111;
496
497 /// 0b11000: pll_p_ck = vco_ck / 24
498 pub const Div24: u32 = 0b11000;
499
500 /// 0b11001: pll_p_ck = vco_ck / 25
501 pub const Div25: u32 = 0b11001;
502
503 /// 0b11010: pll_p_ck = vco_ck / 26
504 pub const Div26: u32 = 0b11010;
505
506 /// 0b11011: pll_p_ck = vco_ck / 27
507 pub const Div27: u32 = 0b11011;
508
509 /// 0b11100: pll_p_ck = vco_ck / 28
510 pub const Div28: u32 = 0b11100;
511
512 /// 0b11101: pll_p_ck = vco_ck / 29
513 pub const Div29: u32 = 0b11101;
514
515 /// 0b11110: pll_p_ck = vco_ck / 30
516 pub const Div30: u32 = 0b11110;
517
518 /// 0b11111: pll_p_ck = vco_ck / 31
519 pub const Div31: u32 = 0b11111;
520 }
521 }
522
523 /// Main PLL division factor for PLLCLK (system clock)
524 pub mod PLLR {
525 /// Offset (25 bits)
526 pub const offset: u32 = 25;
527 /// Mask (2 bits: 0b11 << 25)
528 pub const mask: u32 = 0b11 << offset;
529 /// Read-only values (empty)
530 pub mod R {}
531 /// Write-only values (empty)
532 pub mod W {}
533 /// Read-write values
534 pub mod RW {
535
536 /// 0b00: pll_r_ck = vco_ck / 2
537 pub const Div2: u32 = 0b00;
538
539 /// 0b01: pll_r_ck = vco_ck / 4
540 pub const Div4: u32 = 0b01;
541
542 /// 0b10: pll_r_ck = vco_ck / 6
543 pub const Div6: u32 = 0b10;
544
545 /// 0b11: pll_r_ck = vco_ck / 8
546 pub const Div8: u32 = 0b11;
547 }
548 }
549
550 /// Main PLL PLLCLK output enable
551 pub mod PLLREN {
552 /// Offset (24 bits)
553 pub const offset: u32 = 24;
554 /// Mask (1 bit: 1 << 24)
555 pub const mask: u32 = 1 << offset;
556 /// Read-only values (empty)
557 pub mod R {}
558 /// Write-only values (empty)
559 pub mod W {}
560 /// Read-write values (empty)
561 pub mod RW {}
562 }
563
564 /// Main PLL division factor for PLLUSB1CLK(48 MHz clock)
565 pub mod PLLQ {
566 /// Offset (21 bits)
567 pub const offset: u32 = 21;
568 /// Mask (2 bits: 0b11 << 21)
569 pub const mask: u32 = 0b11 << offset;
570 /// Read-only values (empty)
571 pub mod R {}
572 /// Write-only values (empty)
573 pub mod W {}
574 /// Read-write values
575 pub mod RW {
576
577 /// 0b00: pll_q_ck = vco_ck / 2
578 pub const Div2: u32 = 0b00;
579
580 /// 0b01: pll_q_ck = vco_ck / 4
581 pub const Div4: u32 = 0b01;
582
583 /// 0b10: pll_q_ck = vco_ck / 6
584 pub const Div6: u32 = 0b10;
585
586 /// 0b11: pll_q_ck = vco_ck / 8
587 pub const Div8: u32 = 0b11;
588 }
589 }
590
591 /// Main PLL PLLUSB1CLK output enable
592 pub mod PLLQEN {
593 /// Offset (20 bits)
594 pub const offset: u32 = 20;
595 /// Mask (1 bit: 1 << 20)
596 pub const mask: u32 = 1 << offset;
597 /// Read-only values (empty)
598 pub mod R {}
599 /// Write-only values (empty)
600 pub mod W {}
601 /// Read-write values (empty)
602 pub mod RW {}
603 }
604
605 /// Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
606 pub mod PLLP {
607 /// Offset (17 bits)
608 pub const offset: u32 = 17;
609 /// Mask (1 bit: 1 << 17)
610 pub const mask: u32 = 1 << offset;
611 /// Read-only values (empty)
612 pub mod R {}
613 /// Write-only values (empty)
614 pub mod W {}
615 /// Read-write values
616 pub mod RW {
617
618 /// 0b0: pll_p_ck = vco_ck / 7
619 pub const Div7: u32 = 0b0;
620
621 /// 0b1: pll_p_ck = vco_ck / 17
622 pub const Div17: u32 = 0b1;
623 }
624 }
625
626 /// Main PLL PLLSAI3CLK output enable
627 pub mod PLLPEN {
628 /// Offset (16 bits)
629 pub const offset: u32 = 16;
630 /// Mask (1 bit: 1 << 16)
631 pub const mask: u32 = 1 << offset;
632 /// Read-only values (empty)
633 pub mod R {}
634 /// Write-only values (empty)
635 pub mod W {}
636 /// Read-write values (empty)
637 pub mod RW {}
638 }
639
640 /// Main PLL multiplication factor for VCO
641 pub mod PLLN {
642 /// Offset (8 bits)
643 pub const offset: u32 = 8;
644 /// Mask (7 bits: 0x7f << 8)
645 pub const mask: u32 = 0x7f << offset;
646 /// Read-only values (empty)
647 pub mod R {}
648 /// Write-only values (empty)
649 pub mod W {}
650 /// Read-write values
651 pub mod RW {
652
653 /// 0b0001000: pll_n_ck = vco_ck / 8
654 pub const Div8: u32 = 0b0001000;
655
656 /// 0b0001001: pll_n_ck = vco_ck / 9
657 pub const Div9: u32 = 0b0001001;
658
659 /// 0b0001010: pll_n_ck = vco_ck / 10
660 pub const Div10: u32 = 0b0001010;
661
662 /// 0b0001011: pll_n_ck = vco_ck / 11
663 pub const Div11: u32 = 0b0001011;
664
665 /// 0b0001100: pll_n_ck = vco_ck / 12
666 pub const Div12: u32 = 0b0001100;
667
668 /// 0b0001101: pll_n_ck = vco_ck / 13
669 pub const Div13: u32 = 0b0001101;
670
671 /// 0b0001110: pll_n_ck = vco_ck / 14
672 pub const Div14: u32 = 0b0001110;
673
674 /// 0b0001111: pll_n_ck = vco_ck / 15
675 pub const Div15: u32 = 0b0001111;
676
677 /// 0b0010000: pll_n_ck = vco_ck / 16
678 pub const Div16: u32 = 0b0010000;
679
680 /// 0b0010001: pll_n_ck = vco_ck / 17
681 pub const Div17: u32 = 0b0010001;
682
683 /// 0b0010010: pll_n_ck = vco_ck / 18
684 pub const Div18: u32 = 0b0010010;
685
686 /// 0b0010011: pll_n_ck = vco_ck / 19
687 pub const Div19: u32 = 0b0010011;
688
689 /// 0b0010100: pll_n_ck = vco_ck / 20
690 pub const Div20: u32 = 0b0010100;
691
692 /// 0b0010101: pll_n_ck = vco_ck / 21
693 pub const Div21: u32 = 0b0010101;
694
695 /// 0b0010110: pll_n_ck = vco_ck / 22
696 pub const Div22: u32 = 0b0010110;
697
698 /// 0b0010111: pll_n_ck = vco_ck / 23
699 pub const Div23: u32 = 0b0010111;
700
701 /// 0b0011000: pll_n_ck = vco_ck / 24
702 pub const Div24: u32 = 0b0011000;
703
704 /// 0b0011001: pll_n_ck = vco_ck / 25
705 pub const Div25: u32 = 0b0011001;
706
707 /// 0b0011010: pll_n_ck = vco_ck / 26
708 pub const Div26: u32 = 0b0011010;
709
710 /// 0b0011011: pll_n_ck = vco_ck / 27
711 pub const Div27: u32 = 0b0011011;
712
713 /// 0b0011100: pll_n_ck = vco_ck / 28
714 pub const Div28: u32 = 0b0011100;
715
716 /// 0b0011101: pll_n_ck = vco_ck / 29
717 pub const Div29: u32 = 0b0011101;
718
719 /// 0b0011110: pll_n_ck = vco_ck / 30
720 pub const Div30: u32 = 0b0011110;
721
722 /// 0b0011111: pll_n_ck = vco_ck / 31
723 pub const Div31: u32 = 0b0011111;
724
725 /// 0b0100000: pll_n_ck = vco_ck / 32
726 pub const Div32: u32 = 0b0100000;
727
728 /// 0b0100001: pll_n_ck = vco_ck / 33
729 pub const Div33: u32 = 0b0100001;
730
731 /// 0b0100010: pll_n_ck = vco_ck / 34
732 pub const Div34: u32 = 0b0100010;
733
734 /// 0b0100011: pll_n_ck = vco_ck / 35
735 pub const Div35: u32 = 0b0100011;
736
737 /// 0b0100100: pll_n_ck = vco_ck / 36
738 pub const Div36: u32 = 0b0100100;
739
740 /// 0b0100101: pll_n_ck = vco_ck / 37
741 pub const Div37: u32 = 0b0100101;
742
743 /// 0b0100110: pll_n_ck = vco_ck / 38
744 pub const Div38: u32 = 0b0100110;
745
746 /// 0b0100111: pll_n_ck = vco_ck / 39
747 pub const Div39: u32 = 0b0100111;
748
749 /// 0b0101000: pll_n_ck = vco_ck / 40
750 pub const Div40: u32 = 0b0101000;
751
752 /// 0b0101001: pll_n_ck = vco_ck / 41
753 pub const Div41: u32 = 0b0101001;
754
755 /// 0b0101010: pll_n_ck = vco_ck / 42
756 pub const Div42: u32 = 0b0101010;
757
758 /// 0b0101011: pll_n_ck = vco_ck / 43
759 pub const Div43: u32 = 0b0101011;
760
761 /// 0b0101100: pll_n_ck = vco_ck / 44
762 pub const Div44: u32 = 0b0101100;
763
764 /// 0b0101101: pll_n_ck = vco_ck / 45
765 pub const Div45: u32 = 0b0101101;
766
767 /// 0b0101110: pll_n_ck = vco_ck / 46
768 pub const Div46: u32 = 0b0101110;
769
770 /// 0b0101111: pll_n_ck = vco_ck / 47
771 pub const Div47: u32 = 0b0101111;
772
773 /// 0b0110000: pll_n_ck = vco_ck / 48
774 pub const Div48: u32 = 0b0110000;
775
776 /// 0b0110001: pll_n_ck = vco_ck / 49
777 pub const Div49: u32 = 0b0110001;
778
779 /// 0b0110010: pll_n_ck = vco_ck / 50
780 pub const Div50: u32 = 0b0110010;
781
782 /// 0b0110011: pll_n_ck = vco_ck / 51
783 pub const Div51: u32 = 0b0110011;
784
785 /// 0b0110100: pll_n_ck = vco_ck / 52
786 pub const Div52: u32 = 0b0110100;
787
788 /// 0b0110101: pll_n_ck = vco_ck / 53
789 pub const Div53: u32 = 0b0110101;
790
791 /// 0b0110110: pll_n_ck = vco_ck / 54
792 pub const Div54: u32 = 0b0110110;
793
794 /// 0b0110111: pll_n_ck = vco_ck / 55
795 pub const Div55: u32 = 0b0110111;
796
797 /// 0b0111000: pll_n_ck = vco_ck / 56
798 pub const Div56: u32 = 0b0111000;
799
800 /// 0b0111001: pll_n_ck = vco_ck / 57
801 pub const Div57: u32 = 0b0111001;
802
803 /// 0b0111010: pll_n_ck = vco_ck / 58
804 pub const Div58: u32 = 0b0111010;
805
806 /// 0b0111011: pll_n_ck = vco_ck / 59
807 pub const Div59: u32 = 0b0111011;
808
809 /// 0b0111100: pll_n_ck = vco_ck / 60
810 pub const Div60: u32 = 0b0111100;
811
812 /// 0b0111101: pll_n_ck = vco_ck / 61
813 pub const Div61: u32 = 0b0111101;
814
815 /// 0b0111110: pll_n_ck = vco_ck / 62
816 pub const Div62: u32 = 0b0111110;
817
818 /// 0b0111111: pll_n_ck = vco_ck / 63
819 pub const Div63: u32 = 0b0111111;
820
821 /// 0b1000000: pll_n_ck = vco_ck / 64
822 pub const Div64: u32 = 0b1000000;
823
824 /// 0b1000001: pll_n_ck = vco_ck / 65
825 pub const Div65: u32 = 0b1000001;
826
827 /// 0b1000010: pll_n_ck = vco_ck / 66
828 pub const Div66: u32 = 0b1000010;
829
830 /// 0b1000011: pll_n_ck = vco_ck / 67
831 pub const Div67: u32 = 0b1000011;
832
833 /// 0b1000100: pll_n_ck = vco_ck / 68
834 pub const Div68: u32 = 0b1000100;
835
836 /// 0b1000101: pll_n_ck = vco_ck / 69
837 pub const Div69: u32 = 0b1000101;
838
839 /// 0b1000110: pll_n_ck = vco_ck / 70
840 pub const Div70: u32 = 0b1000110;
841
842 /// 0b1000111: pll_n_ck = vco_ck / 71
843 pub const Div71: u32 = 0b1000111;
844
845 /// 0b1001000: pll_n_ck = vco_ck / 72
846 pub const Div72: u32 = 0b1001000;
847
848 /// 0b1001001: pll_n_ck = vco_ck / 73
849 pub const Div73: u32 = 0b1001001;
850
851 /// 0b1001010: pll_n_ck = vco_ck / 74
852 pub const Div74: u32 = 0b1001010;
853
854 /// 0b1001011: pll_n_ck = vco_ck / 75
855 pub const Div75: u32 = 0b1001011;
856
857 /// 0b1001100: pll_n_ck = vco_ck / 76
858 pub const Div76: u32 = 0b1001100;
859
860 /// 0b1001101: pll_n_ck = vco_ck / 77
861 pub const Div77: u32 = 0b1001101;
862
863 /// 0b1001110: pll_n_ck = vco_ck / 78
864 pub const Div78: u32 = 0b1001110;
865
866 /// 0b1001111: pll_n_ck = vco_ck / 79
867 pub const Div79: u32 = 0b1001111;
868
869 /// 0b1010000: pll_n_ck = vco_ck / 80
870 pub const Div80: u32 = 0b1010000;
871
872 /// 0b1010001: pll_n_ck = vco_ck / 81
873 pub const Div81: u32 = 0b1010001;
874
875 /// 0b1010010: pll_n_ck = vco_ck / 82
876 pub const Div82: u32 = 0b1010010;
877
878 /// 0b1010011: pll_n_ck = vco_ck / 83
879 pub const Div83: u32 = 0b1010011;
880
881 /// 0b1010100: pll_n_ck = vco_ck / 84
882 pub const Div84: u32 = 0b1010100;
883
884 /// 0b1010101: pll_n_ck = vco_ck / 85
885 pub const Div85: u32 = 0b1010101;
886
887 /// 0b1010110: pll_n_ck = vco_ck / 86
888 pub const Div86: u32 = 0b1010110;
889
890 /// 0b1010111: pll_n_ck = vco_ck / 87
891 pub const Div87: u32 = 0b1010111;
892
893 /// 0b1011000: pll_n_ck = vco_ck / 88
894 pub const Div88: u32 = 0b1011000;
895
896 /// 0b1011001: pll_n_ck = vco_ck / 89
897 pub const Div89: u32 = 0b1011001;
898
899 /// 0b1011010: pll_n_ck = vco_ck / 90
900 pub const Div90: u32 = 0b1011010;
901
902 /// 0b1011011: pll_n_ck = vco_ck / 91
903 pub const Div91: u32 = 0b1011011;
904
905 /// 0b1011100: pll_n_ck = vco_ck / 92
906 pub const Div92: u32 = 0b1011100;
907
908 /// 0b1011101: pll_n_ck = vco_ck / 93
909 pub const Div93: u32 = 0b1011101;
910
911 /// 0b1011110: pll_n_ck = vco_ck / 94
912 pub const Div94: u32 = 0b1011110;
913
914 /// 0b1011111: pll_n_ck = vco_ck / 95
915 pub const Div95: u32 = 0b1011111;
916
917 /// 0b1100000: pll_n_ck = vco_ck / 96
918 pub const Div96: u32 = 0b1100000;
919
920 /// 0b1100001: pll_n_ck = vco_ck / 97
921 pub const Div97: u32 = 0b1100001;
922
923 /// 0b1100010: pll_n_ck = vco_ck / 98
924 pub const Div98: u32 = 0b1100010;
925
926 /// 0b1100011: pll_n_ck = vco_ck / 99
927 pub const Div99: u32 = 0b1100011;
928
929 /// 0b1100100: pll_n_ck = vco_ck / 100
930 pub const Div100: u32 = 0b1100100;
931
932 /// 0b1100101: pll_n_ck = vco_ck / 101
933 pub const Div101: u32 = 0b1100101;
934
935 /// 0b1100110: pll_n_ck = vco_ck / 102
936 pub const Div102: u32 = 0b1100110;
937
938 /// 0b1100111: pll_n_ck = vco_ck / 103
939 pub const Div103: u32 = 0b1100111;
940
941 /// 0b1101000: pll_n_ck = vco_ck / 104
942 pub const Div104: u32 = 0b1101000;
943
944 /// 0b1101001: pll_n_ck = vco_ck / 105
945 pub const Div105: u32 = 0b1101001;
946
947 /// 0b1101010: pll_n_ck = vco_ck / 106
948 pub const Div106: u32 = 0b1101010;
949
950 /// 0b1101011: pll_n_ck = vco_ck / 107
951 pub const Div107: u32 = 0b1101011;
952
953 /// 0b1101100: pll_n_ck = vco_ck / 108
954 pub const Div108: u32 = 0b1101100;
955
956 /// 0b1101101: pll_n_ck = vco_ck / 109
957 pub const Div109: u32 = 0b1101101;
958
959 /// 0b1101110: pll_n_ck = vco_ck / 110
960 pub const Div110: u32 = 0b1101110;
961
962 /// 0b1101111: pll_n_ck = vco_ck / 111
963 pub const Div111: u32 = 0b1101111;
964
965 /// 0b1110000: pll_n_ck = vco_ck / 112
966 pub const Div112: u32 = 0b1110000;
967
968 /// 0b1110001: pll_n_ck = vco_ck / 113
969 pub const Div113: u32 = 0b1110001;
970
971 /// 0b1110010: pll_n_ck = vco_ck / 114
972 pub const Div114: u32 = 0b1110010;
973
974 /// 0b1110011: pll_n_ck = vco_ck / 115
975 pub const Div115: u32 = 0b1110011;
976
977 /// 0b1110100: pll_n_ck = vco_ck / 116
978 pub const Div116: u32 = 0b1110100;
979
980 /// 0b1110101: pll_n_ck = vco_ck / 117
981 pub const Div117: u32 = 0b1110101;
982
983 /// 0b1110110: pll_n_ck = vco_ck / 118
984 pub const Div118: u32 = 0b1110110;
985
986 /// 0b1110111: pll_n_ck = vco_ck / 119
987 pub const Div119: u32 = 0b1110111;
988
989 /// 0b1111000: pll_n_ck = vco_ck / 120
990 pub const Div120: u32 = 0b1111000;
991
992 /// 0b1111001: pll_n_ck = vco_ck / 121
993 pub const Div121: u32 = 0b1111001;
994
995 /// 0b1111010: pll_n_ck = vco_ck / 122
996 pub const Div122: u32 = 0b1111010;
997
998 /// 0b1111011: pll_n_ck = vco_ck / 123
999 pub const Div123: u32 = 0b1111011;
1000
1001 /// 0b1111100: pll_n_ck = vco_ck / 124
1002 pub const Div124: u32 = 0b1111100;
1003
1004 /// 0b1111101: pll_n_ck = vco_ck / 125
1005 pub const Div125: u32 = 0b1111101;
1006
1007 /// 0b1111110: pll_n_ck = vco_ck / 126
1008 pub const Div126: u32 = 0b1111110;
1009
1010 /// 0b1111111: pll_n_ck = vco_ck / 127
1011 pub const Div127: u32 = 0b1111111;
1012 }
1013 }
1014
1015 /// Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
1016 pub mod PLLM {
1017 /// Offset (4 bits)
1018 pub const offset: u32 = 4;
1019 /// Mask (4 bits: 0b1111 << 4)
1020 pub const mask: u32 = 0b1111 << offset;
1021 /// Read-only values (empty)
1022 pub mod R {}
1023 /// Write-only values (empty)
1024 pub mod W {}
1025 /// Read-write values
1026 pub mod RW {
1027
1028 /// 0b0000: pll_p_ck = vco_ck / 1
1029 pub const Div1: u32 = 0b0000;
1030
1031 /// 0b0001: pll_p_ck = vco_ck / 2
1032 pub const Div2: u32 = 0b0001;
1033
1034 /// 0b0010: pll_p_ck = vco_ck / 3
1035 pub const Div3: u32 = 0b0010;
1036
1037 /// 0b0011: pll_p_ck = vco_ck / 4
1038 pub const Div4: u32 = 0b0011;
1039
1040 /// 0b0100: pll_p_ck = vco_ck / 5
1041 pub const Div5: u32 = 0b0100;
1042
1043 /// 0b0101: pll_p_ck = vco_ck / 6
1044 pub const Div6: u32 = 0b0101;
1045
1046 /// 0b0110: pll_p_ck = vco_ck / 7
1047 pub const Div7: u32 = 0b0110;
1048
1049 /// 0b0111: pll_p_ck = vco_ck / 8
1050 pub const Div8: u32 = 0b0111;
1051
1052 /// 0b1000: pll_p_ck = vco_ck / 9
1053 pub const Div9: u32 = 0b1000;
1054
1055 /// 0b1001: pll_p_ck = vco_ck / 10
1056 pub const Div10: u32 = 0b1001;
1057
1058 /// 0b1010: pll_p_ck = vco_ck / 11
1059 pub const Div11: u32 = 0b1010;
1060
1061 /// 0b1011: pll_p_ck = vco_ck / 12
1062 pub const Div12: u32 = 0b1011;
1063
1064 /// 0b1100: pll_p_ck = vco_ck / 13
1065 pub const Div13: u32 = 0b1100;
1066
1067 /// 0b1101: pll_p_ck = vco_ck / 14
1068 pub const Div14: u32 = 0b1101;
1069
1070 /// 0b1110: pll_p_ck = vco_ck / 15
1071 pub const Div15: u32 = 0b1110;
1072
1073 /// 0b1111: pll_p_ck = vco_ck / 16
1074 pub const Div16: u32 = 0b1111;
1075 }
1076 }
1077
1078 /// Main PLL, PLLSAI1 and PLLSAI2 entry clock source
1079 pub mod PLLSRC {
1080 /// Offset (0 bits)
1081 pub const offset: u32 = 0;
1082 /// Mask (2 bits: 0b11 << 0)
1083 pub const mask: u32 = 0b11 << offset;
1084 /// Read-only values (empty)
1085 pub mod R {}
1086 /// Write-only values (empty)
1087 pub mod W {}
1088 /// Read-write values
1089 pub mod RW {
1090
1091 /// 0b00: No clock sent to PLL
1092 pub const None: u32 = 0b00;
1093
1094 /// 0b10: No clock sent to PLL
1095 pub const HSI16: u32 = 0b10;
1096
1097 /// 0b11: No clock sent to PLL
1098 pub const HSE: u32 = 0b11;
1099 }
1100 }
1101}
1102
1103/// Clock interrupt enable register
1104pub mod CIER {
1105
1106 /// LSI ready interrupt enable
1107 pub mod LSIRDYIE {
1108 /// Offset (0 bits)
1109 pub const offset: u32 = 0;
1110 /// Mask (1 bit: 1 << 0)
1111 pub const mask: u32 = 1 << offset;
1112 /// Read-only values (empty)
1113 pub mod R {}
1114 /// Write-only values (empty)
1115 pub mod W {}
1116 /// Read-write values (empty)
1117 pub mod RW {}
1118 }
1119
1120 /// LSE ready interrupt enable
1121 pub mod LSERDYIE {
1122 /// Offset (1 bits)
1123 pub const offset: u32 = 1;
1124 /// Mask (1 bit: 1 << 1)
1125 pub const mask: u32 = 1 << offset;
1126 /// Read-only values (empty)
1127 pub mod R {}
1128 /// Write-only values (empty)
1129 pub mod W {}
1130 /// Read-write values (empty)
1131 pub mod RW {}
1132 }
1133
1134 /// HSI ready interrupt enable
1135 pub mod HSIRDYIE {
1136 /// Offset (3 bits)
1137 pub const offset: u32 = 3;
1138 /// Mask (1 bit: 1 << 3)
1139 pub const mask: u32 = 1 << offset;
1140 /// Read-only values (empty)
1141 pub mod R {}
1142 /// Write-only values (empty)
1143 pub mod W {}
1144 /// Read-write values (empty)
1145 pub mod RW {}
1146 }
1147
1148 /// HSE ready interrupt enable
1149 pub mod HSERDYIE {
1150 /// Offset (4 bits)
1151 pub const offset: u32 = 4;
1152 /// Mask (1 bit: 1 << 4)
1153 pub const mask: u32 = 1 << offset;
1154 /// Read-only values (empty)
1155 pub mod R {}
1156 /// Write-only values (empty)
1157 pub mod W {}
1158 /// Read-write values (empty)
1159 pub mod RW {}
1160 }
1161
1162 /// PLL ready interrupt enable
1163 pub mod PLLRDYIE {
1164 /// Offset (5 bits)
1165 pub const offset: u32 = 5;
1166 /// Mask (1 bit: 1 << 5)
1167 pub const mask: u32 = 1 << offset;
1168 /// Read-only values (empty)
1169 pub mod R {}
1170 /// Write-only values (empty)
1171 pub mod W {}
1172 /// Read-write values (empty)
1173 pub mod RW {}
1174 }
1175
1176 /// LSE clock security system interrupt enable
1177 pub mod LSECSSIE {
1178 /// Offset (9 bits)
1179 pub const offset: u32 = 9;
1180 /// Mask (1 bit: 1 << 9)
1181 pub const mask: u32 = 1 << offset;
1182 /// Read-only values (empty)
1183 pub mod R {}
1184 /// Write-only values (empty)
1185 pub mod W {}
1186 /// Read-write values (empty)
1187 pub mod RW {}
1188 }
1189
1190 /// HSI48 ready interrupt enable
1191 pub mod HSI48RDYIE {
1192 /// Offset (10 bits)
1193 pub const offset: u32 = 10;
1194 /// Mask (1 bit: 1 << 10)
1195 pub const mask: u32 = 1 << offset;
1196 /// Read-only values (empty)
1197 pub mod R {}
1198 /// Write-only values (empty)
1199 pub mod W {}
1200 /// Read-write values (empty)
1201 pub mod RW {}
1202 }
1203}
1204
1205/// Clock interrupt flag register
1206pub mod CIFR {
1207
1208 /// LSI ready interrupt flag
1209 pub mod LSIRDYF {
1210 /// Offset (0 bits)
1211 pub const offset: u32 = 0;
1212 /// Mask (1 bit: 1 << 0)
1213 pub const mask: u32 = 1 << offset;
1214 /// Read-only values (empty)
1215 pub mod R {}
1216 /// Write-only values (empty)
1217 pub mod W {}
1218 /// Read-write values (empty)
1219 pub mod RW {}
1220 }
1221
1222 /// LSE ready interrupt flag
1223 pub mod LSERDYF {
1224 /// Offset (1 bits)
1225 pub const offset: u32 = 1;
1226 /// Mask (1 bit: 1 << 1)
1227 pub const mask: u32 = 1 << offset;
1228 /// Read-only values (empty)
1229 pub mod R {}
1230 /// Write-only values (empty)
1231 pub mod W {}
1232 /// Read-write values (empty)
1233 pub mod RW {}
1234 }
1235
1236 /// HSI ready interrupt flag
1237 pub mod HSIRDYF {
1238 /// Offset (3 bits)
1239 pub const offset: u32 = 3;
1240 /// Mask (1 bit: 1 << 3)
1241 pub const mask: u32 = 1 << offset;
1242 /// Read-only values (empty)
1243 pub mod R {}
1244 /// Write-only values (empty)
1245 pub mod W {}
1246 /// Read-write values (empty)
1247 pub mod RW {}
1248 }
1249
1250 /// HSE ready interrupt flag
1251 pub mod HSERDYF {
1252 /// Offset (4 bits)
1253 pub const offset: u32 = 4;
1254 /// Mask (1 bit: 1 << 4)
1255 pub const mask: u32 = 1 << offset;
1256 /// Read-only values (empty)
1257 pub mod R {}
1258 /// Write-only values (empty)
1259 pub mod W {}
1260 /// Read-write values (empty)
1261 pub mod RW {}
1262 }
1263
1264 /// PLL ready interrupt flag
1265 pub mod PLLRDYF {
1266 /// Offset (5 bits)
1267 pub const offset: u32 = 5;
1268 /// Mask (1 bit: 1 << 5)
1269 pub const mask: u32 = 1 << offset;
1270 /// Read-only values (empty)
1271 pub mod R {}
1272 /// Write-only values (empty)
1273 pub mod W {}
1274 /// Read-write values (empty)
1275 pub mod RW {}
1276 }
1277
1278 /// Clock security system interrupt flag
1279 pub mod CSSF {
1280 /// Offset (8 bits)
1281 pub const offset: u32 = 8;
1282 /// Mask (1 bit: 1 << 8)
1283 pub const mask: u32 = 1 << offset;
1284 /// Read-only values (empty)
1285 pub mod R {}
1286 /// Write-only values (empty)
1287 pub mod W {}
1288 /// Read-write values (empty)
1289 pub mod RW {}
1290 }
1291
1292 /// LSE Clock security system interrupt flag
1293 pub mod LSECSSF {
1294 /// Offset (9 bits)
1295 pub const offset: u32 = 9;
1296 /// Mask (1 bit: 1 << 9)
1297 pub const mask: u32 = 1 << offset;
1298 /// Read-only values (empty)
1299 pub mod R {}
1300 /// Write-only values (empty)
1301 pub mod W {}
1302 /// Read-write values (empty)
1303 pub mod RW {}
1304 }
1305
1306 /// HSI48 ready interrupt flag
1307 pub mod HSI48RDYF {
1308 /// Offset (10 bits)
1309 pub const offset: u32 = 10;
1310 /// Mask (1 bit: 1 << 10)
1311 pub const mask: u32 = 1 << offset;
1312 /// Read-only values (empty)
1313 pub mod R {}
1314 /// Write-only values (empty)
1315 pub mod W {}
1316 /// Read-write values (empty)
1317 pub mod RW {}
1318 }
1319}
1320
1321/// Clock interrupt clear register
1322pub mod CICR {
1323
1324 /// LSI ready interrupt clear
1325 pub mod LSIRDYC {
1326 /// Offset (0 bits)
1327 pub const offset: u32 = 0;
1328 /// Mask (1 bit: 1 << 0)
1329 pub const mask: u32 = 1 << offset;
1330 /// Read-only values (empty)
1331 pub mod R {}
1332 /// Write-only values (empty)
1333 pub mod W {}
1334 /// Read-write values (empty)
1335 pub mod RW {}
1336 }
1337
1338 /// LSE ready interrupt clear
1339 pub mod LSERDYC {
1340 /// Offset (1 bits)
1341 pub const offset: u32 = 1;
1342 /// Mask (1 bit: 1 << 1)
1343 pub const mask: u32 = 1 << offset;
1344 /// Read-only values (empty)
1345 pub mod R {}
1346 /// Write-only values (empty)
1347 pub mod W {}
1348 /// Read-write values (empty)
1349 pub mod RW {}
1350 }
1351
1352 /// HSI ready interrupt clear
1353 pub mod HSIRDYC {
1354 /// Offset (3 bits)
1355 pub const offset: u32 = 3;
1356 /// Mask (1 bit: 1 << 3)
1357 pub const mask: u32 = 1 << offset;
1358 /// Read-only values (empty)
1359 pub mod R {}
1360 /// Write-only values (empty)
1361 pub mod W {}
1362 /// Read-write values (empty)
1363 pub mod RW {}
1364 }
1365
1366 /// HSE ready interrupt clear
1367 pub mod HSERDYC {
1368 /// Offset (4 bits)
1369 pub const offset: u32 = 4;
1370 /// Mask (1 bit: 1 << 4)
1371 pub const mask: u32 = 1 << offset;
1372 /// Read-only values (empty)
1373 pub mod R {}
1374 /// Write-only values (empty)
1375 pub mod W {}
1376 /// Read-write values (empty)
1377 pub mod RW {}
1378 }
1379
1380 /// PLL ready interrupt clear
1381 pub mod PLLRDYC {
1382 /// Offset (5 bits)
1383 pub const offset: u32 = 5;
1384 /// Mask (1 bit: 1 << 5)
1385 pub const mask: u32 = 1 << offset;
1386 /// Read-only values (empty)
1387 pub mod R {}
1388 /// Write-only values (empty)
1389 pub mod W {}
1390 /// Read-write values (empty)
1391 pub mod RW {}
1392 }
1393
1394 /// Clock security system interrupt clear
1395 pub mod CSSC {
1396 /// Offset (8 bits)
1397 pub const offset: u32 = 8;
1398 /// Mask (1 bit: 1 << 8)
1399 pub const mask: u32 = 1 << offset;
1400 /// Read-only values (empty)
1401 pub mod R {}
1402 /// Write-only values (empty)
1403 pub mod W {}
1404 /// Read-write values (empty)
1405 pub mod RW {}
1406 }
1407
1408 /// LSE Clock security system interrupt clear
1409 pub mod LSECSSC {
1410 /// Offset (9 bits)
1411 pub const offset: u32 = 9;
1412 /// Mask (1 bit: 1 << 9)
1413 pub const mask: u32 = 1 << offset;
1414 /// Read-only values (empty)
1415 pub mod R {}
1416 /// Write-only values (empty)
1417 pub mod W {}
1418 /// Read-write values (empty)
1419 pub mod RW {}
1420 }
1421
1422 /// HSI48 oscillator ready interrupt clear
1423 pub mod HSI48RDYC {
1424 /// Offset (10 bits)
1425 pub const offset: u32 = 10;
1426 /// Mask (1 bit: 1 << 10)
1427 pub const mask: u32 = 1 << offset;
1428 /// Read-only values (empty)
1429 pub mod R {}
1430 /// Write-only values (empty)
1431 pub mod W {}
1432 /// Read-write values (empty)
1433 pub mod RW {}
1434 }
1435}
1436
1437/// AHB1 peripheral reset register
1438pub mod AHB1RSTR {
1439
1440 /// DMA1 reset
1441 pub mod DMA1RST {
1442 /// Offset (0 bits)
1443 pub const offset: u32 = 0;
1444 /// Mask (1 bit: 1 << 0)
1445 pub const mask: u32 = 1 << offset;
1446 /// Read-only values (empty)
1447 pub mod R {}
1448 /// Write-only values (empty)
1449 pub mod W {}
1450 /// Read-write values
1451 pub mod RW {
1452
1453 /// 0b1: Reset the selected module
1454 pub const Reset: u32 = 0b1;
1455 }
1456 }
1457
1458 /// DMA2 reset
1459 pub mod DMA2RST {
1460 /// Offset (1 bits)
1461 pub const offset: u32 = 1;
1462 /// Mask (1 bit: 1 << 1)
1463 pub const mask: u32 = 1 << offset;
1464 /// Read-only values (empty)
1465 pub mod R {}
1466 /// Write-only values (empty)
1467 pub mod W {}
1468 pub use super::DMA1RST::RW;
1469 }
1470
1471 /// DMAMUXRST
1472 pub mod DMAMUX1RST {
1473 /// Offset (2 bits)
1474 pub const offset: u32 = 2;
1475 /// Mask (1 bit: 1 << 2)
1476 pub const mask: u32 = 1 << offset;
1477 /// Read-only values (empty)
1478 pub mod R {}
1479 /// Write-only values (empty)
1480 pub mod W {}
1481 pub use super::DMA1RST::RW;
1482 }
1483
1484 /// CORDIC reset
1485 pub mod CORDICRST {
1486 /// Offset (3 bits)
1487 pub const offset: u32 = 3;
1488 /// Mask (1 bit: 1 << 3)
1489 pub const mask: u32 = 1 << offset;
1490 /// Read-only values (empty)
1491 pub mod R {}
1492 /// Write-only values (empty)
1493 pub mod W {}
1494 pub use super::DMA1RST::RW;
1495 }
1496
1497 /// FMAC reset
1498 pub mod FMACRST {
1499 /// Offset (4 bits)
1500 pub const offset: u32 = 4;
1501 /// Mask (1 bit: 1 << 4)
1502 pub const mask: u32 = 1 << offset;
1503 /// Read-only values (empty)
1504 pub mod R {}
1505 /// Write-only values (empty)
1506 pub mod W {}
1507 pub use super::DMA1RST::RW;
1508 }
1509
1510 /// Flash memory interface reset
1511 pub mod FLASHRST {
1512 /// Offset (8 bits)
1513 pub const offset: u32 = 8;
1514 /// Mask (1 bit: 1 << 8)
1515 pub const mask: u32 = 1 << offset;
1516 /// Read-only values (empty)
1517 pub mod R {}
1518 /// Write-only values (empty)
1519 pub mod W {}
1520 pub use super::DMA1RST::RW;
1521 }
1522
1523 /// CRC reset
1524 pub mod CRCRST {
1525 /// Offset (12 bits)
1526 pub const offset: u32 = 12;
1527 /// Mask (1 bit: 1 << 12)
1528 pub const mask: u32 = 1 << offset;
1529 /// Read-only values (empty)
1530 pub mod R {}
1531 /// Write-only values (empty)
1532 pub mod W {}
1533 pub use super::DMA1RST::RW;
1534 }
1535}
1536
1537/// AHB2 peripheral reset register
1538pub mod AHB2RSTR {
1539
1540 /// IO port A reset
1541 pub mod GPIOARST {
1542 /// Offset (0 bits)
1543 pub const offset: u32 = 0;
1544 /// Mask (1 bit: 1 << 0)
1545 pub const mask: u32 = 1 << offset;
1546 /// Read-only values (empty)
1547 pub mod R {}
1548 /// Write-only values (empty)
1549 pub mod W {}
1550 /// Read-write values
1551 pub mod RW {
1552
1553 /// 0b1: Reset the selected module
1554 pub const Reset: u32 = 0b1;
1555 }
1556 }
1557
1558 /// IO port B reset
1559 pub mod GPIOBRST {
1560 /// Offset (1 bits)
1561 pub const offset: u32 = 1;
1562 /// Mask (1 bit: 1 << 1)
1563 pub const mask: u32 = 1 << offset;
1564 /// Read-only values (empty)
1565 pub mod R {}
1566 /// Write-only values (empty)
1567 pub mod W {}
1568 pub use super::GPIOARST::RW;
1569 }
1570
1571 /// IO port C reset
1572 pub mod GPIOCRST {
1573 /// Offset (2 bits)
1574 pub const offset: u32 = 2;
1575 /// Mask (1 bit: 1 << 2)
1576 pub const mask: u32 = 1 << offset;
1577 /// Read-only values (empty)
1578 pub mod R {}
1579 /// Write-only values (empty)
1580 pub mod W {}
1581 pub use super::GPIOARST::RW;
1582 }
1583
1584 /// IO port D reset
1585 pub mod GPIODRST {
1586 /// Offset (3 bits)
1587 pub const offset: u32 = 3;
1588 /// Mask (1 bit: 1 << 3)
1589 pub const mask: u32 = 1 << offset;
1590 /// Read-only values (empty)
1591 pub mod R {}
1592 /// Write-only values (empty)
1593 pub mod W {}
1594 pub use super::GPIOARST::RW;
1595 }
1596
1597 /// IO port E reset
1598 pub mod GPIOERST {
1599 /// Offset (4 bits)
1600 pub const offset: u32 = 4;
1601 /// Mask (1 bit: 1 << 4)
1602 pub const mask: u32 = 1 << offset;
1603 /// Read-only values (empty)
1604 pub mod R {}
1605 /// Write-only values (empty)
1606 pub mod W {}
1607 pub use super::GPIOARST::RW;
1608 }
1609
1610 /// IO port F reset
1611 pub mod GPIOFRST {
1612 /// Offset (5 bits)
1613 pub const offset: u32 = 5;
1614 /// Mask (1 bit: 1 << 5)
1615 pub const mask: u32 = 1 << offset;
1616 /// Read-only values (empty)
1617 pub mod R {}
1618 /// Write-only values (empty)
1619 pub mod W {}
1620 pub use super::GPIOARST::RW;
1621 }
1622
1623 /// IO port G reset
1624 pub mod GPIOGRST {
1625 /// Offset (6 bits)
1626 pub const offset: u32 = 6;
1627 /// Mask (1 bit: 1 << 6)
1628 pub const mask: u32 = 1 << offset;
1629 /// Read-only values (empty)
1630 pub mod R {}
1631 /// Write-only values (empty)
1632 pub mod W {}
1633 pub use super::GPIOARST::RW;
1634 }
1635
1636 /// ADC reset
1637 pub mod ADC12RST {
1638 /// Offset (13 bits)
1639 pub const offset: u32 = 13;
1640 /// Mask (1 bit: 1 << 13)
1641 pub const mask: u32 = 1 << offset;
1642 /// Read-only values (empty)
1643 pub mod R {}
1644 /// Write-only values (empty)
1645 pub mod W {}
1646 pub use super::GPIOARST::RW;
1647 }
1648
1649 /// SAR ADC345 interface reset
1650 pub mod ADC345RST {
1651 /// Offset (14 bits)
1652 pub const offset: u32 = 14;
1653 /// Mask (1 bit: 1 << 14)
1654 pub const mask: u32 = 1 << offset;
1655 /// Read-only values (empty)
1656 pub mod R {}
1657 /// Write-only values (empty)
1658 pub mod W {}
1659 pub use super::GPIOARST::RW;
1660 }
1661
1662 /// DAC1 interface reset
1663 pub mod DAC1RST {
1664 /// Offset (16 bits)
1665 pub const offset: u32 = 16;
1666 /// Mask (1 bit: 1 << 16)
1667 pub const mask: u32 = 1 << offset;
1668 /// Read-only values (empty)
1669 pub mod R {}
1670 /// Write-only values (empty)
1671 pub mod W {}
1672 pub use super::GPIOARST::RW;
1673 }
1674
1675 /// DAC2 interface reset
1676 pub mod DAC2RST {
1677 /// Offset (17 bits)
1678 pub const offset: u32 = 17;
1679 /// Mask (1 bit: 1 << 17)
1680 pub const mask: u32 = 1 << offset;
1681 /// Read-only values (empty)
1682 pub mod R {}
1683 /// Write-only values (empty)
1684 pub mod W {}
1685 pub use super::GPIOARST::RW;
1686 }
1687
1688 /// DAC3 interface reset
1689 pub mod DAC3RST {
1690 /// Offset (18 bits)
1691 pub const offset: u32 = 18;
1692 /// Mask (1 bit: 1 << 18)
1693 pub const mask: u32 = 1 << offset;
1694 /// Read-only values (empty)
1695 pub mod R {}
1696 /// Write-only values (empty)
1697 pub mod W {}
1698 pub use super::GPIOARST::RW;
1699 }
1700
1701 /// DAC4 interface reset
1702 pub mod DAC4RST {
1703 /// Offset (19 bits)
1704 pub const offset: u32 = 19;
1705 /// Mask (1 bit: 1 << 19)
1706 pub const mask: u32 = 1 << offset;
1707 /// Read-only values (empty)
1708 pub mod R {}
1709 /// Write-only values (empty)
1710 pub mod W {}
1711 pub use super::GPIOARST::RW;
1712 }
1713
1714 /// Cryptography module reset
1715 pub mod AESRST {
1716 /// Offset (24 bits)
1717 pub const offset: u32 = 24;
1718 /// Mask (1 bit: 1 << 24)
1719 pub const mask: u32 = 1 << offset;
1720 /// Read-only values (empty)
1721 pub mod R {}
1722 /// Write-only values (empty)
1723 pub mod W {}
1724 pub use super::GPIOARST::RW;
1725 }
1726
1727 /// Random Number Generator module reset
1728 pub mod RNGRST {
1729 /// Offset (26 bits)
1730 pub const offset: u32 = 26;
1731 /// Mask (1 bit: 1 << 26)
1732 pub const mask: u32 = 1 << offset;
1733 /// Read-only values (empty)
1734 pub mod R {}
1735 /// Write-only values (empty)
1736 pub mod W {}
1737 pub use super::GPIOARST::RW;
1738 }
1739}
1740
1741/// AHB3 peripheral reset register
1742pub mod AHB3RSTR {
1743
1744 /// Flexible memory controller reset
1745 pub mod FMCRST {
1746 /// Offset (0 bits)
1747 pub const offset: u32 = 0;
1748 /// Mask (1 bit: 1 << 0)
1749 pub const mask: u32 = 1 << offset;
1750 /// Read-only values (empty)
1751 pub mod R {}
1752 /// Write-only values (empty)
1753 pub mod W {}
1754 /// Read-write values
1755 pub mod RW {
1756
1757 /// 0b1: Reset the selected module
1758 pub const Reset: u32 = 0b1;
1759 }
1760 }
1761
1762 /// Quad SPI 1 module reset
1763 pub mod QSPIRST {
1764 /// Offset (8 bits)
1765 pub const offset: u32 = 8;
1766 /// Mask (1 bit: 1 << 8)
1767 pub const mask: u32 = 1 << offset;
1768 /// Read-only values (empty)
1769 pub mod R {}
1770 /// Write-only values (empty)
1771 pub mod W {}
1772 pub use super::FMCRST::RW;
1773 }
1774}
1775
1776/// APB1 peripheral reset register 1
1777pub mod APB1RSTR1 {
1778
1779 /// Low Power Timer 1 reset
1780 pub mod LPTIM1RST {
1781 /// Offset (31 bits)
1782 pub const offset: u32 = 31;
1783 /// Mask (1 bit: 1 << 31)
1784 pub const mask: u32 = 1 << offset;
1785 /// Read-only values (empty)
1786 pub mod R {}
1787 /// Write-only values (empty)
1788 pub mod W {}
1789 /// Read-write values
1790 pub mod RW {
1791
1792 /// 0b1: Reset the selected module
1793 pub const Reset: u32 = 0b1;
1794 }
1795 }
1796
1797 /// I2C3 interface reset
1798 pub mod I2C3RST {
1799 /// Offset (30 bits)
1800 pub const offset: u32 = 30;
1801 /// Mask (1 bit: 1 << 30)
1802 pub const mask: u32 = 1 << offset;
1803 /// Read-only values (empty)
1804 pub mod R {}
1805 /// Write-only values (empty)
1806 pub mod W {}
1807 pub use super::LPTIM1RST::RW;
1808 }
1809
1810 /// Power interface reset
1811 pub mod PWRRST {
1812 /// Offset (28 bits)
1813 pub const offset: u32 = 28;
1814 /// Mask (1 bit: 1 << 28)
1815 pub const mask: u32 = 1 << offset;
1816 /// Read-only values (empty)
1817 pub mod R {}
1818 /// Write-only values (empty)
1819 pub mod W {}
1820 pub use super::LPTIM1RST::RW;
1821 }
1822
1823 /// FDCAN reset
1824 pub mod FDCANRST {
1825 /// Offset (25 bits)
1826 pub const offset: u32 = 25;
1827 /// Mask (1 bit: 1 << 25)
1828 pub const mask: u32 = 1 << offset;
1829 /// Read-only values (empty)
1830 pub mod R {}
1831 /// Write-only values (empty)
1832 pub mod W {}
1833 pub use super::LPTIM1RST::RW;
1834 }
1835
1836 /// USBD reset
1837 pub mod USBRST {
1838 /// Offset (23 bits)
1839 pub const offset: u32 = 23;
1840 /// Mask (1 bit: 1 << 23)
1841 pub const mask: u32 = 1 << offset;
1842 /// Read-only values (empty)
1843 pub mod R {}
1844 /// Write-only values (empty)
1845 pub mod W {}
1846 pub use super::LPTIM1RST::RW;
1847 }
1848
1849 /// I2C2 reset
1850 pub mod I2C2RST {
1851 /// Offset (22 bits)
1852 pub const offset: u32 = 22;
1853 /// Mask (1 bit: 1 << 22)
1854 pub const mask: u32 = 1 << offset;
1855 /// Read-only values (empty)
1856 pub mod R {}
1857 /// Write-only values (empty)
1858 pub mod W {}
1859 pub use super::LPTIM1RST::RW;
1860 }
1861
1862 /// I2C1 reset
1863 pub mod I2C1RST {
1864 /// Offset (21 bits)
1865 pub const offset: u32 = 21;
1866 /// Mask (1 bit: 1 << 21)
1867 pub const mask: u32 = 1 << offset;
1868 /// Read-only values (empty)
1869 pub mod R {}
1870 /// Write-only values (empty)
1871 pub mod W {}
1872 pub use super::LPTIM1RST::RW;
1873 }
1874
1875 /// UART5 reset
1876 pub mod UART5RST {
1877 /// Offset (20 bits)
1878 pub const offset: u32 = 20;
1879 /// Mask (1 bit: 1 << 20)
1880 pub const mask: u32 = 1 << offset;
1881 /// Read-only values (empty)
1882 pub mod R {}
1883 /// Write-only values (empty)
1884 pub mod W {}
1885 pub use super::LPTIM1RST::RW;
1886 }
1887
1888 /// UART4 reset
1889 pub mod UART4RST {
1890 /// Offset (19 bits)
1891 pub const offset: u32 = 19;
1892 /// Mask (1 bit: 1 << 19)
1893 pub const mask: u32 = 1 << offset;
1894 /// Read-only values (empty)
1895 pub mod R {}
1896 /// Write-only values (empty)
1897 pub mod W {}
1898 pub use super::LPTIM1RST::RW;
1899 }
1900
1901 /// USART3 reset
1902 pub mod USART3RST {
1903 /// Offset (18 bits)
1904 pub const offset: u32 = 18;
1905 /// Mask (1 bit: 1 << 18)
1906 pub const mask: u32 = 1 << offset;
1907 /// Read-only values (empty)
1908 pub mod R {}
1909 /// Write-only values (empty)
1910 pub mod W {}
1911 pub use super::LPTIM1RST::RW;
1912 }
1913
1914 /// USART2 reset
1915 pub mod USART2RST {
1916 /// Offset (17 bits)
1917 pub const offset: u32 = 17;
1918 /// Mask (1 bit: 1 << 17)
1919 pub const mask: u32 = 1 << offset;
1920 /// Read-only values (empty)
1921 pub mod R {}
1922 /// Write-only values (empty)
1923 pub mod W {}
1924 pub use super::LPTIM1RST::RW;
1925 }
1926
1927 /// SPI3 reset
1928 pub mod SPI3RST {
1929 /// Offset (15 bits)
1930 pub const offset: u32 = 15;
1931 /// Mask (1 bit: 1 << 15)
1932 pub const mask: u32 = 1 << offset;
1933 /// Read-only values (empty)
1934 pub mod R {}
1935 /// Write-only values (empty)
1936 pub mod W {}
1937 pub use super::LPTIM1RST::RW;
1938 }
1939
1940 /// SPI2 reset
1941 pub mod SPI2RST {
1942 /// Offset (14 bits)
1943 pub const offset: u32 = 14;
1944 /// Mask (1 bit: 1 << 14)
1945 pub const mask: u32 = 1 << offset;
1946 /// Read-only values (empty)
1947 pub mod R {}
1948 /// Write-only values (empty)
1949 pub mod W {}
1950 pub use super::LPTIM1RST::RW;
1951 }
1952
1953 /// Clock recovery system reset
1954 pub mod CRSRST {
1955 /// Offset (8 bits)
1956 pub const offset: u32 = 8;
1957 /// Mask (1 bit: 1 << 8)
1958 pub const mask: u32 = 1 << offset;
1959 /// Read-only values (empty)
1960 pub mod R {}
1961 /// Write-only values (empty)
1962 pub mod W {}
1963 pub use super::LPTIM1RST::RW;
1964 }
1965
1966 /// TIM7 timer reset
1967 pub mod TIM7RST {
1968 /// Offset (5 bits)
1969 pub const offset: u32 = 5;
1970 /// Mask (1 bit: 1 << 5)
1971 pub const mask: u32 = 1 << offset;
1972 /// Read-only values (empty)
1973 pub mod R {}
1974 /// Write-only values (empty)
1975 pub mod W {}
1976 pub use super::LPTIM1RST::RW;
1977 }
1978
1979 /// TIM6 timer reset
1980 pub mod TIM6RST {
1981 /// Offset (4 bits)
1982 pub const offset: u32 = 4;
1983 /// Mask (1 bit: 1 << 4)
1984 pub const mask: u32 = 1 << offset;
1985 /// Read-only values (empty)
1986 pub mod R {}
1987 /// Write-only values (empty)
1988 pub mod W {}
1989 pub use super::LPTIM1RST::RW;
1990 }
1991
1992 /// TIM5 timer reset
1993 pub mod TIM5RST {
1994 /// Offset (3 bits)
1995 pub const offset: u32 = 3;
1996 /// Mask (1 bit: 1 << 3)
1997 pub const mask: u32 = 1 << offset;
1998 /// Read-only values (empty)
1999 pub mod R {}
2000 /// Write-only values (empty)
2001 pub mod W {}
2002 pub use super::LPTIM1RST::RW;
2003 }
2004
2005 /// TIM3 timer reset
2006 pub mod TIM4RST {
2007 /// Offset (2 bits)
2008 pub const offset: u32 = 2;
2009 /// Mask (1 bit: 1 << 2)
2010 pub const mask: u32 = 1 << offset;
2011 /// Read-only values (empty)
2012 pub mod R {}
2013 /// Write-only values (empty)
2014 pub mod W {}
2015 pub use super::LPTIM1RST::RW;
2016 }
2017
2018 /// TIM3 timer reset
2019 pub mod TIM3RST {
2020 /// Offset (1 bits)
2021 pub const offset: u32 = 1;
2022 /// Mask (1 bit: 1 << 1)
2023 pub const mask: u32 = 1 << offset;
2024 /// Read-only values (empty)
2025 pub mod R {}
2026 /// Write-only values (empty)
2027 pub mod W {}
2028 pub use super::LPTIM1RST::RW;
2029 }
2030
2031 /// TIM2 timer reset
2032 pub mod TIM2RST {
2033 /// Offset (0 bits)
2034 pub const offset: u32 = 0;
2035 /// Mask (1 bit: 1 << 0)
2036 pub const mask: u32 = 1 << offset;
2037 /// Read-only values (empty)
2038 pub mod R {}
2039 /// Write-only values (empty)
2040 pub mod W {}
2041 pub use super::LPTIM1RST::RW;
2042 }
2043}
2044
2045/// APB1 peripheral reset register 2
2046pub mod APB1RSTR2 {
2047
2048 /// Low-power UART 1 reset
2049 pub mod LPUART1RST {
2050 /// Offset (0 bits)
2051 pub const offset: u32 = 0;
2052 /// Mask (1 bit: 1 << 0)
2053 pub const mask: u32 = 1 << offset;
2054 /// Read-only values (empty)
2055 pub mod R {}
2056 /// Write-only values (empty)
2057 pub mod W {}
2058 /// Read-write values
2059 pub mod RW {
2060
2061 /// 0b1: Reset the selected module
2062 pub const Reset: u32 = 0b1;
2063 }
2064 }
2065
2066 /// I2C4 reset
2067 pub mod I2C4RST {
2068 /// Offset (1 bits)
2069 pub const offset: u32 = 1;
2070 /// Mask (1 bit: 1 << 1)
2071 pub const mask: u32 = 1 << offset;
2072 /// Read-only values (empty)
2073 pub mod R {}
2074 /// Write-only values (empty)
2075 pub mod W {}
2076 pub use super::LPUART1RST::RW;
2077 }
2078
2079 /// UCPD1 reset
2080 pub mod UCPD1RST {
2081 /// Offset (8 bits)
2082 pub const offset: u32 = 8;
2083 /// Mask (1 bit: 1 << 8)
2084 pub const mask: u32 = 1 << offset;
2085 /// Read-only values (empty)
2086 pub mod R {}
2087 /// Write-only values (empty)
2088 pub mod W {}
2089 pub use super::LPUART1RST::RW;
2090 }
2091}
2092
2093/// APB2 peripheral reset register
2094pub mod APB2RSTR {
2095
2096 /// System configuration (SYSCFG) reset
2097 pub mod SYSCFGRST {
2098 /// Offset (0 bits)
2099 pub const offset: u32 = 0;
2100 /// Mask (1 bit: 1 << 0)
2101 pub const mask: u32 = 1 << offset;
2102 /// Read-only values (empty)
2103 pub mod R {}
2104 /// Write-only values (empty)
2105 pub mod W {}
2106 /// Read-write values
2107 pub mod RW {
2108
2109 /// 0b1: Reset the selected module
2110 pub const Reset: u32 = 0b1;
2111 }
2112 }
2113
2114 /// TIM1 timer reset
2115 pub mod TIM1RST {
2116 /// Offset (11 bits)
2117 pub const offset: u32 = 11;
2118 /// Mask (1 bit: 1 << 11)
2119 pub const mask: u32 = 1 << offset;
2120 /// Read-only values (empty)
2121 pub mod R {}
2122 /// Write-only values (empty)
2123 pub mod W {}
2124 pub use super::SYSCFGRST::RW;
2125 }
2126
2127 /// SPI1 reset
2128 pub mod SPI1RST {
2129 /// Offset (12 bits)
2130 pub const offset: u32 = 12;
2131 /// Mask (1 bit: 1 << 12)
2132 pub const mask: u32 = 1 << offset;
2133 /// Read-only values (empty)
2134 pub mod R {}
2135 /// Write-only values (empty)
2136 pub mod W {}
2137 pub use super::SYSCFGRST::RW;
2138 }
2139
2140 /// TIM8 timer reset
2141 pub mod TIM8RST {
2142 /// Offset (13 bits)
2143 pub const offset: u32 = 13;
2144 /// Mask (1 bit: 1 << 13)
2145 pub const mask: u32 = 1 << offset;
2146 /// Read-only values (empty)
2147 pub mod R {}
2148 /// Write-only values (empty)
2149 pub mod W {}
2150 pub use super::SYSCFGRST::RW;
2151 }
2152
2153 /// USART1 reset
2154 pub mod USART1RST {
2155 /// Offset (14 bits)
2156 pub const offset: u32 = 14;
2157 /// Mask (1 bit: 1 << 14)
2158 pub const mask: u32 = 1 << offset;
2159 /// Read-only values (empty)
2160 pub mod R {}
2161 /// Write-only values (empty)
2162 pub mod W {}
2163 pub use super::SYSCFGRST::RW;
2164 }
2165
2166 /// SPI 4 reset
2167 pub mod SPI4RST {
2168 /// Offset (15 bits)
2169 pub const offset: u32 = 15;
2170 /// Mask (1 bit: 1 << 15)
2171 pub const mask: u32 = 1 << offset;
2172 /// Read-only values (empty)
2173 pub mod R {}
2174 /// Write-only values (empty)
2175 pub mod W {}
2176 pub use super::SYSCFGRST::RW;
2177 }
2178
2179 /// TIM15 timer reset
2180 pub mod TIM15RST {
2181 /// Offset (16 bits)
2182 pub const offset: u32 = 16;
2183 /// Mask (1 bit: 1 << 16)
2184 pub const mask: u32 = 1 << offset;
2185 /// Read-only values (empty)
2186 pub mod R {}
2187 /// Write-only values (empty)
2188 pub mod W {}
2189 pub use super::SYSCFGRST::RW;
2190 }
2191
2192 /// TIM16 timer reset
2193 pub mod TIM16RST {
2194 /// Offset (17 bits)
2195 pub const offset: u32 = 17;
2196 /// Mask (1 bit: 1 << 17)
2197 pub const mask: u32 = 1 << offset;
2198 /// Read-only values (empty)
2199 pub mod R {}
2200 /// Write-only values (empty)
2201 pub mod W {}
2202 pub use super::SYSCFGRST::RW;
2203 }
2204
2205 /// TIM17 timer reset
2206 pub mod TIM17RST {
2207 /// Offset (18 bits)
2208 pub const offset: u32 = 18;
2209 /// Mask (1 bit: 1 << 18)
2210 pub const mask: u32 = 1 << offset;
2211 /// Read-only values (empty)
2212 pub mod R {}
2213 /// Write-only values (empty)
2214 pub mod W {}
2215 pub use super::SYSCFGRST::RW;
2216 }
2217
2218 /// Timer 20 reset
2219 pub mod TIM20RST {
2220 /// Offset (20 bits)
2221 pub const offset: u32 = 20;
2222 /// Mask (1 bit: 1 << 20)
2223 pub const mask: u32 = 1 << offset;
2224 /// Read-only values (empty)
2225 pub mod R {}
2226 /// Write-only values (empty)
2227 pub mod W {}
2228 pub use super::SYSCFGRST::RW;
2229 }
2230
2231 /// Serial audio interface 1 (SAI1) reset
2232 pub mod SAI1RST {
2233 /// Offset (21 bits)
2234 pub const offset: u32 = 21;
2235 /// Mask (1 bit: 1 << 21)
2236 pub const mask: u32 = 1 << offset;
2237 /// Read-only values (empty)
2238 pub mod R {}
2239 /// Write-only values (empty)
2240 pub mod W {}
2241 pub use super::SYSCFGRST::RW;
2242 }
2243
2244 /// HRTIMER reset
2245 pub mod HRTIM1RST {
2246 /// Offset (26 bits)
2247 pub const offset: u32 = 26;
2248 /// Mask (1 bit: 1 << 26)
2249 pub const mask: u32 = 1 << offset;
2250 /// Read-only values (empty)
2251 pub mod R {}
2252 /// Write-only values (empty)
2253 pub mod W {}
2254 pub use super::SYSCFGRST::RW;
2255 }
2256}
2257
2258/// AHB1 peripheral clock enable register
2259pub mod AHB1ENR {
2260
2261 /// DMA1 clock enable
2262 pub mod DMA1EN {
2263 /// Offset (0 bits)
2264 pub const offset: u32 = 0;
2265 /// Mask (1 bit: 1 << 0)
2266 pub const mask: u32 = 1 << offset;
2267 /// Read-only values (empty)
2268 pub mod R {}
2269 /// Write-only values (empty)
2270 pub mod W {}
2271 /// Read-write values
2272 pub mod RW {
2273
2274 /// 0b0: The selected clock is disabled
2275 pub const Disabled: u32 = 0b0;
2276
2277 /// 0b1: The selected clock is enabled
2278 pub const Enabled: u32 = 0b1;
2279 }
2280 }
2281
2282 /// DMA2 clock enable
2283 pub mod DMA2EN {
2284 /// Offset (1 bits)
2285 pub const offset: u32 = 1;
2286 /// Mask (1 bit: 1 << 1)
2287 pub const mask: u32 = 1 << offset;
2288 /// Read-only values (empty)
2289 pub mod R {}
2290 /// Write-only values (empty)
2291 pub mod W {}
2292 pub use super::DMA1EN::RW;
2293 }
2294
2295 /// DMAMUX clock enable
2296 pub mod DMAMUXEN {
2297 /// Offset (2 bits)
2298 pub const offset: u32 = 2;
2299 /// Mask (1 bit: 1 << 2)
2300 pub const mask: u32 = 1 << offset;
2301 /// Read-only values (empty)
2302 pub mod R {}
2303 /// Write-only values (empty)
2304 pub mod W {}
2305 pub use super::DMA1EN::RW;
2306 }
2307
2308 /// CORDIC clock enable
2309 pub mod CORDICEN {
2310 /// Offset (3 bits)
2311 pub const offset: u32 = 3;
2312 /// Mask (1 bit: 1 << 3)
2313 pub const mask: u32 = 1 << offset;
2314 /// Read-only values (empty)
2315 pub mod R {}
2316 /// Write-only values (empty)
2317 pub mod W {}
2318 pub use super::DMA1EN::RW;
2319 }
2320
2321 /// FMAC clock enable
2322 pub mod FMACEN {
2323 /// Offset (4 bits)
2324 pub const offset: u32 = 4;
2325 /// Mask (1 bit: 1 << 4)
2326 pub const mask: u32 = 1 << offset;
2327 /// Read-only values (empty)
2328 pub mod R {}
2329 /// Write-only values (empty)
2330 pub mod W {}
2331 pub use super::DMA1EN::RW;
2332 }
2333
2334 /// Flash memory interface clock enable
2335 pub mod FLASHEN {
2336 /// Offset (8 bits)
2337 pub const offset: u32 = 8;
2338 /// Mask (1 bit: 1 << 8)
2339 pub const mask: u32 = 1 << offset;
2340 /// Read-only values (empty)
2341 pub mod R {}
2342 /// Write-only values (empty)
2343 pub mod W {}
2344 pub use super::DMA1EN::RW;
2345 }
2346
2347 /// CRC clock enable
2348 pub mod CRCEN {
2349 /// Offset (12 bits)
2350 pub const offset: u32 = 12;
2351 /// Mask (1 bit: 1 << 12)
2352 pub const mask: u32 = 1 << offset;
2353 /// Read-only values (empty)
2354 pub mod R {}
2355 /// Write-only values (empty)
2356 pub mod W {}
2357 pub use super::DMA1EN::RW;
2358 }
2359}
2360
2361/// AHB2 peripheral clock enable register
2362pub mod AHB2ENR {
2363
2364 /// IO port A clock enable
2365 pub mod GPIOAEN {
2366 /// Offset (0 bits)
2367 pub const offset: u32 = 0;
2368 /// Mask (1 bit: 1 << 0)
2369 pub const mask: u32 = 1 << offset;
2370 /// Read-only values (empty)
2371 pub mod R {}
2372 /// Write-only values (empty)
2373 pub mod W {}
2374 /// Read-write values
2375 pub mod RW {
2376
2377 /// 0b0: The selected clock is disabled
2378 pub const Disabled: u32 = 0b0;
2379
2380 /// 0b1: The selected clock is enabled
2381 pub const Enabled: u32 = 0b1;
2382 }
2383 }
2384
2385 /// IO port B clock enable
2386 pub mod GPIOBEN {
2387 /// Offset (1 bits)
2388 pub const offset: u32 = 1;
2389 /// Mask (1 bit: 1 << 1)
2390 pub const mask: u32 = 1 << offset;
2391 /// Read-only values (empty)
2392 pub mod R {}
2393 /// Write-only values (empty)
2394 pub mod W {}
2395 pub use super::GPIOAEN::RW;
2396 }
2397
2398 /// IO port C clock enable
2399 pub mod GPIOCEN {
2400 /// Offset (2 bits)
2401 pub const offset: u32 = 2;
2402 /// Mask (1 bit: 1 << 2)
2403 pub const mask: u32 = 1 << offset;
2404 /// Read-only values (empty)
2405 pub mod R {}
2406 /// Write-only values (empty)
2407 pub mod W {}
2408 pub use super::GPIOAEN::RW;
2409 }
2410
2411 /// IO port D clock enable
2412 pub mod GPIODEN {
2413 /// Offset (3 bits)
2414 pub const offset: u32 = 3;
2415 /// Mask (1 bit: 1 << 3)
2416 pub const mask: u32 = 1 << offset;
2417 /// Read-only values (empty)
2418 pub mod R {}
2419 /// Write-only values (empty)
2420 pub mod W {}
2421 pub use super::GPIOAEN::RW;
2422 }
2423
2424 /// IO port E clock enable
2425 pub mod GPIOEEN {
2426 /// Offset (4 bits)
2427 pub const offset: u32 = 4;
2428 /// Mask (1 bit: 1 << 4)
2429 pub const mask: u32 = 1 << offset;
2430 /// Read-only values (empty)
2431 pub mod R {}
2432 /// Write-only values (empty)
2433 pub mod W {}
2434 pub use super::GPIOAEN::RW;
2435 }
2436
2437 /// IO port F clock enable
2438 pub mod GPIOFEN {
2439 /// Offset (5 bits)
2440 pub const offset: u32 = 5;
2441 /// Mask (1 bit: 1 << 5)
2442 pub const mask: u32 = 1 << offset;
2443 /// Read-only values (empty)
2444 pub mod R {}
2445 /// Write-only values (empty)
2446 pub mod W {}
2447 pub use super::GPIOAEN::RW;
2448 }
2449
2450 /// IO port G clock enable
2451 pub mod GPIOGEN {
2452 /// Offset (6 bits)
2453 pub const offset: u32 = 6;
2454 /// Mask (1 bit: 1 << 6)
2455 pub const mask: u32 = 1 << offset;
2456 /// Read-only values (empty)
2457 pub mod R {}
2458 /// Write-only values (empty)
2459 pub mod W {}
2460 pub use super::GPIOAEN::RW;
2461 }
2462
2463 /// ADC clock enable
2464 pub mod ADC12EN {
2465 /// Offset (13 bits)
2466 pub const offset: u32 = 13;
2467 /// Mask (1 bit: 1 << 13)
2468 pub const mask: u32 = 1 << offset;
2469 /// Read-only values (empty)
2470 pub mod R {}
2471 /// Write-only values (empty)
2472 pub mod W {}
2473 pub use super::GPIOAEN::RW;
2474 }
2475
2476 /// DCMI clock enable
2477 pub mod ADC345EN {
2478 /// Offset (14 bits)
2479 pub const offset: u32 = 14;
2480 /// Mask (1 bit: 1 << 14)
2481 pub const mask: u32 = 1 << offset;
2482 /// Read-only values (empty)
2483 pub mod R {}
2484 /// Write-only values (empty)
2485 pub mod W {}
2486 pub use super::GPIOAEN::RW;
2487 }
2488
2489 /// AES accelerator clock enable
2490 pub mod DAC1EN {
2491 /// Offset (16 bits)
2492 pub const offset: u32 = 16;
2493 /// Mask (1 bit: 1 << 16)
2494 pub const mask: u32 = 1 << offset;
2495 /// Read-only values (empty)
2496 pub mod R {}
2497 /// Write-only values (empty)
2498 pub mod W {}
2499 pub use super::GPIOAEN::RW;
2500 }
2501
2502 /// HASH clock enable
2503 pub mod DAC2EN {
2504 /// Offset (17 bits)
2505 pub const offset: u32 = 17;
2506 /// Mask (1 bit: 1 << 17)
2507 pub const mask: u32 = 1 << offset;
2508 /// Read-only values (empty)
2509 pub mod R {}
2510 /// Write-only values (empty)
2511 pub mod W {}
2512 pub use super::GPIOAEN::RW;
2513 }
2514
2515 /// Random Number Generator clock enable
2516 pub mod DAC3EN {
2517 /// Offset (18 bits)
2518 pub const offset: u32 = 18;
2519 /// Mask (1 bit: 1 << 18)
2520 pub const mask: u32 = 1 << offset;
2521 /// Read-only values (empty)
2522 pub mod R {}
2523 /// Write-only values (empty)
2524 pub mod W {}
2525 pub use super::GPIOAEN::RW;
2526 }
2527
2528 /// DAC4 clock enable
2529 pub mod DAC4EN {
2530 /// Offset (19 bits)
2531 pub const offset: u32 = 19;
2532 /// Mask (1 bit: 1 << 19)
2533 pub const mask: u32 = 1 << offset;
2534 /// Read-only values (empty)
2535 pub mod R {}
2536 /// Write-only values (empty)
2537 pub mod W {}
2538 pub use super::GPIOAEN::RW;
2539 }
2540
2541 /// AES clock enable
2542 pub mod AESEN {
2543 /// Offset (24 bits)
2544 pub const offset: u32 = 24;
2545 /// Mask (1 bit: 1 << 24)
2546 pub const mask: u32 = 1 << offset;
2547 /// Read-only values (empty)
2548 pub mod R {}
2549 /// Write-only values (empty)
2550 pub mod W {}
2551 pub use super::GPIOAEN::RW;
2552 }
2553
2554 /// Random Number Generator clock enable
2555 pub mod RNGEN {
2556 /// Offset (26 bits)
2557 pub const offset: u32 = 26;
2558 /// Mask (1 bit: 1 << 26)
2559 pub const mask: u32 = 1 << offset;
2560 /// Read-only values (empty)
2561 pub mod R {}
2562 /// Write-only values (empty)
2563 pub mod W {}
2564 pub use super::GPIOAEN::RW;
2565 }
2566}
2567
2568/// AHB3 peripheral clock enable register
2569pub mod AHB3ENR {
2570
2571 /// Flexible memory controller clock enable
2572 pub mod FMCEN {
2573 /// Offset (0 bits)
2574 pub const offset: u32 = 0;
2575 /// Mask (1 bit: 1 << 0)
2576 pub const mask: u32 = 1 << offset;
2577 /// Read-only values (empty)
2578 pub mod R {}
2579 /// Write-only values (empty)
2580 pub mod W {}
2581 /// Read-write values
2582 pub mod RW {
2583
2584 /// 0b0: The selected clock is disabled
2585 pub const Disabled: u32 = 0b0;
2586
2587 /// 0b1: The selected clock is enabled
2588 pub const Enabled: u32 = 0b1;
2589 }
2590 }
2591
2592 /// QUADSPI memory interface clock enable
2593 pub mod QSPIEN {
2594 /// Offset (8 bits)
2595 pub const offset: u32 = 8;
2596 /// Mask (1 bit: 1 << 8)
2597 pub const mask: u32 = 1 << offset;
2598 /// Read-only values (empty)
2599 pub mod R {}
2600 /// Write-only values (empty)
2601 pub mod W {}
2602 pub use super::FMCEN::RW;
2603 }
2604}
2605
2606/// APB1ENR1
2607pub mod APB1ENR1 {
2608
2609 /// TIM2 timer clock enable
2610 pub mod TIM2EN {
2611 /// Offset (0 bits)
2612 pub const offset: u32 = 0;
2613 /// Mask (1 bit: 1 << 0)
2614 pub const mask: u32 = 1 << offset;
2615 /// Read-only values (empty)
2616 pub mod R {}
2617 /// Write-only values (empty)
2618 pub mod W {}
2619 /// Read-write values
2620 pub mod RW {
2621
2622 /// 0b0: The selected clock is disabled
2623 pub const Disabled: u32 = 0b0;
2624
2625 /// 0b1: The selected clock is enabled
2626 pub const Enabled: u32 = 0b1;
2627 }
2628 }
2629
2630 /// TIM3 timer clock enable
2631 pub mod TIM3EN {
2632 /// Offset (1 bits)
2633 pub const offset: u32 = 1;
2634 /// Mask (1 bit: 1 << 1)
2635 pub const mask: u32 = 1 << offset;
2636 /// Read-only values (empty)
2637 pub mod R {}
2638 /// Write-only values (empty)
2639 pub mod W {}
2640 pub use super::TIM2EN::RW;
2641 }
2642
2643 /// TIM4 timer clock enable
2644 pub mod TIM4EN {
2645 /// Offset (2 bits)
2646 pub const offset: u32 = 2;
2647 /// Mask (1 bit: 1 << 2)
2648 pub const mask: u32 = 1 << offset;
2649 /// Read-only values (empty)
2650 pub mod R {}
2651 /// Write-only values (empty)
2652 pub mod W {}
2653 pub use super::TIM2EN::RW;
2654 }
2655
2656 /// TIM5 timer clock enable
2657 pub mod TIM5EN {
2658 /// Offset (3 bits)
2659 pub const offset: u32 = 3;
2660 /// Mask (1 bit: 1 << 3)
2661 pub const mask: u32 = 1 << offset;
2662 /// Read-only values (empty)
2663 pub mod R {}
2664 /// Write-only values (empty)
2665 pub mod W {}
2666 pub use super::TIM2EN::RW;
2667 }
2668
2669 /// TIM6 timer clock enable
2670 pub mod TIM6EN {
2671 /// Offset (4 bits)
2672 pub const offset: u32 = 4;
2673 /// Mask (1 bit: 1 << 4)
2674 pub const mask: u32 = 1 << offset;
2675 /// Read-only values (empty)
2676 pub mod R {}
2677 /// Write-only values (empty)
2678 pub mod W {}
2679 pub use super::TIM2EN::RW;
2680 }
2681
2682 /// TIM7 timer clock enable
2683 pub mod TIM7EN {
2684 /// Offset (5 bits)
2685 pub const offset: u32 = 5;
2686 /// Mask (1 bit: 1 << 5)
2687 pub const mask: u32 = 1 << offset;
2688 /// Read-only values (empty)
2689 pub mod R {}
2690 /// Write-only values (empty)
2691 pub mod W {}
2692 pub use super::TIM2EN::RW;
2693 }
2694
2695 /// CRSclock enable
2696 pub mod CRSEN {
2697 /// Offset (8 bits)
2698 pub const offset: u32 = 8;
2699 /// Mask (1 bit: 1 << 8)
2700 pub const mask: u32 = 1 << offset;
2701 /// Read-only values (empty)
2702 pub mod R {}
2703 /// Write-only values (empty)
2704 pub mod W {}
2705 pub use super::TIM2EN::RW;
2706 }
2707
2708 /// RTC APB clock enable
2709 pub mod RTCAPBEN {
2710 /// Offset (10 bits)
2711 pub const offset: u32 = 10;
2712 /// Mask (1 bit: 1 << 10)
2713 pub const mask: u32 = 1 << offset;
2714 /// Read-only values (empty)
2715 pub mod R {}
2716 /// Write-only values (empty)
2717 pub mod W {}
2718 pub use super::TIM2EN::RW;
2719 }
2720
2721 /// Window watchdog clock enable
2722 pub mod WWDGEN {
2723 /// Offset (11 bits)
2724 pub const offset: u32 = 11;
2725 /// Mask (1 bit: 1 << 11)
2726 pub const mask: u32 = 1 << offset;
2727 /// Read-only values (empty)
2728 pub mod R {}
2729 /// Write-only values (empty)
2730 pub mod W {}
2731 pub use super::TIM2EN::RW;
2732 }
2733
2734 /// SPI2 clock enable
2735 pub mod SPI2EN {
2736 /// Offset (14 bits)
2737 pub const offset: u32 = 14;
2738 /// Mask (1 bit: 1 << 14)
2739 pub const mask: u32 = 1 << offset;
2740 /// Read-only values (empty)
2741 pub mod R {}
2742 /// Write-only values (empty)
2743 pub mod W {}
2744 pub use super::TIM2EN::RW;
2745 }
2746
2747 /// SPI3 clock enable
2748 pub mod SPI3EN {
2749 /// Offset (15 bits)
2750 pub const offset: u32 = 15;
2751 /// Mask (1 bit: 1 << 15)
2752 pub const mask: u32 = 1 << offset;
2753 /// Read-only values (empty)
2754 pub mod R {}
2755 /// Write-only values (empty)
2756 pub mod W {}
2757 pub use super::TIM2EN::RW;
2758 }
2759
2760 /// USART2 clock enable
2761 pub mod USART2EN {
2762 /// Offset (17 bits)
2763 pub const offset: u32 = 17;
2764 /// Mask (1 bit: 1 << 17)
2765 pub const mask: u32 = 1 << offset;
2766 /// Read-only values (empty)
2767 pub mod R {}
2768 /// Write-only values (empty)
2769 pub mod W {}
2770 pub use super::TIM2EN::RW;
2771 }
2772
2773 /// USART3 clock enable
2774 pub mod USART3EN {
2775 /// Offset (18 bits)
2776 pub const offset: u32 = 18;
2777 /// Mask (1 bit: 1 << 18)
2778 pub const mask: u32 = 1 << offset;
2779 /// Read-only values (empty)
2780 pub mod R {}
2781 /// Write-only values (empty)
2782 pub mod W {}
2783 pub use super::TIM2EN::RW;
2784 }
2785
2786 /// UART4 clock enable
2787 pub mod UART4EN {
2788 /// Offset (19 bits)
2789 pub const offset: u32 = 19;
2790 /// Mask (1 bit: 1 << 19)
2791 pub const mask: u32 = 1 << offset;
2792 /// Read-only values (empty)
2793 pub mod R {}
2794 /// Write-only values (empty)
2795 pub mod W {}
2796 pub use super::TIM2EN::RW;
2797 }
2798
2799 /// UART5 clock enable
2800 pub mod UART5EN {
2801 /// Offset (20 bits)
2802 pub const offset: u32 = 20;
2803 /// Mask (1 bit: 1 << 20)
2804 pub const mask: u32 = 1 << offset;
2805 /// Read-only values (empty)
2806 pub mod R {}
2807 /// Write-only values (empty)
2808 pub mod W {}
2809 pub use super::TIM2EN::RW;
2810 }
2811
2812 /// I2C1 clock enable
2813 pub mod I2C1EN {
2814 /// Offset (21 bits)
2815 pub const offset: u32 = 21;
2816 /// Mask (1 bit: 1 << 21)
2817 pub const mask: u32 = 1 << offset;
2818 /// Read-only values (empty)
2819 pub mod R {}
2820 /// Write-only values (empty)
2821 pub mod W {}
2822 pub use super::TIM2EN::RW;
2823 }
2824
2825 /// I2C2 clock enable
2826 pub mod I2C2EN {
2827 /// Offset (22 bits)
2828 pub const offset: u32 = 22;
2829 /// Mask (1 bit: 1 << 22)
2830 pub const mask: u32 = 1 << offset;
2831 /// Read-only values (empty)
2832 pub mod R {}
2833 /// Write-only values (empty)
2834 pub mod W {}
2835 pub use super::TIM2EN::RW;
2836 }
2837
2838 /// USB device clock enable
2839 pub mod USBEN {
2840 /// Offset (23 bits)
2841 pub const offset: u32 = 23;
2842 /// Mask (1 bit: 1 << 23)
2843 pub const mask: u32 = 1 << offset;
2844 /// Read-only values (empty)
2845 pub mod R {}
2846 /// Write-only values (empty)
2847 pub mod W {}
2848 pub use super::TIM2EN::RW;
2849 }
2850
2851 /// FDCAN clock enable
2852 pub mod FDCANEN {
2853 /// Offset (25 bits)
2854 pub const offset: u32 = 25;
2855 /// Mask (1 bit: 1 << 25)
2856 pub const mask: u32 = 1 << offset;
2857 /// Read-only values (empty)
2858 pub mod R {}
2859 /// Write-only values (empty)
2860 pub mod W {}
2861 pub use super::TIM2EN::RW;
2862 }
2863
2864 /// Power interface clock enable
2865 pub mod PWREN {
2866 /// Offset (28 bits)
2867 pub const offset: u32 = 28;
2868 /// Mask (1 bit: 1 << 28)
2869 pub const mask: u32 = 1 << offset;
2870 /// Read-only values (empty)
2871 pub mod R {}
2872 /// Write-only values (empty)
2873 pub mod W {}
2874 pub use super::TIM2EN::RW;
2875 }
2876
2877 /// I2C3 clock enable
2878 pub mod I2C3EN {
2879 /// Offset (30 bits)
2880 pub const offset: u32 = 30;
2881 /// Mask (1 bit: 1 << 30)
2882 pub const mask: u32 = 1 << offset;
2883 /// Read-only values (empty)
2884 pub mod R {}
2885 /// Write-only values (empty)
2886 pub mod W {}
2887 pub use super::TIM2EN::RW;
2888 }
2889
2890 /// Low power timer 1 clock enable
2891 pub mod LPTIM1EN {
2892 /// Offset (31 bits)
2893 pub const offset: u32 = 31;
2894 /// Mask (1 bit: 1 << 31)
2895 pub const mask: u32 = 1 << offset;
2896 /// Read-only values (empty)
2897 pub mod R {}
2898 /// Write-only values (empty)
2899 pub mod W {}
2900 pub use super::TIM2EN::RW;
2901 }
2902}
2903
2904/// APB1 peripheral clock enable register 2
2905pub mod APB1ENR2 {
2906
2907 /// Low power UART 1 clock enable
2908 pub mod LPUART1EN {
2909 /// Offset (0 bits)
2910 pub const offset: u32 = 0;
2911 /// Mask (1 bit: 1 << 0)
2912 pub const mask: u32 = 1 << offset;
2913 /// Read-only values (empty)
2914 pub mod R {}
2915 /// Write-only values (empty)
2916 pub mod W {}
2917 /// Read-write values
2918 pub mod RW {
2919
2920 /// 0b0: The selected clock is disabled
2921 pub const Disabled: u32 = 0b0;
2922
2923 /// 0b1: The selected clock is enabled
2924 pub const Enabled: u32 = 0b1;
2925 }
2926 }
2927
2928 /// I2C4 clock enable
2929 pub mod I2C4EN {
2930 /// Offset (1 bits)
2931 pub const offset: u32 = 1;
2932 /// Mask (1 bit: 1 << 1)
2933 pub const mask: u32 = 1 << offset;
2934 /// Read-only values (empty)
2935 pub mod R {}
2936 /// Write-only values (empty)
2937 pub mod W {}
2938 pub use super::LPUART1EN::RW;
2939 }
2940
2941 /// UCPD1 clock enable
2942 pub mod UCPD1EN {
2943 /// Offset (8 bits)
2944 pub const offset: u32 = 8;
2945 /// Mask (1 bit: 1 << 8)
2946 pub const mask: u32 = 1 << offset;
2947 /// Read-only values (empty)
2948 pub mod R {}
2949 /// Write-only values (empty)
2950 pub mod W {}
2951 pub use super::LPUART1EN::RW;
2952 }
2953}
2954
2955/// APB2ENR
2956pub mod APB2ENR {
2957
2958 /// SYSCFG clock enable
2959 pub mod SYSCFGEN {
2960 /// Offset (0 bits)
2961 pub const offset: u32 = 0;
2962 /// Mask (1 bit: 1 << 0)
2963 pub const mask: u32 = 1 << offset;
2964 /// Read-only values (empty)
2965 pub mod R {}
2966 /// Write-only values (empty)
2967 pub mod W {}
2968 /// Read-write values
2969 pub mod RW {
2970
2971 /// 0b0: The selected clock is disabled
2972 pub const Disabled: u32 = 0b0;
2973
2974 /// 0b1: The selected clock is enabled
2975 pub const Enabled: u32 = 0b1;
2976 }
2977 }
2978
2979 /// TIM1 timer clock enable
2980 pub mod TIM1EN {
2981 /// Offset (11 bits)
2982 pub const offset: u32 = 11;
2983 /// Mask (1 bit: 1 << 11)
2984 pub const mask: u32 = 1 << offset;
2985 /// Read-only values (empty)
2986 pub mod R {}
2987 /// Write-only values (empty)
2988 pub mod W {}
2989 pub use super::SYSCFGEN::RW;
2990 }
2991
2992 /// SPI1 clock enable
2993 pub mod SPI1EN {
2994 /// Offset (12 bits)
2995 pub const offset: u32 = 12;
2996 /// Mask (1 bit: 1 << 12)
2997 pub const mask: u32 = 1 << offset;
2998 /// Read-only values (empty)
2999 pub mod R {}
3000 /// Write-only values (empty)
3001 pub mod W {}
3002 pub use super::SYSCFGEN::RW;
3003 }
3004
3005 /// TIM8 timer clock enable
3006 pub mod TIM8EN {
3007 /// Offset (13 bits)
3008 pub const offset: u32 = 13;
3009 /// Mask (1 bit: 1 << 13)
3010 pub const mask: u32 = 1 << offset;
3011 /// Read-only values (empty)
3012 pub mod R {}
3013 /// Write-only values (empty)
3014 pub mod W {}
3015 pub use super::SYSCFGEN::RW;
3016 }
3017
3018 /// USART1clock enable
3019 pub mod USART1EN {
3020 /// Offset (14 bits)
3021 pub const offset: u32 = 14;
3022 /// Mask (1 bit: 1 << 14)
3023 pub const mask: u32 = 1 << offset;
3024 /// Read-only values (empty)
3025 pub mod R {}
3026 /// Write-only values (empty)
3027 pub mod W {}
3028 pub use super::SYSCFGEN::RW;
3029 }
3030
3031 /// SPI 4 clock enable
3032 pub mod SPI4EN {
3033 /// Offset (15 bits)
3034 pub const offset: u32 = 15;
3035 /// Mask (1 bit: 1 << 15)
3036 pub const mask: u32 = 1 << offset;
3037 /// Read-only values (empty)
3038 pub mod R {}
3039 /// Write-only values (empty)
3040 pub mod W {}
3041 pub use super::SYSCFGEN::RW;
3042 }
3043
3044 /// TIM15 timer clock enable
3045 pub mod TIM15EN {
3046 /// Offset (16 bits)
3047 pub const offset: u32 = 16;
3048 /// Mask (1 bit: 1 << 16)
3049 pub const mask: u32 = 1 << offset;
3050 /// Read-only values (empty)
3051 pub mod R {}
3052 /// Write-only values (empty)
3053 pub mod W {}
3054 pub use super::SYSCFGEN::RW;
3055 }
3056
3057 /// TIM16 timer clock enable
3058 pub mod TIM16EN {
3059 /// Offset (17 bits)
3060 pub const offset: u32 = 17;
3061 /// Mask (1 bit: 1 << 17)
3062 pub const mask: u32 = 1 << offset;
3063 /// Read-only values (empty)
3064 pub mod R {}
3065 /// Write-only values (empty)
3066 pub mod W {}
3067 pub use super::SYSCFGEN::RW;
3068 }
3069
3070 /// TIM17 timer clock enable
3071 pub mod TIM17EN {
3072 /// Offset (18 bits)
3073 pub const offset: u32 = 18;
3074 /// Mask (1 bit: 1 << 18)
3075 pub const mask: u32 = 1 << offset;
3076 /// Read-only values (empty)
3077 pub mod R {}
3078 /// Write-only values (empty)
3079 pub mod W {}
3080 pub use super::SYSCFGEN::RW;
3081 }
3082
3083 /// Timer 20 clock enable
3084 pub mod TIM20EN {
3085 /// Offset (20 bits)
3086 pub const offset: u32 = 20;
3087 /// Mask (1 bit: 1 << 20)
3088 pub const mask: u32 = 1 << offset;
3089 /// Read-only values (empty)
3090 pub mod R {}
3091 /// Write-only values (empty)
3092 pub mod W {}
3093 pub use super::SYSCFGEN::RW;
3094 }
3095
3096 /// SAI1 clock enable
3097 pub mod SAI1EN {
3098 /// Offset (21 bits)
3099 pub const offset: u32 = 21;
3100 /// Mask (1 bit: 1 << 21)
3101 pub const mask: u32 = 1 << offset;
3102 /// Read-only values (empty)
3103 pub mod R {}
3104 /// Write-only values (empty)
3105 pub mod W {}
3106 pub use super::SYSCFGEN::RW;
3107 }
3108
3109 /// HRTIMER clock enable
3110 pub mod HRTIM1EN {
3111 /// Offset (26 bits)
3112 pub const offset: u32 = 26;
3113 /// Mask (1 bit: 1 << 26)
3114 pub const mask: u32 = 1 << offset;
3115 /// Read-only values (empty)
3116 pub mod R {}
3117 /// Write-only values (empty)
3118 pub mod W {}
3119 pub use super::SYSCFGEN::RW;
3120 }
3121}
3122
3123/// AHB1 peripheral clocks enable in Sleep and Stop modes register
3124pub mod AHB1SMENR {
3125
3126 /// DMA1 clocks enable during Sleep and Stop modes
3127 pub mod DMA1SMEN {
3128 /// Offset (0 bits)
3129 pub const offset: u32 = 0;
3130 /// Mask (1 bit: 1 << 0)
3131 pub const mask: u32 = 1 << offset;
3132 /// Read-only values (empty)
3133 pub mod R {}
3134 /// Write-only values (empty)
3135 pub mod W {}
3136 /// Read-write values (empty)
3137 pub mod RW {}
3138 }
3139
3140 /// DMA2 clocks enable during Sleep and Stop modes
3141 pub mod DMA2SMEN {
3142 /// Offset (1 bits)
3143 pub const offset: u32 = 1;
3144 /// Mask (1 bit: 1 << 1)
3145 pub const mask: u32 = 1 << offset;
3146 /// Read-only values (empty)
3147 pub mod R {}
3148 /// Write-only values (empty)
3149 pub mod W {}
3150 /// Read-write values (empty)
3151 pub mod RW {}
3152 }
3153
3154 /// DMAMUX clock enable during Sleep and Stop modes
3155 pub mod DMAMUX1SMEN {
3156 /// Offset (2 bits)
3157 pub const offset: u32 = 2;
3158 /// Mask (1 bit: 1 << 2)
3159 pub const mask: u32 = 1 << offset;
3160 /// Read-only values (empty)
3161 pub mod R {}
3162 /// Write-only values (empty)
3163 pub mod W {}
3164 /// Read-write values (empty)
3165 pub mod RW {}
3166 }
3167
3168 /// CORDIC clock enable during sleep mode
3169 pub mod CORDICSMEN {
3170 /// Offset (3 bits)
3171 pub const offset: u32 = 3;
3172 /// Mask (1 bit: 1 << 3)
3173 pub const mask: u32 = 1 << offset;
3174 /// Read-only values (empty)
3175 pub mod R {}
3176 /// Write-only values (empty)
3177 pub mod W {}
3178 /// Read-write values (empty)
3179 pub mod RW {}
3180 }
3181
3182 /// Flash memory interface clocks enable during Sleep and Stop modes
3183 pub mod FLASHSMEN {
3184 /// Offset (8 bits)
3185 pub const offset: u32 = 8;
3186 /// Mask (1 bit: 1 << 8)
3187 pub const mask: u32 = 1 << offset;
3188 /// Read-only values (empty)
3189 pub mod R {}
3190 /// Write-only values (empty)
3191 pub mod W {}
3192 /// Read-write values (empty)
3193 pub mod RW {}
3194 }
3195
3196 /// SRAM1 interface clocks enable during Sleep and Stop modes
3197 pub mod SRAM1SMEN {
3198 /// Offset (9 bits)
3199 pub const offset: u32 = 9;
3200 /// Mask (1 bit: 1 << 9)
3201 pub const mask: u32 = 1 << offset;
3202 /// Read-only values (empty)
3203 pub mod R {}
3204 /// Write-only values (empty)
3205 pub mod W {}
3206 /// Read-write values (empty)
3207 pub mod RW {}
3208 }
3209
3210 /// CRCSMEN
3211 pub mod CRCSMEN {
3212 /// Offset (12 bits)
3213 pub const offset: u32 = 12;
3214 /// Mask (1 bit: 1 << 12)
3215 pub const mask: u32 = 1 << offset;
3216 /// Read-only values (empty)
3217 pub mod R {}
3218 /// Write-only values (empty)
3219 pub mod W {}
3220 /// Read-write values (empty)
3221 pub mod RW {}
3222 }
3223
3224 /// FMACSM clock enable
3225 pub mod FMACSMEN {
3226 /// Offset (4 bits)
3227 pub const offset: u32 = 4;
3228 /// Mask (1 bit: 1 << 4)
3229 pub const mask: u32 = 1 << offset;
3230 /// Read-only values (empty)
3231 pub mod R {}
3232 /// Write-only values (empty)
3233 pub mod W {}
3234 /// Read-write values (empty)
3235 pub mod RW {}
3236 }
3237}
3238
3239/// AHB2 peripheral clocks enable in Sleep and Stop modes register
3240pub mod AHB2SMENR {
3241
3242 /// IO port A clocks enable during Sleep and Stop modes
3243 pub mod GPIOASMEN {
3244 /// Offset (0 bits)
3245 pub const offset: u32 = 0;
3246 /// Mask (1 bit: 1 << 0)
3247 pub const mask: u32 = 1 << offset;
3248 /// Read-only values (empty)
3249 pub mod R {}
3250 /// Write-only values (empty)
3251 pub mod W {}
3252 /// Read-write values (empty)
3253 pub mod RW {}
3254 }
3255
3256 /// IO port B clocks enable during Sleep and Stop modes
3257 pub mod GPIOBSMEN {
3258 /// Offset (1 bits)
3259 pub const offset: u32 = 1;
3260 /// Mask (1 bit: 1 << 1)
3261 pub const mask: u32 = 1 << offset;
3262 /// Read-only values (empty)
3263 pub mod R {}
3264 /// Write-only values (empty)
3265 pub mod W {}
3266 /// Read-write values (empty)
3267 pub mod RW {}
3268 }
3269
3270 /// IO port C clocks enable during Sleep and Stop modes
3271 pub mod GPIOCSMEN {
3272 /// Offset (2 bits)
3273 pub const offset: u32 = 2;
3274 /// Mask (1 bit: 1 << 2)
3275 pub const mask: u32 = 1 << offset;
3276 /// Read-only values (empty)
3277 pub mod R {}
3278 /// Write-only values (empty)
3279 pub mod W {}
3280 /// Read-write values (empty)
3281 pub mod RW {}
3282 }
3283
3284 /// IO port D clocks enable during Sleep and Stop modes
3285 pub mod GPIODSMEN {
3286 /// Offset (3 bits)
3287 pub const offset: u32 = 3;
3288 /// Mask (1 bit: 1 << 3)
3289 pub const mask: u32 = 1 << offset;
3290 /// Read-only values (empty)
3291 pub mod R {}
3292 /// Write-only values (empty)
3293 pub mod W {}
3294 /// Read-write values (empty)
3295 pub mod RW {}
3296 }
3297
3298 /// IO port E clocks enable during Sleep and Stop modes
3299 pub mod GPIOESMEN {
3300 /// Offset (4 bits)
3301 pub const offset: u32 = 4;
3302 /// Mask (1 bit: 1 << 4)
3303 pub const mask: u32 = 1 << offset;
3304 /// Read-only values (empty)
3305 pub mod R {}
3306 /// Write-only values (empty)
3307 pub mod W {}
3308 /// Read-write values (empty)
3309 pub mod RW {}
3310 }
3311
3312 /// IO port F clocks enable during Sleep and Stop modes
3313 pub mod GPIOFSMEN {
3314 /// Offset (5 bits)
3315 pub const offset: u32 = 5;
3316 /// Mask (1 bit: 1 << 5)
3317 pub const mask: u32 = 1 << offset;
3318 /// Read-only values (empty)
3319 pub mod R {}
3320 /// Write-only values (empty)
3321 pub mod W {}
3322 /// Read-write values (empty)
3323 pub mod RW {}
3324 }
3325
3326 /// IO port G clocks enable during Sleep and Stop modes
3327 pub mod GPIOGSMEN {
3328 /// Offset (6 bits)
3329 pub const offset: u32 = 6;
3330 /// Mask (1 bit: 1 << 6)
3331 pub const mask: u32 = 1 << offset;
3332 /// Read-only values (empty)
3333 pub mod R {}
3334 /// Write-only values (empty)
3335 pub mod W {}
3336 /// Read-write values (empty)
3337 pub mod RW {}
3338 }
3339
3340 /// ADC clocks enable during Sleep and Stop modes
3341 pub mod ADC12SMEN {
3342 /// Offset (13 bits)
3343 pub const offset: u32 = 13;
3344 /// Mask (1 bit: 1 << 13)
3345 pub const mask: u32 = 1 << offset;
3346 /// Read-only values (empty)
3347 pub mod R {}
3348 /// Write-only values (empty)
3349 pub mod W {}
3350 /// Read-write values (empty)
3351 pub mod RW {}
3352 }
3353
3354 /// DCMI clock enable during Sleep and Stop modes
3355 pub mod ADC345SMEN {
3356 /// Offset (14 bits)
3357 pub const offset: u32 = 14;
3358 /// Mask (1 bit: 1 << 14)
3359 pub const mask: u32 = 1 << offset;
3360 /// Read-only values (empty)
3361 pub mod R {}
3362 /// Write-only values (empty)
3363 pub mod W {}
3364 /// Read-write values (empty)
3365 pub mod RW {}
3366 }
3367
3368 /// AES accelerator clocks enable during Sleep and Stop modes
3369 pub mod DAC1SMEN {
3370 /// Offset (16 bits)
3371 pub const offset: u32 = 16;
3372 /// Mask (1 bit: 1 << 16)
3373 pub const mask: u32 = 1 << offset;
3374 /// Read-only values (empty)
3375 pub mod R {}
3376 /// Write-only values (empty)
3377 pub mod W {}
3378 /// Read-write values (empty)
3379 pub mod RW {}
3380 }
3381
3382 /// HASH clock enable during Sleep and Stop modes
3383 pub mod DAC2SMEN {
3384 /// Offset (17 bits)
3385 pub const offset: u32 = 17;
3386 /// Mask (1 bit: 1 << 17)
3387 pub const mask: u32 = 1 << offset;
3388 /// Read-only values (empty)
3389 pub mod R {}
3390 /// Write-only values (empty)
3391 pub mod W {}
3392 /// Read-write values (empty)
3393 pub mod RW {}
3394 }
3395
3396 /// DAC3 clock enable during sleep mode
3397 pub mod DAC3SMEN {
3398 /// Offset (18 bits)
3399 pub const offset: u32 = 18;
3400 /// Mask (1 bit: 1 << 18)
3401 pub const mask: u32 = 1 << offset;
3402 /// Read-only values (empty)
3403 pub mod R {}
3404 /// Write-only values (empty)
3405 pub mod W {}
3406 /// Read-write values (empty)
3407 pub mod RW {}
3408 }
3409
3410 /// DAC4 clock enable during sleep mode
3411 pub mod DAC4SMEN {
3412 /// Offset (19 bits)
3413 pub const offset: u32 = 19;
3414 /// Mask (1 bit: 1 << 19)
3415 pub const mask: u32 = 1 << offset;
3416 /// Read-only values (empty)
3417 pub mod R {}
3418 /// Write-only values (empty)
3419 pub mod W {}
3420 /// Read-write values (empty)
3421 pub mod RW {}
3422 }
3423
3424 /// Cryptography clock enable during sleep mode
3425 pub mod AESMEN {
3426 /// Offset (24 bits)
3427 pub const offset: u32 = 24;
3428 /// Mask (1 bit: 1 << 24)
3429 pub const mask: u32 = 1 << offset;
3430 /// Read-only values (empty)
3431 pub mod R {}
3432 /// Write-only values (empty)
3433 pub mod W {}
3434 /// Read-write values (empty)
3435 pub mod RW {}
3436 }
3437
3438 /// Random Number Generator clock enable during sleep mode
3439 pub mod RNGSMEN {
3440 /// Offset (26 bits)
3441 pub const offset: u32 = 26;
3442 /// Mask (1 bit: 1 << 26)
3443 pub const mask: u32 = 1 << offset;
3444 /// Read-only values (empty)
3445 pub mod R {}
3446 /// Write-only values (empty)
3447 pub mod W {}
3448 /// Read-write values (empty)
3449 pub mod RW {}
3450 }
3451
3452 /// CCM SRAM interface clocks enable during Sleep and Stop modes
3453 pub mod CCMSRAMSMEN {
3454 /// Offset (9 bits)
3455 pub const offset: u32 = 9;
3456 /// Mask (1 bit: 1 << 9)
3457 pub const mask: u32 = 1 << offset;
3458 /// Read-only values (empty)
3459 pub mod R {}
3460 /// Write-only values (empty)
3461 pub mod W {}
3462 /// Read-write values (empty)
3463 pub mod RW {}
3464 }
3465
3466 /// SRAM2 interface clocks enable during Sleep and Stop modes
3467 pub mod SRAM2SMEN {
3468 /// Offset (10 bits)
3469 pub const offset: u32 = 10;
3470 /// Mask (1 bit: 1 << 10)
3471 pub const mask: u32 = 1 << offset;
3472 /// Read-only values (empty)
3473 pub mod R {}
3474 /// Write-only values (empty)
3475 pub mod W {}
3476 /// Read-write values (empty)
3477 pub mod RW {}
3478 }
3479}
3480
3481/// AHB3 peripheral clocks enable in Sleep and Stop modes register
3482pub mod AHB3SMENR {
3483
3484 /// Flexible memory controller clocks enable during Sleep and Stop modes
3485 pub mod FMCSMEN {
3486 /// Offset (0 bits)
3487 pub const offset: u32 = 0;
3488 /// Mask (1 bit: 1 << 0)
3489 pub const mask: u32 = 1 << offset;
3490 /// Read-only values (empty)
3491 pub mod R {}
3492 /// Write-only values (empty)
3493 pub mod W {}
3494 /// Read-write values (empty)
3495 pub mod RW {}
3496 }
3497
3498 /// QUADSPI memory interface clock enable during Sleep and Stop modes
3499 pub mod QSPISMEN {
3500 /// Offset (8 bits)
3501 pub const offset: u32 = 8;
3502 /// Mask (1 bit: 1 << 8)
3503 pub const mask: u32 = 1 << offset;
3504 /// Read-only values (empty)
3505 pub mod R {}
3506 /// Write-only values (empty)
3507 pub mod W {}
3508 /// Read-write values (empty)
3509 pub mod RW {}
3510 }
3511}
3512
3513/// APB1SMENR1
3514pub mod APB1SMENR1 {
3515
3516 /// TIM2 timer clocks enable during Sleep and Stop modes
3517 pub mod TIM2SMEN {
3518 /// Offset (0 bits)
3519 pub const offset: u32 = 0;
3520 /// Mask (1 bit: 1 << 0)
3521 pub const mask: u32 = 1 << offset;
3522 /// Read-only values (empty)
3523 pub mod R {}
3524 /// Write-only values (empty)
3525 pub mod W {}
3526 /// Read-write values (empty)
3527 pub mod RW {}
3528 }
3529
3530 /// TIM3 timer clocks enable during Sleep and Stop modes
3531 pub mod TIM3SMEN {
3532 /// Offset (1 bits)
3533 pub const offset: u32 = 1;
3534 /// Mask (1 bit: 1 << 1)
3535 pub const mask: u32 = 1 << offset;
3536 /// Read-only values (empty)
3537 pub mod R {}
3538 /// Write-only values (empty)
3539 pub mod W {}
3540 /// Read-write values (empty)
3541 pub mod RW {}
3542 }
3543
3544 /// TIM4 timer clocks enable during Sleep and Stop modes
3545 pub mod TIM4SMEN {
3546 /// Offset (2 bits)
3547 pub const offset: u32 = 2;
3548 /// Mask (1 bit: 1 << 2)
3549 pub const mask: u32 = 1 << offset;
3550 /// Read-only values (empty)
3551 pub mod R {}
3552 /// Write-only values (empty)
3553 pub mod W {}
3554 /// Read-write values (empty)
3555 pub mod RW {}
3556 }
3557
3558 /// TIM5 timer clocks enable during Sleep and Stop modes
3559 pub mod TIM5SMEN {
3560 /// Offset (3 bits)
3561 pub const offset: u32 = 3;
3562 /// Mask (1 bit: 1 << 3)
3563 pub const mask: u32 = 1 << offset;
3564 /// Read-only values (empty)
3565 pub mod R {}
3566 /// Write-only values (empty)
3567 pub mod W {}
3568 /// Read-write values (empty)
3569 pub mod RW {}
3570 }
3571
3572 /// TIM6 timer clocks enable during Sleep and Stop modes
3573 pub mod TIM6SMEN {
3574 /// Offset (4 bits)
3575 pub const offset: u32 = 4;
3576 /// Mask (1 bit: 1 << 4)
3577 pub const mask: u32 = 1 << offset;
3578 /// Read-only values (empty)
3579 pub mod R {}
3580 /// Write-only values (empty)
3581 pub mod W {}
3582 /// Read-write values (empty)
3583 pub mod RW {}
3584 }
3585
3586 /// TIM7 timer clocks enable during Sleep and Stop modes
3587 pub mod TIM7SMEN {
3588 /// Offset (5 bits)
3589 pub const offset: u32 = 5;
3590 /// Mask (1 bit: 1 << 5)
3591 pub const mask: u32 = 1 << offset;
3592 /// Read-only values (empty)
3593 pub mod R {}
3594 /// Write-only values (empty)
3595 pub mod W {}
3596 /// Read-write values (empty)
3597 pub mod RW {}
3598 }
3599
3600 /// CRS clock enable during sleep mode
3601 pub mod CRSSMEN {
3602 /// Offset (8 bits)
3603 pub const offset: u32 = 8;
3604 /// Mask (1 bit: 1 << 8)
3605 pub const mask: u32 = 1 << offset;
3606 /// Read-only values (empty)
3607 pub mod R {}
3608 /// Write-only values (empty)
3609 pub mod W {}
3610 /// Read-write values (empty)
3611 pub mod RW {}
3612 }
3613
3614 /// RTC APB clock enable during Sleep and Stop modes
3615 pub mod RTCAPBSMEN {
3616 /// Offset (10 bits)
3617 pub const offset: u32 = 10;
3618 /// Mask (1 bit: 1 << 10)
3619 pub const mask: u32 = 1 << offset;
3620 /// Read-only values (empty)
3621 pub mod R {}
3622 /// Write-only values (empty)
3623 pub mod W {}
3624 /// Read-write values (empty)
3625 pub mod RW {}
3626 }
3627
3628 /// Window watchdog clocks enable during Sleep and Stop modes
3629 pub mod WWDGSMEN {
3630 /// Offset (11 bits)
3631 pub const offset: u32 = 11;
3632 /// Mask (1 bit: 1 << 11)
3633 pub const mask: u32 = 1 << offset;
3634 /// Read-only values (empty)
3635 pub mod R {}
3636 /// Write-only values (empty)
3637 pub mod W {}
3638 /// Read-write values (empty)
3639 pub mod RW {}
3640 }
3641
3642 /// SPI2 clocks enable during Sleep and Stop modes
3643 pub mod SPI2SMEN {
3644 /// Offset (14 bits)
3645 pub const offset: u32 = 14;
3646 /// Mask (1 bit: 1 << 14)
3647 pub const mask: u32 = 1 << offset;
3648 /// Read-only values (empty)
3649 pub mod R {}
3650 /// Write-only values (empty)
3651 pub mod W {}
3652 /// Read-write values (empty)
3653 pub mod RW {}
3654 }
3655
3656 /// SPI3 clocks enable during Sleep and Stop modes
3657 pub mod SP3SMEN {
3658 /// Offset (15 bits)
3659 pub const offset: u32 = 15;
3660 /// Mask (1 bit: 1 << 15)
3661 pub const mask: u32 = 1 << offset;
3662 /// Read-only values (empty)
3663 pub mod R {}
3664 /// Write-only values (empty)
3665 pub mod W {}
3666 /// Read-write values (empty)
3667 pub mod RW {}
3668 }
3669
3670 /// USART2 clocks enable during Sleep and Stop modes
3671 pub mod USART2SMEN {
3672 /// Offset (17 bits)
3673 pub const offset: u32 = 17;
3674 /// Mask (1 bit: 1 << 17)
3675 pub const mask: u32 = 1 << offset;
3676 /// Read-only values (empty)
3677 pub mod R {}
3678 /// Write-only values (empty)
3679 pub mod W {}
3680 /// Read-write values (empty)
3681 pub mod RW {}
3682 }
3683
3684 /// USART3 clocks enable during Sleep and Stop modes
3685 pub mod USART3SMEN {
3686 /// Offset (18 bits)
3687 pub const offset: u32 = 18;
3688 /// Mask (1 bit: 1 << 18)
3689 pub const mask: u32 = 1 << offset;
3690 /// Read-only values (empty)
3691 pub mod R {}
3692 /// Write-only values (empty)
3693 pub mod W {}
3694 /// Read-write values (empty)
3695 pub mod RW {}
3696 }
3697
3698 /// UART4 clocks enable during Sleep and Stop modes
3699 pub mod UART4SMEN {
3700 /// Offset (19 bits)
3701 pub const offset: u32 = 19;
3702 /// Mask (1 bit: 1 << 19)
3703 pub const mask: u32 = 1 << offset;
3704 /// Read-only values (empty)
3705 pub mod R {}
3706 /// Write-only values (empty)
3707 pub mod W {}
3708 /// Read-write values (empty)
3709 pub mod RW {}
3710 }
3711
3712 /// UART5 clocks enable during Sleep and Stop modes
3713 pub mod UART5SMEN {
3714 /// Offset (20 bits)
3715 pub const offset: u32 = 20;
3716 /// Mask (1 bit: 1 << 20)
3717 pub const mask: u32 = 1 << offset;
3718 /// Read-only values (empty)
3719 pub mod R {}
3720 /// Write-only values (empty)
3721 pub mod W {}
3722 /// Read-write values (empty)
3723 pub mod RW {}
3724 }
3725
3726 /// I2C1 clocks enable during Sleep and Stop modes
3727 pub mod I2C1SMEN {
3728 /// Offset (21 bits)
3729 pub const offset: u32 = 21;
3730 /// Mask (1 bit: 1 << 21)
3731 pub const mask: u32 = 1 << offset;
3732 /// Read-only values (empty)
3733 pub mod R {}
3734 /// Write-only values (empty)
3735 pub mod W {}
3736 /// Read-write values (empty)
3737 pub mod RW {}
3738 }
3739
3740 /// I2C2 clocks enable during Sleep and Stop modes
3741 pub mod I2C2SMEN {
3742 /// Offset (22 bits)
3743 pub const offset: u32 = 22;
3744 /// Mask (1 bit: 1 << 22)
3745 pub const mask: u32 = 1 << offset;
3746 /// Read-only values (empty)
3747 pub mod R {}
3748 /// Write-only values (empty)
3749 pub mod W {}
3750 /// Read-write values (empty)
3751 pub mod RW {}
3752 }
3753
3754 /// FDCAN clock enable during sleep mode
3755 pub mod FDCANSMEN {
3756 /// Offset (25 bits)
3757 pub const offset: u32 = 25;
3758 /// Mask (1 bit: 1 << 25)
3759 pub const mask: u32 = 1 << offset;
3760 /// Read-only values (empty)
3761 pub mod R {}
3762 /// Write-only values (empty)
3763 pub mod W {}
3764 /// Read-write values (empty)
3765 pub mod RW {}
3766 }
3767
3768 /// Power interface clocks enable during Sleep and Stop modes
3769 pub mod PWRSMEN {
3770 /// Offset (28 bits)
3771 pub const offset: u32 = 28;
3772 /// Mask (1 bit: 1 << 28)
3773 pub const mask: u32 = 1 << offset;
3774 /// Read-only values (empty)
3775 pub mod R {}
3776 /// Write-only values (empty)
3777 pub mod W {}
3778 /// Read-write values (empty)
3779 pub mod RW {}
3780 }
3781
3782 /// Low Power Timer1 clock enable during sleep mode
3783 pub mod LPTIM1SMEN {
3784 /// Offset (31 bits)
3785 pub const offset: u32 = 31;
3786 /// Mask (1 bit: 1 << 31)
3787 pub const mask: u32 = 1 << offset;
3788 /// Read-only values (empty)
3789 pub mod R {}
3790 /// Write-only values (empty)
3791 pub mod W {}
3792 /// Read-write values (empty)
3793 pub mod RW {}
3794 }
3795
3796 /// USB device clocks enable during Sleep and Stop modes
3797 pub mod USBSMEN {
3798 /// Offset (23 bits)
3799 pub const offset: u32 = 23;
3800 /// Mask (1 bit: 1 << 23)
3801 pub const mask: u32 = 1 << offset;
3802 /// Read-only values (empty)
3803 pub mod R {}
3804 /// Write-only values (empty)
3805 pub mod W {}
3806 /// Read-write values (empty)
3807 pub mod RW {}
3808 }
3809
3810 /// I2C3 clocks enable during Sleep and Stop modes
3811 pub mod I2C3SMEN {
3812 /// Offset (30 bits)
3813 pub const offset: u32 = 30;
3814 /// Mask (1 bit: 1 << 30)
3815 pub const mask: u32 = 1 << offset;
3816 /// Read-only values (empty)
3817 pub mod R {}
3818 /// Write-only values (empty)
3819 pub mod W {}
3820 /// Read-write values (empty)
3821 pub mod RW {}
3822 }
3823}
3824
3825/// APB1 peripheral clocks enable in Sleep and Stop modes register 2
3826pub mod APB1SMENR2 {
3827
3828 /// Low power UART 1 clocks enable during Sleep and Stop modes
3829 pub mod LPUART1SMEN {
3830 /// Offset (0 bits)
3831 pub const offset: u32 = 0;
3832 /// Mask (1 bit: 1 << 0)
3833 pub const mask: u32 = 1 << offset;
3834 /// Read-only values (empty)
3835 pub mod R {}
3836 /// Write-only values (empty)
3837 pub mod W {}
3838 /// Read-write values (empty)
3839 pub mod RW {}
3840 }
3841
3842 /// I2C4 clocks enable during Sleep and Stop modes
3843 pub mod I2C4SMEN {
3844 /// Offset (1 bits)
3845 pub const offset: u32 = 1;
3846 /// Mask (1 bit: 1 << 1)
3847 pub const mask: u32 = 1 << offset;
3848 /// Read-only values (empty)
3849 pub mod R {}
3850 /// Write-only values (empty)
3851 pub mod W {}
3852 /// Read-write values (empty)
3853 pub mod RW {}
3854 }
3855
3856 /// UCPD1 clocks enable during Sleep and Stop modes
3857 pub mod UCPD1SMEN {
3858 /// Offset (8 bits)
3859 pub const offset: u32 = 8;
3860 /// Mask (1 bit: 1 << 8)
3861 pub const mask: u32 = 1 << offset;
3862 /// Read-only values (empty)
3863 pub mod R {}
3864 /// Write-only values (empty)
3865 pub mod W {}
3866 /// Read-write values (empty)
3867 pub mod RW {}
3868 }
3869}
3870
3871/// APB2SMENR
3872pub mod APB2SMENR {
3873
3874 /// SYSCFG clocks enable during Sleep and Stop modes
3875 pub mod SYSCFGSMEN {
3876 /// Offset (0 bits)
3877 pub const offset: u32 = 0;
3878 /// Mask (1 bit: 1 << 0)
3879 pub const mask: u32 = 1 << offset;
3880 /// Read-only values (empty)
3881 pub mod R {}
3882 /// Write-only values (empty)
3883 pub mod W {}
3884 /// Read-write values (empty)
3885 pub mod RW {}
3886 }
3887
3888 /// TIM1 timer clocks enable during Sleep and Stop modes
3889 pub mod TIM1SMEN {
3890 /// Offset (11 bits)
3891 pub const offset: u32 = 11;
3892 /// Mask (1 bit: 1 << 11)
3893 pub const mask: u32 = 1 << offset;
3894 /// Read-only values (empty)
3895 pub mod R {}
3896 /// Write-only values (empty)
3897 pub mod W {}
3898 /// Read-write values (empty)
3899 pub mod RW {}
3900 }
3901
3902 /// SPI1 clocks enable during Sleep and Stop modes
3903 pub mod SPI1SMEN {
3904 /// Offset (12 bits)
3905 pub const offset: u32 = 12;
3906 /// Mask (1 bit: 1 << 12)
3907 pub const mask: u32 = 1 << offset;
3908 /// Read-only values (empty)
3909 pub mod R {}
3910 /// Write-only values (empty)
3911 pub mod W {}
3912 /// Read-write values (empty)
3913 pub mod RW {}
3914 }
3915
3916 /// TIM8 timer clocks enable during Sleep and Stop modes
3917 pub mod TIM8SMEN {
3918 /// Offset (13 bits)
3919 pub const offset: u32 = 13;
3920 /// Mask (1 bit: 1 << 13)
3921 pub const mask: u32 = 1 << offset;
3922 /// Read-only values (empty)
3923 pub mod R {}
3924 /// Write-only values (empty)
3925 pub mod W {}
3926 /// Read-write values (empty)
3927 pub mod RW {}
3928 }
3929
3930 /// USART1clocks enable during Sleep and Stop modes
3931 pub mod USART1SMEN {
3932 /// Offset (14 bits)
3933 pub const offset: u32 = 14;
3934 /// Mask (1 bit: 1 << 14)
3935 pub const mask: u32 = 1 << offset;
3936 /// Read-only values (empty)
3937 pub mod R {}
3938 /// Write-only values (empty)
3939 pub mod W {}
3940 /// Read-write values (empty)
3941 pub mod RW {}
3942 }
3943
3944 /// SPI4 timer clocks enable during Sleep and Stop modes
3945 pub mod SPI4SMEN {
3946 /// Offset (15 bits)
3947 pub const offset: u32 = 15;
3948 /// Mask (1 bit: 1 << 15)
3949 pub const mask: u32 = 1 << offset;
3950 /// Read-only values (empty)
3951 pub mod R {}
3952 /// Write-only values (empty)
3953 pub mod W {}
3954 /// Read-write values (empty)
3955 pub mod RW {}
3956 }
3957
3958 /// TIM15 timer clocks enable during Sleep and Stop modes
3959 pub mod TIM15SMEN {
3960 /// Offset (16 bits)
3961 pub const offset: u32 = 16;
3962 /// Mask (1 bit: 1 << 16)
3963 pub const mask: u32 = 1 << offset;
3964 /// Read-only values (empty)
3965 pub mod R {}
3966 /// Write-only values (empty)
3967 pub mod W {}
3968 /// Read-write values (empty)
3969 pub mod RW {}
3970 }
3971
3972 /// TIM16 timer clocks enable during Sleep and Stop modes
3973 pub mod TIM16SMEN {
3974 /// Offset (17 bits)
3975 pub const offset: u32 = 17;
3976 /// Mask (1 bit: 1 << 17)
3977 pub const mask: u32 = 1 << offset;
3978 /// Read-only values (empty)
3979 pub mod R {}
3980 /// Write-only values (empty)
3981 pub mod W {}
3982 /// Read-write values (empty)
3983 pub mod RW {}
3984 }
3985
3986 /// TIM17 timer clocks enable during Sleep and Stop modes
3987 pub mod TIM17SMEN {
3988 /// Offset (18 bits)
3989 pub const offset: u32 = 18;
3990 /// Mask (1 bit: 1 << 18)
3991 pub const mask: u32 = 1 << offset;
3992 /// Read-only values (empty)
3993 pub mod R {}
3994 /// Write-only values (empty)
3995 pub mod W {}
3996 /// Read-write values (empty)
3997 pub mod RW {}
3998 }
3999
4000 /// Timer 20clock enable during sleep mode
4001 pub mod TIM20SMEN {
4002 /// Offset (20 bits)
4003 pub const offset: u32 = 20;
4004 /// Mask (1 bit: 1 << 20)
4005 pub const mask: u32 = 1 << offset;
4006 /// Read-only values (empty)
4007 pub mod R {}
4008 /// Write-only values (empty)
4009 pub mod W {}
4010 /// Read-write values (empty)
4011 pub mod RW {}
4012 }
4013
4014 /// SAI1 clock enable during sleep mode
4015 pub mod SAI1SMEN {
4016 /// Offset (21 bits)
4017 pub const offset: u32 = 21;
4018 /// Mask (1 bit: 1 << 21)
4019 pub const mask: u32 = 1 << offset;
4020 /// Read-only values (empty)
4021 pub mod R {}
4022 /// Write-only values (empty)
4023 pub mod W {}
4024 /// Read-write values (empty)
4025 pub mod RW {}
4026 }
4027
4028 /// HRTIMER clock enable during sleep mode
4029 pub mod HRTIM1SMEN {
4030 /// Offset (26 bits)
4031 pub const offset: u32 = 26;
4032 /// Mask (1 bit: 1 << 26)
4033 pub const mask: u32 = 1 << offset;
4034 /// Read-only values (empty)
4035 pub mod R {}
4036 /// Write-only values (empty)
4037 pub mod W {}
4038 /// Read-write values (empty)
4039 pub mod RW {}
4040 }
4041}
4042
4043/// CCIPR
4044pub mod CCIPR {
4045
4046 /// ADC3/4/5 clock source selection
4047 pub mod ADC345SEL {
4048 /// Offset (30 bits)
4049 pub const offset: u32 = 30;
4050 /// Mask (2 bits: 0b11 << 30)
4051 pub const mask: u32 = 0b11 << offset;
4052 /// Read-only values (empty)
4053 pub mod R {}
4054 /// Write-only values (empty)
4055 pub mod W {}
4056 /// Read-write values
4057 pub mod RW {
4058
4059 /// 0b00: No clock selected for ADC
4060 pub const None: u32 = 0b00;
4061
4062 /// 0b01: PLL 'P' clock selected for ADC
4063 pub const PLLP: u32 = 0b01;
4064
4065 /// 0b10: System clock selected for ADC
4066 pub const System: u32 = 0b10;
4067 }
4068 }
4069
4070 /// ADCs clock source selection
4071 pub mod ADC12SEL {
4072 /// Offset (28 bits)
4073 pub const offset: u32 = 28;
4074 /// Mask (2 bits: 0b11 << 28)
4075 pub const mask: u32 = 0b11 << offset;
4076 /// Read-only values (empty)
4077 pub mod R {}
4078 /// Write-only values (empty)
4079 pub mod W {}
4080 pub use super::ADC345SEL::RW;
4081 }
4082
4083 /// 48 MHz clock source selection
4084 pub mod CLK48SEL {
4085 /// Offset (26 bits)
4086 pub const offset: u32 = 26;
4087 /// Mask (2 bits: 0b11 << 26)
4088 pub const mask: u32 = 0b11 << offset;
4089 /// Read-only values (empty)
4090 pub mod R {}
4091 /// Write-only values (empty)
4092 pub mod W {}
4093 /// Read-write values
4094 pub mod RW {
4095
4096 /// 0b00: HSI48 clock selected as 48MHz clock
4097 pub const HSI48: u32 = 0b00;
4098
4099 /// 0b10: PLL 'Q' (PLL48M1CLK) clock selected as 48MHz clock
4100 pub const PLLQ: u32 = 0b10;
4101 }
4102 }
4103
4104 /// SAI2 clock source selection
4105 pub mod FDCANSEL {
4106 /// Offset (24 bits)
4107 pub const offset: u32 = 24;
4108 /// Mask (2 bits: 0b11 << 24)
4109 pub const mask: u32 = 0b11 << offset;
4110 /// Read-only values (empty)
4111 pub mod R {}
4112 /// Write-only values (empty)
4113 pub mod W {}
4114 /// Read-write values
4115 pub mod RW {
4116
4117 /// 0b00: HSE clock selected as FDCAN clock
4118 pub const HSE: u32 = 0b00;
4119
4120 /// 0b01: PLL 'Q' clock selected as FDCAN clock
4121 pub const PLLQ: u32 = 0b01;
4122
4123 /// 0b10: PCLK clock selected as FDCAN clock
4124 pub const PCLK: u32 = 0b10;
4125 }
4126 }
4127
4128 /// SAI1 clock source selection
4129 pub mod I2S23SEL {
4130 /// Offset (22 bits)
4131 pub const offset: u32 = 22;
4132 /// Mask (2 bits: 0b11 << 22)
4133 pub const mask: u32 = 0b11 << offset;
4134 /// Read-only values (empty)
4135 pub mod R {}
4136 /// Write-only values (empty)
4137 pub mod W {}
4138 /// Read-write values
4139 pub mod RW {
4140
4141 /// 0b00: System clock selected as I2S23 clock
4142 pub const System: u32 = 0b00;
4143
4144 /// 0b01: PLL 'Q' clock selected as I2S23 clock
4145 pub const PLLQ: u32 = 0b01;
4146
4147 /// 0b10: Clock provided on I2S_CKIN pin is selected as I2S23 clock
4148 pub const I2S_CKIN: u32 = 0b10;
4149
4150 /// 0b11: HSI16 clock selected as I2S23 clock
4151 pub const HSI16: u32 = 0b11;
4152 }
4153 }
4154
4155 /// Low power timer 2 clock source selection
4156 pub mod SAI1SEL {
4157 /// Offset (20 bits)
4158 pub const offset: u32 = 20;
4159 /// Mask (2 bits: 0b11 << 20)
4160 pub const mask: u32 = 0b11 << offset;
4161 /// Read-only values (empty)
4162 pub mod R {}
4163 /// Write-only values (empty)
4164 pub mod W {}
4165 /// Read-write values
4166 pub mod RW {
4167
4168 /// 0b00: System clock selected as SAI clock
4169 pub const System: u32 = 0b00;
4170
4171 /// 0b01: PLL 'Q' clock selected as SAI clock
4172 pub const PLLQ: u32 = 0b01;
4173
4174 /// 0b10: Clock provided on I2S_CKIN pin is selected as SAI clock
4175 pub const I2S_CKIN: u32 = 0b10;
4176
4177 /// 0b11: HSI16 clock selected as SAI clock
4178 pub const HSI16: u32 = 0b11;
4179 }
4180 }
4181
4182 /// Low power timer 1 clock source selection
4183 pub mod LPTIM1SEL {
4184 /// Offset (18 bits)
4185 pub const offset: u32 = 18;
4186 /// Mask (2 bits: 0b11 << 18)
4187 pub const mask: u32 = 0b11 << offset;
4188 /// Read-only values (empty)
4189 pub mod R {}
4190 /// Write-only values (empty)
4191 pub mod W {}
4192 /// Read-write values
4193 pub mod RW {
4194
4195 /// 0b00: PCLK clock selected as LPTIM1 clock
4196 pub const PCLK: u32 = 0b00;
4197
4198 /// 0b01: LSI clock selected as LPTIM1 clock
4199 pub const LSI: u32 = 0b01;
4200
4201 /// 0b10: HSI16 clock selected as LPTIM1 clock
4202 pub const HSI16: u32 = 0b10;
4203
4204 /// 0b11: LSE clock selected as LPTIM1 clock
4205 pub const LSE: u32 = 0b11;
4206 }
4207 }
4208
4209 /// I2C3 clock source selection
4210 pub mod I2C3SEL {
4211 /// Offset (16 bits)
4212 pub const offset: u32 = 16;
4213 /// Mask (2 bits: 0b11 << 16)
4214 pub const mask: u32 = 0b11 << offset;
4215 /// Read-only values (empty)
4216 pub mod R {}
4217 /// Write-only values (empty)
4218 pub mod W {}
4219 /// Read-write values
4220 pub mod RW {
4221
4222 /// 0b00: PCLK clock selected as I2C clock
4223 pub const PCLK: u32 = 0b00;
4224
4225 /// 0b01: System clock (SYSCLK) selected as I2C clock
4226 pub const System: u32 = 0b01;
4227
4228 /// 0b10: HSI16 clock selected as I2C clock
4229 pub const HSI16: u32 = 0b10;
4230 }
4231 }
4232
4233 /// I2C2 clock source selection
4234 pub mod I2C2SEL {
4235 /// Offset (14 bits)
4236 pub const offset: u32 = 14;
4237 /// Mask (2 bits: 0b11 << 14)
4238 pub const mask: u32 = 0b11 << offset;
4239 /// Read-only values (empty)
4240 pub mod R {}
4241 /// Write-only values (empty)
4242 pub mod W {}
4243 pub use super::I2C3SEL::RW;
4244 }
4245
4246 /// I2C1 clock source selection
4247 pub mod I2C1SEL {
4248 /// Offset (12 bits)
4249 pub const offset: u32 = 12;
4250 /// Mask (2 bits: 0b11 << 12)
4251 pub const mask: u32 = 0b11 << offset;
4252 /// Read-only values (empty)
4253 pub mod R {}
4254 /// Write-only values (empty)
4255 pub mod W {}
4256 pub use super::I2C3SEL::RW;
4257 }
4258
4259 /// LPUART1 clock source selection
4260 pub mod LPUART1SEL {
4261 /// Offset (10 bits)
4262 pub const offset: u32 = 10;
4263 /// Mask (2 bits: 0b11 << 10)
4264 pub const mask: u32 = 0b11 << offset;
4265 /// Read-only values (empty)
4266 pub mod R {}
4267 /// Write-only values (empty)
4268 pub mod W {}
4269 /// Read-write values
4270 pub mod RW {
4271
4272 /// 0b00: PCLK clock selected as UART clock
4273 pub const PCLK: u32 = 0b00;
4274
4275 /// 0b01: System clock (SYSCLK) selected as UART clock
4276 pub const System: u32 = 0b01;
4277
4278 /// 0b10: HSI16 clock selected as UART clock
4279 pub const HSI16: u32 = 0b10;
4280
4281 /// 0b11: LSE clock selected as UART clock
4282 pub const LSE: u32 = 0b11;
4283 }
4284 }
4285
4286 /// UART5 clock source selection
4287 pub mod UART5SEL {
4288 /// Offset (8 bits)
4289 pub const offset: u32 = 8;
4290 /// Mask (2 bits: 0b11 << 8)
4291 pub const mask: u32 = 0b11 << offset;
4292 /// Read-only values (empty)
4293 pub mod R {}
4294 /// Write-only values (empty)
4295 pub mod W {}
4296 pub use super::LPUART1SEL::RW;
4297 }
4298
4299 /// UART4 clock source selection
4300 pub mod UART4SEL {
4301 /// Offset (6 bits)
4302 pub const offset: u32 = 6;
4303 /// Mask (2 bits: 0b11 << 6)
4304 pub const mask: u32 = 0b11 << offset;
4305 /// Read-only values (empty)
4306 pub mod R {}
4307 /// Write-only values (empty)
4308 pub mod W {}
4309 pub use super::LPUART1SEL::RW;
4310 }
4311
4312 /// USART3 clock source selection
4313 pub mod USART3SEL {
4314 /// Offset (4 bits)
4315 pub const offset: u32 = 4;
4316 /// Mask (2 bits: 0b11 << 4)
4317 pub const mask: u32 = 0b11 << offset;
4318 /// Read-only values (empty)
4319 pub mod R {}
4320 /// Write-only values (empty)
4321 pub mod W {}
4322 /// Read-write values (empty)
4323 pub mod RW {}
4324 }
4325
4326 /// USART2 clock source selection
4327 pub mod USART2SEL {
4328 /// Offset (2 bits)
4329 pub const offset: u32 = 2;
4330 /// Mask (2 bits: 0b11 << 2)
4331 pub const mask: u32 = 0b11 << offset;
4332 /// Read-only values (empty)
4333 pub mod R {}
4334 /// Write-only values (empty)
4335 pub mod W {}
4336 /// Read-write values (empty)
4337 pub mod RW {}
4338 }
4339
4340 /// USART1 clock source selection
4341 pub mod USART1SEL {
4342 /// Offset (0 bits)
4343 pub const offset: u32 = 0;
4344 /// Mask (2 bits: 0b11 << 0)
4345 pub const mask: u32 = 0b11 << offset;
4346 /// Read-only values (empty)
4347 pub mod R {}
4348 /// Write-only values (empty)
4349 pub mod W {}
4350 /// Read-write values (empty)
4351 pub mod RW {}
4352 }
4353}
4354
4355/// BDCR
4356pub mod BDCR {
4357
4358 /// Low speed clock output selection
4359 pub mod LSCOSEL {
4360 /// Offset (25 bits)
4361 pub const offset: u32 = 25;
4362 /// Mask (1 bit: 1 << 25)
4363 pub const mask: u32 = 1 << offset;
4364 /// Read-only values (empty)
4365 pub mod R {}
4366 /// Write-only values (empty)
4367 pub mod W {}
4368 /// Read-write values
4369 pub mod RW {
4370
4371 /// 0b0: LSI clock selected
4372 pub const LSI: u32 = 0b0;
4373
4374 /// 0b1: LSE clock selected
4375 pub const LSE: u32 = 0b1;
4376 }
4377 }
4378
4379 /// Low speed clock output enable
4380 pub mod LSCOEN {
4381 /// Offset (24 bits)
4382 pub const offset: u32 = 24;
4383 /// Mask (1 bit: 1 << 24)
4384 pub const mask: u32 = 1 << offset;
4385 /// Read-only values (empty)
4386 pub mod R {}
4387 /// Write-only values (empty)
4388 pub mod W {}
4389 /// Read-write values
4390 pub mod RW {
4391
4392 /// 0b0: LSCO disabled
4393 pub const Disabled: u32 = 0b0;
4394
4395 /// 0b1: LSCO enabled
4396 pub const Enabled: u32 = 0b1;
4397 }
4398 }
4399
4400 /// RTC domain software reset
4401 pub mod BDRST {
4402 /// Offset (16 bits)
4403 pub const offset: u32 = 16;
4404 /// Mask (1 bit: 1 << 16)
4405 pub const mask: u32 = 1 << offset;
4406 /// Read-only values (empty)
4407 pub mod R {}
4408 /// Write-only values (empty)
4409 pub mod W {}
4410 /// Read-write values
4411 pub mod RW {
4412
4413 /// 0b0: Reset not activated
4414 pub const Disabled: u32 = 0b0;
4415
4416 /// 0b1: Reset the entire RTC domain
4417 pub const Enabled: u32 = 0b1;
4418 }
4419 }
4420
4421 /// RTC clock enable
4422 pub mod RTCEN {
4423 /// Offset (15 bits)
4424 pub const offset: u32 = 15;
4425 /// Mask (1 bit: 1 << 15)
4426 pub const mask: u32 = 1 << offset;
4427 /// Read-only values (empty)
4428 pub mod R {}
4429 /// Write-only values (empty)
4430 pub mod W {}
4431 /// Read-write values
4432 pub mod RW {
4433
4434 /// 0b0: RTC clock disabled
4435 pub const Disabled: u32 = 0b0;
4436
4437 /// 0b1: RTC clock enabled
4438 pub const Enabled: u32 = 0b1;
4439 }
4440 }
4441
4442 /// RTC clock source selection
4443 pub mod RTCSEL {
4444 /// Offset (8 bits)
4445 pub const offset: u32 = 8;
4446 /// Mask (2 bits: 0b11 << 8)
4447 pub const mask: u32 = 0b11 << offset;
4448 /// Read-only values (empty)
4449 pub mod R {}
4450 /// Write-only values (empty)
4451 pub mod W {}
4452 /// Read-write values
4453 pub mod RW {
4454
4455 /// 0b00: No clock
4456 pub const NoClock: u32 = 0b00;
4457
4458 /// 0b01: LSE oscillator clock used as RTC clock
4459 pub const LSE: u32 = 0b01;
4460
4461 /// 0b10: LSI oscillator clock used as RTC clock
4462 pub const LSI: u32 = 0b10;
4463
4464 /// 0b11: HSE oscillator clock divided by a prescaler used as RTC clock
4465 pub const HSE: u32 = 0b11;
4466 }
4467 }
4468
4469 /// LSECSSD
4470 pub mod LSECSSD {
4471 /// Offset (6 bits)
4472 pub const offset: u32 = 6;
4473 /// Mask (1 bit: 1 << 6)
4474 pub const mask: u32 = 1 << offset;
4475 /// Read-only values
4476 pub mod R {
4477
4478 /// 0b0: No failure detected on LSE (32 kHz oscillator)
4479 pub const NoFailure: u32 = 0b0;
4480
4481 /// 0b1: Failure detected on LSE (32 kHz oscillator)
4482 pub const Failure: u32 = 0b1;
4483 }
4484 /// Write-only values (empty)
4485 pub mod W {}
4486 /// Read-write values (empty)
4487 pub mod RW {}
4488 }
4489
4490 /// LSECSSON
4491 pub mod LSECSSON {
4492 /// Offset (5 bits)
4493 pub const offset: u32 = 5;
4494 /// Mask (1 bit: 1 << 5)
4495 pub const mask: u32 = 1 << offset;
4496 /// Read-only values (empty)
4497 pub mod R {}
4498 /// Write-only values (empty)
4499 pub mod W {}
4500 /// Read-write values
4501 pub mod RW {
4502
4503 /// 0b0: CSS on LSE (32 kHz external oscillator) OFF
4504 pub const Off: u32 = 0b0;
4505
4506 /// 0b1: CSS on LSE (32 kHz external oscillator) ON
4507 pub const On: u32 = 0b1;
4508 }
4509 }
4510
4511 /// SE oscillator drive capability
4512 pub mod LSEDRV {
4513 /// Offset (3 bits)
4514 pub const offset: u32 = 3;
4515 /// Mask (2 bits: 0b11 << 3)
4516 pub const mask: u32 = 0b11 << offset;
4517 /// Read-only values (empty)
4518 pub mod R {}
4519 /// Write-only values (empty)
4520 pub mod W {}
4521 /// Read-write values
4522 pub mod RW {
4523
4524 /// 0b00: 'Xtal mode' lower driving capability
4525 pub const Lower: u32 = 0b00;
4526
4527 /// 0b01: 'Xtal mode' medium low driving capability
4528 pub const MediumLow: u32 = 0b01;
4529
4530 /// 0b10: 'Xtal mode' medium high driving capability
4531 pub const MediumHigh: u32 = 0b10;
4532
4533 /// 0b11: 'Xtal mode' higher driving capability
4534 pub const Higher: u32 = 0b11;
4535 }
4536 }
4537
4538 /// LSE oscillator bypass
4539 pub mod LSEBYP {
4540 /// Offset (2 bits)
4541 pub const offset: u32 = 2;
4542 /// Mask (1 bit: 1 << 2)
4543 pub const mask: u32 = 1 << offset;
4544 /// Read-only values (empty)
4545 pub mod R {}
4546 /// Write-only values (empty)
4547 pub mod W {}
4548 /// Read-write values
4549 pub mod RW {
4550
4551 /// 0b0: LSE crystal oscillator not bypassed
4552 pub const NotBypassed: u32 = 0b0;
4553
4554 /// 0b1: LSE crystal oscillator bypassed with external clock
4555 pub const Bypassed: u32 = 0b1;
4556 }
4557 }
4558
4559 /// LSE oscillator ready
4560 pub mod LSERDY {
4561 /// Offset (1 bits)
4562 pub const offset: u32 = 1;
4563 /// Mask (1 bit: 1 << 1)
4564 pub const mask: u32 = 1 << offset;
4565 /// Read-only values
4566 pub mod R {
4567
4568 /// 0b0: LSE clock not ready
4569 pub const NotReady: u32 = 0b0;
4570
4571 /// 0b1: LSE clock ready
4572 pub const Ready: u32 = 0b1;
4573 }
4574 /// Write-only values (empty)
4575 pub mod W {}
4576 /// Read-write values (empty)
4577 pub mod RW {}
4578 }
4579
4580 /// LSE oscillator enable
4581 pub mod LSEON {
4582 /// Offset (0 bits)
4583 pub const offset: u32 = 0;
4584 /// Mask (1 bit: 1 << 0)
4585 pub const mask: u32 = 1 << offset;
4586 /// Read-only values (empty)
4587 pub mod R {}
4588 /// Write-only values (empty)
4589 pub mod W {}
4590 /// Read-write values
4591 pub mod RW {
4592
4593 /// 0b0: LSE only enabled when requested by a peripheral or system function
4594 pub const Off: u32 = 0b0;
4595
4596 /// 0b1: LSE enabled always generated by RCC
4597 pub const On: u32 = 0b1;
4598 }
4599 }
4600}
4601
4602/// CSR
4603pub mod CSR {
4604
4605 /// Low-power reset flag
4606 pub mod LPWRSTF {
4607 /// Offset (31 bits)
4608 pub const offset: u32 = 31;
4609 /// Mask (1 bit: 1 << 31)
4610 pub const mask: u32 = 1 << offset;
4611 /// Read-only values
4612 pub mod R {
4613
4614 /// 0b0: No reset has occured
4615 pub const NoReset: u32 = 0b0;
4616
4617 /// 0b1: A reset has occured
4618 pub const Reset: u32 = 0b1;
4619 }
4620 /// Write-only values (empty)
4621 pub mod W {}
4622 /// Read-write values (empty)
4623 pub mod RW {}
4624 }
4625
4626 /// Window watchdog reset flag
4627 pub mod WWDGRSTF {
4628 /// Offset (30 bits)
4629 pub const offset: u32 = 30;
4630 /// Mask (1 bit: 1 << 30)
4631 pub const mask: u32 = 1 << offset;
4632 pub use super::LPWRSTF::R;
4633 /// Write-only values (empty)
4634 pub mod W {}
4635 /// Read-write values (empty)
4636 pub mod RW {}
4637 }
4638
4639 /// Independent window watchdog reset flag
4640 pub mod IWDGRSTF {
4641 /// Offset (29 bits)
4642 pub const offset: u32 = 29;
4643 /// Mask (1 bit: 1 << 29)
4644 pub const mask: u32 = 1 << offset;
4645 pub use super::LPWRSTF::R;
4646 /// Write-only values (empty)
4647 pub mod W {}
4648 /// Read-write values (empty)
4649 pub mod RW {}
4650 }
4651
4652 /// Software reset flag
4653 pub mod SFTRSTF {
4654 /// Offset (28 bits)
4655 pub const offset: u32 = 28;
4656 /// Mask (1 bit: 1 << 28)
4657 pub const mask: u32 = 1 << offset;
4658 pub use super::LPWRSTF::R;
4659 /// Write-only values (empty)
4660 pub mod W {}
4661 /// Read-write values (empty)
4662 pub mod RW {}
4663 }
4664
4665 /// BOR flag
4666 pub mod BORRSTF {
4667 /// Offset (27 bits)
4668 pub const offset: u32 = 27;
4669 /// Mask (1 bit: 1 << 27)
4670 pub const mask: u32 = 1 << offset;
4671 pub use super::LPWRSTF::R;
4672 /// Write-only values (empty)
4673 pub mod W {}
4674 /// Read-write values (empty)
4675 pub mod RW {}
4676 }
4677
4678 /// Pad reset flag
4679 pub mod PINRSTF {
4680 /// Offset (26 bits)
4681 pub const offset: u32 = 26;
4682 /// Mask (1 bit: 1 << 26)
4683 pub const mask: u32 = 1 << offset;
4684 pub use super::LPWRSTF::R;
4685 /// Write-only values (empty)
4686 pub mod W {}
4687 /// Read-write values (empty)
4688 pub mod RW {}
4689 }
4690
4691 /// Option byte loader reset flag
4692 pub mod OBLRSTF {
4693 /// Offset (25 bits)
4694 pub const offset: u32 = 25;
4695 /// Mask (1 bit: 1 << 25)
4696 pub const mask: u32 = 1 << offset;
4697 pub use super::LPWRSTF::R;
4698 /// Write-only values (empty)
4699 pub mod W {}
4700 /// Read-write values (empty)
4701 pub mod RW {}
4702 }
4703
4704 /// Remove reset flag
4705 pub mod RMVF {
4706 /// Offset (23 bits)
4707 pub const offset: u32 = 23;
4708 /// Mask (1 bit: 1 << 23)
4709 pub const mask: u32 = 1 << offset;
4710 /// Read-only values (empty)
4711 pub mod R {}
4712 /// Write-only values
4713 pub mod W {
4714
4715 /// 0b1: Clears the reset flag
4716 pub const Clear: u32 = 0b1;
4717 }
4718 /// Read-write values (empty)
4719 pub mod RW {}
4720 }
4721
4722 /// LSI oscillator ready
4723 pub mod LSIRDY {
4724 /// Offset (1 bits)
4725 pub const offset: u32 = 1;
4726 /// Mask (1 bit: 1 << 1)
4727 pub const mask: u32 = 1 << offset;
4728 /// Read-only values
4729 pub mod R {
4730
4731 /// 0b0: LSI oscillator not ready
4732 pub const NotReady: u32 = 0b0;
4733
4734 /// 0b1: LSI oscillator ready
4735 pub const Ready: u32 = 0b1;
4736 }
4737 /// Write-only values (empty)
4738 pub mod W {}
4739 /// Read-write values (empty)
4740 pub mod RW {}
4741 }
4742
4743 /// LSI oscillator enable
4744 pub mod LSION {
4745 /// Offset (0 bits)
4746 pub const offset: u32 = 0;
4747 /// Mask (1 bit: 1 << 0)
4748 pub const mask: u32 = 1 << offset;
4749 /// Read-only values (empty)
4750 pub mod R {}
4751 /// Write-only values (empty)
4752 pub mod W {}
4753 /// Read-write values
4754 pub mod RW {
4755
4756 /// 0b0: LSI oscillator Off
4757 pub const Off: u32 = 0b0;
4758
4759 /// 0b1: LSI oscillator On
4760 pub const On: u32 = 0b1;
4761 }
4762 }
4763}
4764
4765/// Clock recovery RC register
4766pub mod CRRCR {
4767
4768 /// HSI48 clock enable
4769 pub mod HSI48ON {
4770 /// Offset (0 bits)
4771 pub const offset: u32 = 0;
4772 /// Mask (1 bit: 1 << 0)
4773 pub const mask: u32 = 1 << offset;
4774 /// Read-only values (empty)
4775 pub mod R {}
4776 /// Write-only values (empty)
4777 pub mod W {}
4778 /// Read-write values (empty)
4779 pub mod RW {}
4780 }
4781
4782 /// HSI48 clock ready flag
4783 pub mod HSI48RDY {
4784 /// Offset (1 bits)
4785 pub const offset: u32 = 1;
4786 /// Mask (1 bit: 1 << 1)
4787 pub const mask: u32 = 1 << offset;
4788 /// Read-only values (empty)
4789 pub mod R {}
4790 /// Write-only values (empty)
4791 pub mod W {}
4792 /// Read-write values (empty)
4793 pub mod RW {}
4794 }
4795
4796 /// HSI48 clock calibration
4797 pub mod HSI48CAL {
4798 /// Offset (7 bits)
4799 pub const offset: u32 = 7;
4800 /// Mask (9 bits: 0x1ff << 7)
4801 pub const mask: u32 = 0x1ff << offset;
4802 /// Read-only values (empty)
4803 pub mod R {}
4804 /// Write-only values (empty)
4805 pub mod W {}
4806 /// Read-write values (empty)
4807 pub mod RW {}
4808 }
4809}
4810
4811/// Peripherals independent clock configuration register
4812pub mod CCIPR2 {
4813
4814 /// I2C4 clock source selection
4815 pub mod I2C4SEL {
4816 /// Offset (0 bits)
4817 pub const offset: u32 = 0;
4818 /// Mask (2 bits: 0b11 << 0)
4819 pub const mask: u32 = 0b11 << offset;
4820 /// Read-only values (empty)
4821 pub mod R {}
4822 /// Write-only values (empty)
4823 pub mod W {}
4824 /// Read-write values
4825 pub mod RW {
4826
4827 /// 0b00: PCLK clock selected as I2C clock
4828 pub const PCLK: u32 = 0b00;
4829
4830 /// 0b01: System clock (SYSCLK) selected as I2C clock
4831 pub const System: u32 = 0b01;
4832
4833 /// 0b10: HSI16 clock selected as I2C clock
4834 pub const HSI16: u32 = 0b10;
4835 }
4836 }
4837
4838 /// Octospi clock source selection
4839 pub mod QSPISEL {
4840 /// Offset (20 bits)
4841 pub const offset: u32 = 20;
4842 /// Mask (2 bits: 0b11 << 20)
4843 pub const mask: u32 = 0b11 << offset;
4844 /// Read-only values (empty)
4845 pub mod R {}
4846 /// Write-only values (empty)
4847 pub mod W {}
4848 /// Read-write values
4849 pub mod RW {
4850
4851 /// 0b00: System clock selected as QUADSPI kernel clock
4852 pub const System: u32 = 0b00;
4853
4854 /// 0b01: HSI16 clock selected as QUADSPI kernel clock
4855 pub const HSI16: u32 = 0b01;
4856
4857 /// 0b10: PLL 'Q' clock selected as QUADSPI kernel clock
4858 pub const PLLQ: u32 = 0b10;
4859 }
4860 }
4861}
4862#[repr(C)]
4863pub struct RegisterBlock {
4864 /// Clock control register
4865 pub CR: RWRegister<u32>,
4866
4867 /// Internal clock sources calibration register
4868 pub ICSCR: RWRegister<u32>,
4869
4870 /// Clock configuration register
4871 pub CFGR: RWRegister<u32>,
4872
4873 /// PLL configuration register
4874 pub PLLCFGR: RWRegister<u32>,
4875
4876 _reserved1: [u8; 8],
4877
4878 /// Clock interrupt enable register
4879 pub CIER: RWRegister<u32>,
4880
4881 /// Clock interrupt flag register
4882 pub CIFR: RORegister<u32>,
4883
4884 /// Clock interrupt clear register
4885 pub CICR: WORegister<u32>,
4886
4887 _reserved2: [u8; 4],
4888
4889 /// AHB1 peripheral reset register
4890 pub AHB1RSTR: RWRegister<u32>,
4891
4892 /// AHB2 peripheral reset register
4893 pub AHB2RSTR: RWRegister<u32>,
4894
4895 /// AHB3 peripheral reset register
4896 pub AHB3RSTR: RWRegister<u32>,
4897
4898 _reserved3: [u8; 4],
4899
4900 /// APB1 peripheral reset register 1
4901 pub APB1RSTR1: RWRegister<u32>,
4902
4903 /// APB1 peripheral reset register 2
4904 pub APB1RSTR2: RWRegister<u32>,
4905
4906 /// APB2 peripheral reset register
4907 pub APB2RSTR: RWRegister<u32>,
4908
4909 _reserved4: [u8; 4],
4910
4911 /// AHB1 peripheral clock enable register
4912 pub AHB1ENR: RWRegister<u32>,
4913
4914 /// AHB2 peripheral clock enable register
4915 pub AHB2ENR: RWRegister<u32>,
4916
4917 /// AHB3 peripheral clock enable register
4918 pub AHB3ENR: RWRegister<u32>,
4919
4920 _reserved5: [u8; 4],
4921
4922 /// APB1ENR1
4923 pub APB1ENR1: RWRegister<u32>,
4924
4925 /// APB1 peripheral clock enable register 2
4926 pub APB1ENR2: RWRegister<u32>,
4927
4928 /// APB2ENR
4929 pub APB2ENR: RWRegister<u32>,
4930
4931 _reserved6: [u8; 4],
4932
4933 /// AHB1 peripheral clocks enable in Sleep and Stop modes register
4934 pub AHB1SMENR: RWRegister<u32>,
4935
4936 /// AHB2 peripheral clocks enable in Sleep and Stop modes register
4937 pub AHB2SMENR: RWRegister<u32>,
4938
4939 /// AHB3 peripheral clocks enable in Sleep and Stop modes register
4940 pub AHB3SMENR: RWRegister<u32>,
4941
4942 _reserved7: [u8; 4],
4943
4944 /// APB1SMENR1
4945 pub APB1SMENR1: RWRegister<u32>,
4946
4947 /// APB1 peripheral clocks enable in Sleep and Stop modes register 2
4948 pub APB1SMENR2: RWRegister<u32>,
4949
4950 /// APB2SMENR
4951 pub APB2SMENR: RWRegister<u32>,
4952
4953 _reserved8: [u8; 4],
4954
4955 /// CCIPR
4956 pub CCIPR: RWRegister<u32>,
4957
4958 _reserved9: [u8; 4],
4959
4960 /// BDCR
4961 pub BDCR: RWRegister<u32>,
4962
4963 /// CSR
4964 pub CSR: RWRegister<u32>,
4965
4966 /// Clock recovery RC register
4967 pub CRRCR: RWRegister<u32>,
4968
4969 /// Peripherals independent clock configuration register
4970 pub CCIPR2: RWRegister<u32>,
4971}
4972pub struct ResetValues {
4973 pub CR: u32,
4974 pub ICSCR: u32,
4975 pub CFGR: u32,
4976 pub PLLCFGR: u32,
4977 pub CIER: u32,
4978 pub CIFR: u32,
4979 pub CICR: u32,
4980 pub AHB1RSTR: u32,
4981 pub AHB2RSTR: u32,
4982 pub AHB3RSTR: u32,
4983 pub APB1RSTR1: u32,
4984 pub APB1RSTR2: u32,
4985 pub APB2RSTR: u32,
4986 pub AHB1ENR: u32,
4987 pub AHB2ENR: u32,
4988 pub AHB3ENR: u32,
4989 pub APB1ENR1: u32,
4990 pub APB1ENR2: u32,
4991 pub APB2ENR: u32,
4992 pub AHB1SMENR: u32,
4993 pub AHB2SMENR: u32,
4994 pub AHB3SMENR: u32,
4995 pub APB1SMENR1: u32,
4996 pub APB1SMENR2: u32,
4997 pub APB2SMENR: u32,
4998 pub CCIPR: u32,
4999 pub BDCR: u32,
5000 pub CSR: u32,
5001 pub CRRCR: u32,
5002 pub CCIPR2: u32,
5003}
5004#[cfg(not(feature = "nosync"))]
5005pub struct Instance {
5006 pub(crate) addr: u32,
5007 pub(crate) _marker: PhantomData<*const RegisterBlock>,
5008}
5009#[cfg(not(feature = "nosync"))]
5010impl ::core::ops::Deref for Instance {
5011 type Target = RegisterBlock;
5012 #[inline(always)]
5013 fn deref(&self) -> &RegisterBlock {
5014 unsafe { &*(self.addr as *const _) }
5015 }
5016}
5017#[cfg(feature = "rtic")]
5018unsafe impl Send for Instance {}