stm32ral/stm32g0/stm32g07x/gpio.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General-purpose I/Os
4
5use crate::{RORegister, RWRegister, WORegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// GPIO port mode register
10pub mod MODER {
11
12 /// Port x configuration bits (y = 0..15)
13 pub mod MODER15 {
14 /// Offset (30 bits)
15 pub const offset: u32 = 30;
16 /// Mask (2 bits: 0b11 << 30)
17 pub const mask: u32 = 0b11 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25
26 /// Port x configuration bits (y = 0..15)
27 pub mod MODER14 {
28 /// Offset (28 bits)
29 pub const offset: u32 = 28;
30 /// Mask (2 bits: 0b11 << 28)
31 pub const mask: u32 = 0b11 << offset;
32 /// Read-only values (empty)
33 pub mod R {}
34 /// Write-only values (empty)
35 pub mod W {}
36 /// Read-write values (empty)
37 pub mod RW {}
38 }
39
40 /// Port x configuration bits (y = 0..15)
41 pub mod MODER13 {
42 /// Offset (26 bits)
43 pub const offset: u32 = 26;
44 /// Mask (2 bits: 0b11 << 26)
45 pub const mask: u32 = 0b11 << offset;
46 /// Read-only values (empty)
47 pub mod R {}
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53
54 /// Port x configuration bits (y = 0..15)
55 pub mod MODER12 {
56 /// Offset (24 bits)
57 pub const offset: u32 = 24;
58 /// Mask (2 bits: 0b11 << 24)
59 pub const mask: u32 = 0b11 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// Port x configuration bits (y = 0..15)
69 pub mod MODER11 {
70 /// Offset (22 bits)
71 pub const offset: u32 = 22;
72 /// Mask (2 bits: 0b11 << 22)
73 pub const mask: u32 = 0b11 << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// Port x configuration bits (y = 0..15)
83 pub mod MODER10 {
84 /// Offset (20 bits)
85 pub const offset: u32 = 20;
86 /// Mask (2 bits: 0b11 << 20)
87 pub const mask: u32 = 0b11 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 /// Read-write values (empty)
93 pub mod RW {}
94 }
95
96 /// Port x configuration bits (y = 0..15)
97 pub mod MODER9 {
98 /// Offset (18 bits)
99 pub const offset: u32 = 18;
100 /// Mask (2 bits: 0b11 << 18)
101 pub const mask: u32 = 0b11 << offset;
102 /// Read-only values (empty)
103 pub mod R {}
104 /// Write-only values (empty)
105 pub mod W {}
106 /// Read-write values (empty)
107 pub mod RW {}
108 }
109
110 /// Port x configuration bits (y = 0..15)
111 pub mod MODER8 {
112 /// Offset (16 bits)
113 pub const offset: u32 = 16;
114 /// Mask (2 bits: 0b11 << 16)
115 pub const mask: u32 = 0b11 << offset;
116 /// Read-only values (empty)
117 pub mod R {}
118 /// Write-only values (empty)
119 pub mod W {}
120 /// Read-write values (empty)
121 pub mod RW {}
122 }
123
124 /// Port x configuration bits (y = 0..15)
125 pub mod MODER7 {
126 /// Offset (14 bits)
127 pub const offset: u32 = 14;
128 /// Mask (2 bits: 0b11 << 14)
129 pub const mask: u32 = 0b11 << offset;
130 /// Read-only values (empty)
131 pub mod R {}
132 /// Write-only values (empty)
133 pub mod W {}
134 /// Read-write values (empty)
135 pub mod RW {}
136 }
137
138 /// Port x configuration bits (y = 0..15)
139 pub mod MODER6 {
140 /// Offset (12 bits)
141 pub const offset: u32 = 12;
142 /// Mask (2 bits: 0b11 << 12)
143 pub const mask: u32 = 0b11 << offset;
144 /// Read-only values (empty)
145 pub mod R {}
146 /// Write-only values (empty)
147 pub mod W {}
148 /// Read-write values (empty)
149 pub mod RW {}
150 }
151
152 /// Port x configuration bits (y = 0..15)
153 pub mod MODER5 {
154 /// Offset (10 bits)
155 pub const offset: u32 = 10;
156 /// Mask (2 bits: 0b11 << 10)
157 pub const mask: u32 = 0b11 << offset;
158 /// Read-only values (empty)
159 pub mod R {}
160 /// Write-only values (empty)
161 pub mod W {}
162 /// Read-write values (empty)
163 pub mod RW {}
164 }
165
166 /// Port x configuration bits (y = 0..15)
167 pub mod MODER4 {
168 /// Offset (8 bits)
169 pub const offset: u32 = 8;
170 /// Mask (2 bits: 0b11 << 8)
171 pub const mask: u32 = 0b11 << offset;
172 /// Read-only values (empty)
173 pub mod R {}
174 /// Write-only values (empty)
175 pub mod W {}
176 /// Read-write values (empty)
177 pub mod RW {}
178 }
179
180 /// Port x configuration bits (y = 0..15)
181 pub mod MODER3 {
182 /// Offset (6 bits)
183 pub const offset: u32 = 6;
184 /// Mask (2 bits: 0b11 << 6)
185 pub const mask: u32 = 0b11 << offset;
186 /// Read-only values (empty)
187 pub mod R {}
188 /// Write-only values (empty)
189 pub mod W {}
190 /// Read-write values (empty)
191 pub mod RW {}
192 }
193
194 /// Port x configuration bits (y = 0..15)
195 pub mod MODER2 {
196 /// Offset (4 bits)
197 pub const offset: u32 = 4;
198 /// Mask (2 bits: 0b11 << 4)
199 pub const mask: u32 = 0b11 << offset;
200 /// Read-only values (empty)
201 pub mod R {}
202 /// Write-only values (empty)
203 pub mod W {}
204 /// Read-write values (empty)
205 pub mod RW {}
206 }
207
208 /// Port x configuration bits (y = 0..15)
209 pub mod MODER1 {
210 /// Offset (2 bits)
211 pub const offset: u32 = 2;
212 /// Mask (2 bits: 0b11 << 2)
213 pub const mask: u32 = 0b11 << offset;
214 /// Read-only values (empty)
215 pub mod R {}
216 /// Write-only values (empty)
217 pub mod W {}
218 /// Read-write values (empty)
219 pub mod RW {}
220 }
221
222 /// Port x configuration bits (y = 0..15)
223 pub mod MODER0 {
224 /// Offset (0 bits)
225 pub const offset: u32 = 0;
226 /// Mask (2 bits: 0b11 << 0)
227 pub const mask: u32 = 0b11 << offset;
228 /// Read-only values (empty)
229 pub mod R {}
230 /// Write-only values (empty)
231 pub mod W {}
232 /// Read-write values (empty)
233 pub mod RW {}
234 }
235}
236
237/// GPIO port output type register
238pub mod OTYPER {
239
240 /// Port x configuration bits (y = 0..15)
241 pub mod OT15 {
242 /// Offset (15 bits)
243 pub const offset: u32 = 15;
244 /// Mask (1 bit: 1 << 15)
245 pub const mask: u32 = 1 << offset;
246 /// Read-only values (empty)
247 pub mod R {}
248 /// Write-only values (empty)
249 pub mod W {}
250 /// Read-write values (empty)
251 pub mod RW {}
252 }
253
254 /// Port x configuration bits (y = 0..15)
255 pub mod OT14 {
256 /// Offset (14 bits)
257 pub const offset: u32 = 14;
258 /// Mask (1 bit: 1 << 14)
259 pub const mask: u32 = 1 << offset;
260 /// Read-only values (empty)
261 pub mod R {}
262 /// Write-only values (empty)
263 pub mod W {}
264 /// Read-write values (empty)
265 pub mod RW {}
266 }
267
268 /// Port x configuration bits (y = 0..15)
269 pub mod OT13 {
270 /// Offset (13 bits)
271 pub const offset: u32 = 13;
272 /// Mask (1 bit: 1 << 13)
273 pub const mask: u32 = 1 << offset;
274 /// Read-only values (empty)
275 pub mod R {}
276 /// Write-only values (empty)
277 pub mod W {}
278 /// Read-write values (empty)
279 pub mod RW {}
280 }
281
282 /// Port x configuration bits (y = 0..15)
283 pub mod OT12 {
284 /// Offset (12 bits)
285 pub const offset: u32 = 12;
286 /// Mask (1 bit: 1 << 12)
287 pub const mask: u32 = 1 << offset;
288 /// Read-only values (empty)
289 pub mod R {}
290 /// Write-only values (empty)
291 pub mod W {}
292 /// Read-write values (empty)
293 pub mod RW {}
294 }
295
296 /// Port x configuration bits (y = 0..15)
297 pub mod OT11 {
298 /// Offset (11 bits)
299 pub const offset: u32 = 11;
300 /// Mask (1 bit: 1 << 11)
301 pub const mask: u32 = 1 << offset;
302 /// Read-only values (empty)
303 pub mod R {}
304 /// Write-only values (empty)
305 pub mod W {}
306 /// Read-write values (empty)
307 pub mod RW {}
308 }
309
310 /// Port x configuration bits (y = 0..15)
311 pub mod OT10 {
312 /// Offset (10 bits)
313 pub const offset: u32 = 10;
314 /// Mask (1 bit: 1 << 10)
315 pub const mask: u32 = 1 << offset;
316 /// Read-only values (empty)
317 pub mod R {}
318 /// Write-only values (empty)
319 pub mod W {}
320 /// Read-write values (empty)
321 pub mod RW {}
322 }
323
324 /// Port x configuration bits (y = 0..15)
325 pub mod OT9 {
326 /// Offset (9 bits)
327 pub const offset: u32 = 9;
328 /// Mask (1 bit: 1 << 9)
329 pub const mask: u32 = 1 << offset;
330 /// Read-only values (empty)
331 pub mod R {}
332 /// Write-only values (empty)
333 pub mod W {}
334 /// Read-write values (empty)
335 pub mod RW {}
336 }
337
338 /// Port x configuration bits (y = 0..15)
339 pub mod OT8 {
340 /// Offset (8 bits)
341 pub const offset: u32 = 8;
342 /// Mask (1 bit: 1 << 8)
343 pub const mask: u32 = 1 << offset;
344 /// Read-only values (empty)
345 pub mod R {}
346 /// Write-only values (empty)
347 pub mod W {}
348 /// Read-write values (empty)
349 pub mod RW {}
350 }
351
352 /// Port x configuration bits (y = 0..15)
353 pub mod OT7 {
354 /// Offset (7 bits)
355 pub const offset: u32 = 7;
356 /// Mask (1 bit: 1 << 7)
357 pub const mask: u32 = 1 << offset;
358 /// Read-only values (empty)
359 pub mod R {}
360 /// Write-only values (empty)
361 pub mod W {}
362 /// Read-write values (empty)
363 pub mod RW {}
364 }
365
366 /// Port x configuration bits (y = 0..15)
367 pub mod OT6 {
368 /// Offset (6 bits)
369 pub const offset: u32 = 6;
370 /// Mask (1 bit: 1 << 6)
371 pub const mask: u32 = 1 << offset;
372 /// Read-only values (empty)
373 pub mod R {}
374 /// Write-only values (empty)
375 pub mod W {}
376 /// Read-write values (empty)
377 pub mod RW {}
378 }
379
380 /// Port x configuration bits (y = 0..15)
381 pub mod OT5 {
382 /// Offset (5 bits)
383 pub const offset: u32 = 5;
384 /// Mask (1 bit: 1 << 5)
385 pub const mask: u32 = 1 << offset;
386 /// Read-only values (empty)
387 pub mod R {}
388 /// Write-only values (empty)
389 pub mod W {}
390 /// Read-write values (empty)
391 pub mod RW {}
392 }
393
394 /// Port x configuration bits (y = 0..15)
395 pub mod OT4 {
396 /// Offset (4 bits)
397 pub const offset: u32 = 4;
398 /// Mask (1 bit: 1 << 4)
399 pub const mask: u32 = 1 << offset;
400 /// Read-only values (empty)
401 pub mod R {}
402 /// Write-only values (empty)
403 pub mod W {}
404 /// Read-write values (empty)
405 pub mod RW {}
406 }
407
408 /// Port x configuration bits (y = 0..15)
409 pub mod OT3 {
410 /// Offset (3 bits)
411 pub const offset: u32 = 3;
412 /// Mask (1 bit: 1 << 3)
413 pub const mask: u32 = 1 << offset;
414 /// Read-only values (empty)
415 pub mod R {}
416 /// Write-only values (empty)
417 pub mod W {}
418 /// Read-write values (empty)
419 pub mod RW {}
420 }
421
422 /// Port x configuration bits (y = 0..15)
423 pub mod OT2 {
424 /// Offset (2 bits)
425 pub const offset: u32 = 2;
426 /// Mask (1 bit: 1 << 2)
427 pub const mask: u32 = 1 << offset;
428 /// Read-only values (empty)
429 pub mod R {}
430 /// Write-only values (empty)
431 pub mod W {}
432 /// Read-write values (empty)
433 pub mod RW {}
434 }
435
436 /// Port x configuration bits (y = 0..15)
437 pub mod OT1 {
438 /// Offset (1 bits)
439 pub const offset: u32 = 1;
440 /// Mask (1 bit: 1 << 1)
441 pub const mask: u32 = 1 << offset;
442 /// Read-only values (empty)
443 pub mod R {}
444 /// Write-only values (empty)
445 pub mod W {}
446 /// Read-write values (empty)
447 pub mod RW {}
448 }
449
450 /// Port x configuration bits (y = 0..15)
451 pub mod OT0 {
452 /// Offset (0 bits)
453 pub const offset: u32 = 0;
454 /// Mask (1 bit: 1 << 0)
455 pub const mask: u32 = 1 << offset;
456 /// Read-only values (empty)
457 pub mod R {}
458 /// Write-only values (empty)
459 pub mod W {}
460 /// Read-write values (empty)
461 pub mod RW {}
462 }
463}
464
465/// GPIO port output speed register
466pub mod OSPEEDR {
467
468 /// Port x configuration bits (y = 0..15)
469 pub mod OSPEEDR15 {
470 /// Offset (30 bits)
471 pub const offset: u32 = 30;
472 /// Mask (2 bits: 0b11 << 30)
473 pub const mask: u32 = 0b11 << offset;
474 /// Read-only values (empty)
475 pub mod R {}
476 /// Write-only values (empty)
477 pub mod W {}
478 /// Read-write values (empty)
479 pub mod RW {}
480 }
481
482 /// Port x configuration bits (y = 0..15)
483 pub mod OSPEEDR14 {
484 /// Offset (28 bits)
485 pub const offset: u32 = 28;
486 /// Mask (2 bits: 0b11 << 28)
487 pub const mask: u32 = 0b11 << offset;
488 /// Read-only values (empty)
489 pub mod R {}
490 /// Write-only values (empty)
491 pub mod W {}
492 /// Read-write values (empty)
493 pub mod RW {}
494 }
495
496 /// Port x configuration bits (y = 0..15)
497 pub mod OSPEEDR13 {
498 /// Offset (26 bits)
499 pub const offset: u32 = 26;
500 /// Mask (2 bits: 0b11 << 26)
501 pub const mask: u32 = 0b11 << offset;
502 /// Read-only values (empty)
503 pub mod R {}
504 /// Write-only values (empty)
505 pub mod W {}
506 /// Read-write values (empty)
507 pub mod RW {}
508 }
509
510 /// Port x configuration bits (y = 0..15)
511 pub mod OSPEEDR12 {
512 /// Offset (24 bits)
513 pub const offset: u32 = 24;
514 /// Mask (2 bits: 0b11 << 24)
515 pub const mask: u32 = 0b11 << offset;
516 /// Read-only values (empty)
517 pub mod R {}
518 /// Write-only values (empty)
519 pub mod W {}
520 /// Read-write values (empty)
521 pub mod RW {}
522 }
523
524 /// Port x configuration bits (y = 0..15)
525 pub mod OSPEEDR11 {
526 /// Offset (22 bits)
527 pub const offset: u32 = 22;
528 /// Mask (2 bits: 0b11 << 22)
529 pub const mask: u32 = 0b11 << offset;
530 /// Read-only values (empty)
531 pub mod R {}
532 /// Write-only values (empty)
533 pub mod W {}
534 /// Read-write values (empty)
535 pub mod RW {}
536 }
537
538 /// Port x configuration bits (y = 0..15)
539 pub mod OSPEEDR10 {
540 /// Offset (20 bits)
541 pub const offset: u32 = 20;
542 /// Mask (2 bits: 0b11 << 20)
543 pub const mask: u32 = 0b11 << offset;
544 /// Read-only values (empty)
545 pub mod R {}
546 /// Write-only values (empty)
547 pub mod W {}
548 /// Read-write values (empty)
549 pub mod RW {}
550 }
551
552 /// Port x configuration bits (y = 0..15)
553 pub mod OSPEEDR9 {
554 /// Offset (18 bits)
555 pub const offset: u32 = 18;
556 /// Mask (2 bits: 0b11 << 18)
557 pub const mask: u32 = 0b11 << offset;
558 /// Read-only values (empty)
559 pub mod R {}
560 /// Write-only values (empty)
561 pub mod W {}
562 /// Read-write values (empty)
563 pub mod RW {}
564 }
565
566 /// Port x configuration bits (y = 0..15)
567 pub mod OSPEEDR8 {
568 /// Offset (16 bits)
569 pub const offset: u32 = 16;
570 /// Mask (2 bits: 0b11 << 16)
571 pub const mask: u32 = 0b11 << offset;
572 /// Read-only values (empty)
573 pub mod R {}
574 /// Write-only values (empty)
575 pub mod W {}
576 /// Read-write values (empty)
577 pub mod RW {}
578 }
579
580 /// Port x configuration bits (y = 0..15)
581 pub mod OSPEEDR7 {
582 /// Offset (14 bits)
583 pub const offset: u32 = 14;
584 /// Mask (2 bits: 0b11 << 14)
585 pub const mask: u32 = 0b11 << offset;
586 /// Read-only values (empty)
587 pub mod R {}
588 /// Write-only values (empty)
589 pub mod W {}
590 /// Read-write values (empty)
591 pub mod RW {}
592 }
593
594 /// Port x configuration bits (y = 0..15)
595 pub mod OSPEEDR6 {
596 /// Offset (12 bits)
597 pub const offset: u32 = 12;
598 /// Mask (2 bits: 0b11 << 12)
599 pub const mask: u32 = 0b11 << offset;
600 /// Read-only values (empty)
601 pub mod R {}
602 /// Write-only values (empty)
603 pub mod W {}
604 /// Read-write values (empty)
605 pub mod RW {}
606 }
607
608 /// Port x configuration bits (y = 0..15)
609 pub mod OSPEEDR5 {
610 /// Offset (10 bits)
611 pub const offset: u32 = 10;
612 /// Mask (2 bits: 0b11 << 10)
613 pub const mask: u32 = 0b11 << offset;
614 /// Read-only values (empty)
615 pub mod R {}
616 /// Write-only values (empty)
617 pub mod W {}
618 /// Read-write values (empty)
619 pub mod RW {}
620 }
621
622 /// Port x configuration bits (y = 0..15)
623 pub mod OSPEEDR4 {
624 /// Offset (8 bits)
625 pub const offset: u32 = 8;
626 /// Mask (2 bits: 0b11 << 8)
627 pub const mask: u32 = 0b11 << offset;
628 /// Read-only values (empty)
629 pub mod R {}
630 /// Write-only values (empty)
631 pub mod W {}
632 /// Read-write values (empty)
633 pub mod RW {}
634 }
635
636 /// Port x configuration bits (y = 0..15)
637 pub mod OSPEEDR3 {
638 /// Offset (6 bits)
639 pub const offset: u32 = 6;
640 /// Mask (2 bits: 0b11 << 6)
641 pub const mask: u32 = 0b11 << offset;
642 /// Read-only values (empty)
643 pub mod R {}
644 /// Write-only values (empty)
645 pub mod W {}
646 /// Read-write values (empty)
647 pub mod RW {}
648 }
649
650 /// Port x configuration bits (y = 0..15)
651 pub mod OSPEEDR2 {
652 /// Offset (4 bits)
653 pub const offset: u32 = 4;
654 /// Mask (2 bits: 0b11 << 4)
655 pub const mask: u32 = 0b11 << offset;
656 /// Read-only values (empty)
657 pub mod R {}
658 /// Write-only values (empty)
659 pub mod W {}
660 /// Read-write values (empty)
661 pub mod RW {}
662 }
663
664 /// Port x configuration bits (y = 0..15)
665 pub mod OSPEEDR1 {
666 /// Offset (2 bits)
667 pub const offset: u32 = 2;
668 /// Mask (2 bits: 0b11 << 2)
669 pub const mask: u32 = 0b11 << offset;
670 /// Read-only values (empty)
671 pub mod R {}
672 /// Write-only values (empty)
673 pub mod W {}
674 /// Read-write values (empty)
675 pub mod RW {}
676 }
677
678 /// Port x configuration bits (y = 0..15)
679 pub mod OSPEEDR0 {
680 /// Offset (0 bits)
681 pub const offset: u32 = 0;
682 /// Mask (2 bits: 0b11 << 0)
683 pub const mask: u32 = 0b11 << offset;
684 /// Read-only values (empty)
685 pub mod R {}
686 /// Write-only values (empty)
687 pub mod W {}
688 /// Read-write values (empty)
689 pub mod RW {}
690 }
691}
692
693/// GPIO port pull-up/pull-down register
694pub mod PUPDR {
695
696 /// Port x configuration bits (y = 0..15)
697 pub mod PUPDR15 {
698 /// Offset (30 bits)
699 pub const offset: u32 = 30;
700 /// Mask (2 bits: 0b11 << 30)
701 pub const mask: u32 = 0b11 << offset;
702 /// Read-only values (empty)
703 pub mod R {}
704 /// Write-only values (empty)
705 pub mod W {}
706 /// Read-write values (empty)
707 pub mod RW {}
708 }
709
710 /// Port x configuration bits (y = 0..15)
711 pub mod PUPDR14 {
712 /// Offset (28 bits)
713 pub const offset: u32 = 28;
714 /// Mask (2 bits: 0b11 << 28)
715 pub const mask: u32 = 0b11 << offset;
716 /// Read-only values (empty)
717 pub mod R {}
718 /// Write-only values (empty)
719 pub mod W {}
720 /// Read-write values (empty)
721 pub mod RW {}
722 }
723
724 /// Port x configuration bits (y = 0..15)
725 pub mod PUPDR13 {
726 /// Offset (26 bits)
727 pub const offset: u32 = 26;
728 /// Mask (2 bits: 0b11 << 26)
729 pub const mask: u32 = 0b11 << offset;
730 /// Read-only values (empty)
731 pub mod R {}
732 /// Write-only values (empty)
733 pub mod W {}
734 /// Read-write values (empty)
735 pub mod RW {}
736 }
737
738 /// Port x configuration bits (y = 0..15)
739 pub mod PUPDR12 {
740 /// Offset (24 bits)
741 pub const offset: u32 = 24;
742 /// Mask (2 bits: 0b11 << 24)
743 pub const mask: u32 = 0b11 << offset;
744 /// Read-only values (empty)
745 pub mod R {}
746 /// Write-only values (empty)
747 pub mod W {}
748 /// Read-write values (empty)
749 pub mod RW {}
750 }
751
752 /// Port x configuration bits (y = 0..15)
753 pub mod PUPDR11 {
754 /// Offset (22 bits)
755 pub const offset: u32 = 22;
756 /// Mask (2 bits: 0b11 << 22)
757 pub const mask: u32 = 0b11 << offset;
758 /// Read-only values (empty)
759 pub mod R {}
760 /// Write-only values (empty)
761 pub mod W {}
762 /// Read-write values (empty)
763 pub mod RW {}
764 }
765
766 /// Port x configuration bits (y = 0..15)
767 pub mod PUPDR10 {
768 /// Offset (20 bits)
769 pub const offset: u32 = 20;
770 /// Mask (2 bits: 0b11 << 20)
771 pub const mask: u32 = 0b11 << offset;
772 /// Read-only values (empty)
773 pub mod R {}
774 /// Write-only values (empty)
775 pub mod W {}
776 /// Read-write values (empty)
777 pub mod RW {}
778 }
779
780 /// Port x configuration bits (y = 0..15)
781 pub mod PUPDR9 {
782 /// Offset (18 bits)
783 pub const offset: u32 = 18;
784 /// Mask (2 bits: 0b11 << 18)
785 pub const mask: u32 = 0b11 << offset;
786 /// Read-only values (empty)
787 pub mod R {}
788 /// Write-only values (empty)
789 pub mod W {}
790 /// Read-write values (empty)
791 pub mod RW {}
792 }
793
794 /// Port x configuration bits (y = 0..15)
795 pub mod PUPDR8 {
796 /// Offset (16 bits)
797 pub const offset: u32 = 16;
798 /// Mask (2 bits: 0b11 << 16)
799 pub const mask: u32 = 0b11 << offset;
800 /// Read-only values (empty)
801 pub mod R {}
802 /// Write-only values (empty)
803 pub mod W {}
804 /// Read-write values (empty)
805 pub mod RW {}
806 }
807
808 /// Port x configuration bits (y = 0..15)
809 pub mod PUPDR7 {
810 /// Offset (14 bits)
811 pub const offset: u32 = 14;
812 /// Mask (2 bits: 0b11 << 14)
813 pub const mask: u32 = 0b11 << offset;
814 /// Read-only values (empty)
815 pub mod R {}
816 /// Write-only values (empty)
817 pub mod W {}
818 /// Read-write values (empty)
819 pub mod RW {}
820 }
821
822 /// Port x configuration bits (y = 0..15)
823 pub mod PUPDR6 {
824 /// Offset (12 bits)
825 pub const offset: u32 = 12;
826 /// Mask (2 bits: 0b11 << 12)
827 pub const mask: u32 = 0b11 << offset;
828 /// Read-only values (empty)
829 pub mod R {}
830 /// Write-only values (empty)
831 pub mod W {}
832 /// Read-write values (empty)
833 pub mod RW {}
834 }
835
836 /// Port x configuration bits (y = 0..15)
837 pub mod PUPDR5 {
838 /// Offset (10 bits)
839 pub const offset: u32 = 10;
840 /// Mask (2 bits: 0b11 << 10)
841 pub const mask: u32 = 0b11 << offset;
842 /// Read-only values (empty)
843 pub mod R {}
844 /// Write-only values (empty)
845 pub mod W {}
846 /// Read-write values (empty)
847 pub mod RW {}
848 }
849
850 /// Port x configuration bits (y = 0..15)
851 pub mod PUPDR4 {
852 /// Offset (8 bits)
853 pub const offset: u32 = 8;
854 /// Mask (2 bits: 0b11 << 8)
855 pub const mask: u32 = 0b11 << offset;
856 /// Read-only values (empty)
857 pub mod R {}
858 /// Write-only values (empty)
859 pub mod W {}
860 /// Read-write values (empty)
861 pub mod RW {}
862 }
863
864 /// Port x configuration bits (y = 0..15)
865 pub mod PUPDR3 {
866 /// Offset (6 bits)
867 pub const offset: u32 = 6;
868 /// Mask (2 bits: 0b11 << 6)
869 pub const mask: u32 = 0b11 << offset;
870 /// Read-only values (empty)
871 pub mod R {}
872 /// Write-only values (empty)
873 pub mod W {}
874 /// Read-write values (empty)
875 pub mod RW {}
876 }
877
878 /// Port x configuration bits (y = 0..15)
879 pub mod PUPDR2 {
880 /// Offset (4 bits)
881 pub const offset: u32 = 4;
882 /// Mask (2 bits: 0b11 << 4)
883 pub const mask: u32 = 0b11 << offset;
884 /// Read-only values (empty)
885 pub mod R {}
886 /// Write-only values (empty)
887 pub mod W {}
888 /// Read-write values (empty)
889 pub mod RW {}
890 }
891
892 /// Port x configuration bits (y = 0..15)
893 pub mod PUPDR1 {
894 /// Offset (2 bits)
895 pub const offset: u32 = 2;
896 /// Mask (2 bits: 0b11 << 2)
897 pub const mask: u32 = 0b11 << offset;
898 /// Read-only values (empty)
899 pub mod R {}
900 /// Write-only values (empty)
901 pub mod W {}
902 /// Read-write values (empty)
903 pub mod RW {}
904 }
905
906 /// Port x configuration bits (y = 0..15)
907 pub mod PUPDR0 {
908 /// Offset (0 bits)
909 pub const offset: u32 = 0;
910 /// Mask (2 bits: 0b11 << 0)
911 pub const mask: u32 = 0b11 << offset;
912 /// Read-only values (empty)
913 pub mod R {}
914 /// Write-only values (empty)
915 pub mod W {}
916 /// Read-write values (empty)
917 pub mod RW {}
918 }
919}
920
921/// GPIO port input data register
922pub mod IDR {
923
924 /// Port input data (y = 0..15)
925 pub mod IDR15 {
926 /// Offset (15 bits)
927 pub const offset: u32 = 15;
928 /// Mask (1 bit: 1 << 15)
929 pub const mask: u32 = 1 << offset;
930 /// Read-only values (empty)
931 pub mod R {}
932 /// Write-only values (empty)
933 pub mod W {}
934 /// Read-write values (empty)
935 pub mod RW {}
936 }
937
938 /// Port input data (y = 0..15)
939 pub mod IDR14 {
940 /// Offset (14 bits)
941 pub const offset: u32 = 14;
942 /// Mask (1 bit: 1 << 14)
943 pub const mask: u32 = 1 << offset;
944 /// Read-only values (empty)
945 pub mod R {}
946 /// Write-only values (empty)
947 pub mod W {}
948 /// Read-write values (empty)
949 pub mod RW {}
950 }
951
952 /// Port input data (y = 0..15)
953 pub mod IDR13 {
954 /// Offset (13 bits)
955 pub const offset: u32 = 13;
956 /// Mask (1 bit: 1 << 13)
957 pub const mask: u32 = 1 << offset;
958 /// Read-only values (empty)
959 pub mod R {}
960 /// Write-only values (empty)
961 pub mod W {}
962 /// Read-write values (empty)
963 pub mod RW {}
964 }
965
966 /// Port input data (y = 0..15)
967 pub mod IDR12 {
968 /// Offset (12 bits)
969 pub const offset: u32 = 12;
970 /// Mask (1 bit: 1 << 12)
971 pub const mask: u32 = 1 << offset;
972 /// Read-only values (empty)
973 pub mod R {}
974 /// Write-only values (empty)
975 pub mod W {}
976 /// Read-write values (empty)
977 pub mod RW {}
978 }
979
980 /// Port input data (y = 0..15)
981 pub mod IDR11 {
982 /// Offset (11 bits)
983 pub const offset: u32 = 11;
984 /// Mask (1 bit: 1 << 11)
985 pub const mask: u32 = 1 << offset;
986 /// Read-only values (empty)
987 pub mod R {}
988 /// Write-only values (empty)
989 pub mod W {}
990 /// Read-write values (empty)
991 pub mod RW {}
992 }
993
994 /// Port input data (y = 0..15)
995 pub mod IDR10 {
996 /// Offset (10 bits)
997 pub const offset: u32 = 10;
998 /// Mask (1 bit: 1 << 10)
999 pub const mask: u32 = 1 << offset;
1000 /// Read-only values (empty)
1001 pub mod R {}
1002 /// Write-only values (empty)
1003 pub mod W {}
1004 /// Read-write values (empty)
1005 pub mod RW {}
1006 }
1007
1008 /// Port input data (y = 0..15)
1009 pub mod IDR9 {
1010 /// Offset (9 bits)
1011 pub const offset: u32 = 9;
1012 /// Mask (1 bit: 1 << 9)
1013 pub const mask: u32 = 1 << offset;
1014 /// Read-only values (empty)
1015 pub mod R {}
1016 /// Write-only values (empty)
1017 pub mod W {}
1018 /// Read-write values (empty)
1019 pub mod RW {}
1020 }
1021
1022 /// Port input data (y = 0..15)
1023 pub mod IDR8 {
1024 /// Offset (8 bits)
1025 pub const offset: u32 = 8;
1026 /// Mask (1 bit: 1 << 8)
1027 pub const mask: u32 = 1 << offset;
1028 /// Read-only values (empty)
1029 pub mod R {}
1030 /// Write-only values (empty)
1031 pub mod W {}
1032 /// Read-write values (empty)
1033 pub mod RW {}
1034 }
1035
1036 /// Port input data (y = 0..15)
1037 pub mod IDR7 {
1038 /// Offset (7 bits)
1039 pub const offset: u32 = 7;
1040 /// Mask (1 bit: 1 << 7)
1041 pub const mask: u32 = 1 << offset;
1042 /// Read-only values (empty)
1043 pub mod R {}
1044 /// Write-only values (empty)
1045 pub mod W {}
1046 /// Read-write values (empty)
1047 pub mod RW {}
1048 }
1049
1050 /// Port input data (y = 0..15)
1051 pub mod IDR6 {
1052 /// Offset (6 bits)
1053 pub const offset: u32 = 6;
1054 /// Mask (1 bit: 1 << 6)
1055 pub const mask: u32 = 1 << offset;
1056 /// Read-only values (empty)
1057 pub mod R {}
1058 /// Write-only values (empty)
1059 pub mod W {}
1060 /// Read-write values (empty)
1061 pub mod RW {}
1062 }
1063
1064 /// Port input data (y = 0..15)
1065 pub mod IDR5 {
1066 /// Offset (5 bits)
1067 pub const offset: u32 = 5;
1068 /// Mask (1 bit: 1 << 5)
1069 pub const mask: u32 = 1 << offset;
1070 /// Read-only values (empty)
1071 pub mod R {}
1072 /// Write-only values (empty)
1073 pub mod W {}
1074 /// Read-write values (empty)
1075 pub mod RW {}
1076 }
1077
1078 /// Port input data (y = 0..15)
1079 pub mod IDR4 {
1080 /// Offset (4 bits)
1081 pub const offset: u32 = 4;
1082 /// Mask (1 bit: 1 << 4)
1083 pub const mask: u32 = 1 << offset;
1084 /// Read-only values (empty)
1085 pub mod R {}
1086 /// Write-only values (empty)
1087 pub mod W {}
1088 /// Read-write values (empty)
1089 pub mod RW {}
1090 }
1091
1092 /// Port input data (y = 0..15)
1093 pub mod IDR3 {
1094 /// Offset (3 bits)
1095 pub const offset: u32 = 3;
1096 /// Mask (1 bit: 1 << 3)
1097 pub const mask: u32 = 1 << offset;
1098 /// Read-only values (empty)
1099 pub mod R {}
1100 /// Write-only values (empty)
1101 pub mod W {}
1102 /// Read-write values (empty)
1103 pub mod RW {}
1104 }
1105
1106 /// Port input data (y = 0..15)
1107 pub mod IDR2 {
1108 /// Offset (2 bits)
1109 pub const offset: u32 = 2;
1110 /// Mask (1 bit: 1 << 2)
1111 pub const mask: u32 = 1 << offset;
1112 /// Read-only values (empty)
1113 pub mod R {}
1114 /// Write-only values (empty)
1115 pub mod W {}
1116 /// Read-write values (empty)
1117 pub mod RW {}
1118 }
1119
1120 /// Port input data (y = 0..15)
1121 pub mod IDR1 {
1122 /// Offset (1 bits)
1123 pub const offset: u32 = 1;
1124 /// Mask (1 bit: 1 << 1)
1125 pub const mask: u32 = 1 << offset;
1126 /// Read-only values (empty)
1127 pub mod R {}
1128 /// Write-only values (empty)
1129 pub mod W {}
1130 /// Read-write values (empty)
1131 pub mod RW {}
1132 }
1133
1134 /// Port input data (y = 0..15)
1135 pub mod IDR0 {
1136 /// Offset (0 bits)
1137 pub const offset: u32 = 0;
1138 /// Mask (1 bit: 1 << 0)
1139 pub const mask: u32 = 1 << offset;
1140 /// Read-only values (empty)
1141 pub mod R {}
1142 /// Write-only values (empty)
1143 pub mod W {}
1144 /// Read-write values (empty)
1145 pub mod RW {}
1146 }
1147}
1148
1149/// GPIO port output data register
1150pub mod ODR {
1151
1152 /// Port output data (y = 0..15)
1153 pub mod ODR15 {
1154 /// Offset (15 bits)
1155 pub const offset: u32 = 15;
1156 /// Mask (1 bit: 1 << 15)
1157 pub const mask: u32 = 1 << offset;
1158 /// Read-only values (empty)
1159 pub mod R {}
1160 /// Write-only values (empty)
1161 pub mod W {}
1162 /// Read-write values (empty)
1163 pub mod RW {}
1164 }
1165
1166 /// Port output data (y = 0..15)
1167 pub mod ODR14 {
1168 /// Offset (14 bits)
1169 pub const offset: u32 = 14;
1170 /// Mask (1 bit: 1 << 14)
1171 pub const mask: u32 = 1 << offset;
1172 /// Read-only values (empty)
1173 pub mod R {}
1174 /// Write-only values (empty)
1175 pub mod W {}
1176 /// Read-write values (empty)
1177 pub mod RW {}
1178 }
1179
1180 /// Port output data (y = 0..15)
1181 pub mod ODR13 {
1182 /// Offset (13 bits)
1183 pub const offset: u32 = 13;
1184 /// Mask (1 bit: 1 << 13)
1185 pub const mask: u32 = 1 << offset;
1186 /// Read-only values (empty)
1187 pub mod R {}
1188 /// Write-only values (empty)
1189 pub mod W {}
1190 /// Read-write values (empty)
1191 pub mod RW {}
1192 }
1193
1194 /// Port output data (y = 0..15)
1195 pub mod ODR12 {
1196 /// Offset (12 bits)
1197 pub const offset: u32 = 12;
1198 /// Mask (1 bit: 1 << 12)
1199 pub const mask: u32 = 1 << offset;
1200 /// Read-only values (empty)
1201 pub mod R {}
1202 /// Write-only values (empty)
1203 pub mod W {}
1204 /// Read-write values (empty)
1205 pub mod RW {}
1206 }
1207
1208 /// Port output data (y = 0..15)
1209 pub mod ODR11 {
1210 /// Offset (11 bits)
1211 pub const offset: u32 = 11;
1212 /// Mask (1 bit: 1 << 11)
1213 pub const mask: u32 = 1 << offset;
1214 /// Read-only values (empty)
1215 pub mod R {}
1216 /// Write-only values (empty)
1217 pub mod W {}
1218 /// Read-write values (empty)
1219 pub mod RW {}
1220 }
1221
1222 /// Port output data (y = 0..15)
1223 pub mod ODR10 {
1224 /// Offset (10 bits)
1225 pub const offset: u32 = 10;
1226 /// Mask (1 bit: 1 << 10)
1227 pub const mask: u32 = 1 << offset;
1228 /// Read-only values (empty)
1229 pub mod R {}
1230 /// Write-only values (empty)
1231 pub mod W {}
1232 /// Read-write values (empty)
1233 pub mod RW {}
1234 }
1235
1236 /// Port output data (y = 0..15)
1237 pub mod ODR9 {
1238 /// Offset (9 bits)
1239 pub const offset: u32 = 9;
1240 /// Mask (1 bit: 1 << 9)
1241 pub const mask: u32 = 1 << offset;
1242 /// Read-only values (empty)
1243 pub mod R {}
1244 /// Write-only values (empty)
1245 pub mod W {}
1246 /// Read-write values (empty)
1247 pub mod RW {}
1248 }
1249
1250 /// Port output data (y = 0..15)
1251 pub mod ODR8 {
1252 /// Offset (8 bits)
1253 pub const offset: u32 = 8;
1254 /// Mask (1 bit: 1 << 8)
1255 pub const mask: u32 = 1 << offset;
1256 /// Read-only values (empty)
1257 pub mod R {}
1258 /// Write-only values (empty)
1259 pub mod W {}
1260 /// Read-write values (empty)
1261 pub mod RW {}
1262 }
1263
1264 /// Port output data (y = 0..15)
1265 pub mod ODR7 {
1266 /// Offset (7 bits)
1267 pub const offset: u32 = 7;
1268 /// Mask (1 bit: 1 << 7)
1269 pub const mask: u32 = 1 << offset;
1270 /// Read-only values (empty)
1271 pub mod R {}
1272 /// Write-only values (empty)
1273 pub mod W {}
1274 /// Read-write values (empty)
1275 pub mod RW {}
1276 }
1277
1278 /// Port output data (y = 0..15)
1279 pub mod ODR6 {
1280 /// Offset (6 bits)
1281 pub const offset: u32 = 6;
1282 /// Mask (1 bit: 1 << 6)
1283 pub const mask: u32 = 1 << offset;
1284 /// Read-only values (empty)
1285 pub mod R {}
1286 /// Write-only values (empty)
1287 pub mod W {}
1288 /// Read-write values (empty)
1289 pub mod RW {}
1290 }
1291
1292 /// Port output data (y = 0..15)
1293 pub mod ODR5 {
1294 /// Offset (5 bits)
1295 pub const offset: u32 = 5;
1296 /// Mask (1 bit: 1 << 5)
1297 pub const mask: u32 = 1 << offset;
1298 /// Read-only values (empty)
1299 pub mod R {}
1300 /// Write-only values (empty)
1301 pub mod W {}
1302 /// Read-write values (empty)
1303 pub mod RW {}
1304 }
1305
1306 /// Port output data (y = 0..15)
1307 pub mod ODR4 {
1308 /// Offset (4 bits)
1309 pub const offset: u32 = 4;
1310 /// Mask (1 bit: 1 << 4)
1311 pub const mask: u32 = 1 << offset;
1312 /// Read-only values (empty)
1313 pub mod R {}
1314 /// Write-only values (empty)
1315 pub mod W {}
1316 /// Read-write values (empty)
1317 pub mod RW {}
1318 }
1319
1320 /// Port output data (y = 0..15)
1321 pub mod ODR3 {
1322 /// Offset (3 bits)
1323 pub const offset: u32 = 3;
1324 /// Mask (1 bit: 1 << 3)
1325 pub const mask: u32 = 1 << offset;
1326 /// Read-only values (empty)
1327 pub mod R {}
1328 /// Write-only values (empty)
1329 pub mod W {}
1330 /// Read-write values (empty)
1331 pub mod RW {}
1332 }
1333
1334 /// Port output data (y = 0..15)
1335 pub mod ODR2 {
1336 /// Offset (2 bits)
1337 pub const offset: u32 = 2;
1338 /// Mask (1 bit: 1 << 2)
1339 pub const mask: u32 = 1 << offset;
1340 /// Read-only values (empty)
1341 pub mod R {}
1342 /// Write-only values (empty)
1343 pub mod W {}
1344 /// Read-write values (empty)
1345 pub mod RW {}
1346 }
1347
1348 /// Port output data (y = 0..15)
1349 pub mod ODR1 {
1350 /// Offset (1 bits)
1351 pub const offset: u32 = 1;
1352 /// Mask (1 bit: 1 << 1)
1353 pub const mask: u32 = 1 << offset;
1354 /// Read-only values (empty)
1355 pub mod R {}
1356 /// Write-only values (empty)
1357 pub mod W {}
1358 /// Read-write values (empty)
1359 pub mod RW {}
1360 }
1361
1362 /// Port output data (y = 0..15)
1363 pub mod ODR0 {
1364 /// Offset (0 bits)
1365 pub const offset: u32 = 0;
1366 /// Mask (1 bit: 1 << 0)
1367 pub const mask: u32 = 1 << offset;
1368 /// Read-only values (empty)
1369 pub mod R {}
1370 /// Write-only values (empty)
1371 pub mod W {}
1372 /// Read-write values (empty)
1373 pub mod RW {}
1374 }
1375}
1376
1377/// GPIO port bit set/reset register
1378pub mod BSRR {
1379
1380 /// Port x reset bit y (y = 0..15)
1381 pub mod BR15 {
1382 /// Offset (31 bits)
1383 pub const offset: u32 = 31;
1384 /// Mask (1 bit: 1 << 31)
1385 pub const mask: u32 = 1 << offset;
1386 /// Read-only values (empty)
1387 pub mod R {}
1388 /// Write-only values (empty)
1389 pub mod W {}
1390 /// Read-write values (empty)
1391 pub mod RW {}
1392 }
1393
1394 /// Port x reset bit y (y = 0..15)
1395 pub mod BR14 {
1396 /// Offset (30 bits)
1397 pub const offset: u32 = 30;
1398 /// Mask (1 bit: 1 << 30)
1399 pub const mask: u32 = 1 << offset;
1400 /// Read-only values (empty)
1401 pub mod R {}
1402 /// Write-only values (empty)
1403 pub mod W {}
1404 /// Read-write values (empty)
1405 pub mod RW {}
1406 }
1407
1408 /// Port x reset bit y (y = 0..15)
1409 pub mod BR13 {
1410 /// Offset (29 bits)
1411 pub const offset: u32 = 29;
1412 /// Mask (1 bit: 1 << 29)
1413 pub const mask: u32 = 1 << offset;
1414 /// Read-only values (empty)
1415 pub mod R {}
1416 /// Write-only values (empty)
1417 pub mod W {}
1418 /// Read-write values (empty)
1419 pub mod RW {}
1420 }
1421
1422 /// Port x reset bit y (y = 0..15)
1423 pub mod BR12 {
1424 /// Offset (28 bits)
1425 pub const offset: u32 = 28;
1426 /// Mask (1 bit: 1 << 28)
1427 pub const mask: u32 = 1 << offset;
1428 /// Read-only values (empty)
1429 pub mod R {}
1430 /// Write-only values (empty)
1431 pub mod W {}
1432 /// Read-write values (empty)
1433 pub mod RW {}
1434 }
1435
1436 /// Port x reset bit y (y = 0..15)
1437 pub mod BR11 {
1438 /// Offset (27 bits)
1439 pub const offset: u32 = 27;
1440 /// Mask (1 bit: 1 << 27)
1441 pub const mask: u32 = 1 << offset;
1442 /// Read-only values (empty)
1443 pub mod R {}
1444 /// Write-only values (empty)
1445 pub mod W {}
1446 /// Read-write values (empty)
1447 pub mod RW {}
1448 }
1449
1450 /// Port x reset bit y (y = 0..15)
1451 pub mod BR10 {
1452 /// Offset (26 bits)
1453 pub const offset: u32 = 26;
1454 /// Mask (1 bit: 1 << 26)
1455 pub const mask: u32 = 1 << offset;
1456 /// Read-only values (empty)
1457 pub mod R {}
1458 /// Write-only values (empty)
1459 pub mod W {}
1460 /// Read-write values (empty)
1461 pub mod RW {}
1462 }
1463
1464 /// Port x reset bit y (y = 0..15)
1465 pub mod BR9 {
1466 /// Offset (25 bits)
1467 pub const offset: u32 = 25;
1468 /// Mask (1 bit: 1 << 25)
1469 pub const mask: u32 = 1 << offset;
1470 /// Read-only values (empty)
1471 pub mod R {}
1472 /// Write-only values (empty)
1473 pub mod W {}
1474 /// Read-write values (empty)
1475 pub mod RW {}
1476 }
1477
1478 /// Port x reset bit y (y = 0..15)
1479 pub mod BR8 {
1480 /// Offset (24 bits)
1481 pub const offset: u32 = 24;
1482 /// Mask (1 bit: 1 << 24)
1483 pub const mask: u32 = 1 << offset;
1484 /// Read-only values (empty)
1485 pub mod R {}
1486 /// Write-only values (empty)
1487 pub mod W {}
1488 /// Read-write values (empty)
1489 pub mod RW {}
1490 }
1491
1492 /// Port x reset bit y (y = 0..15)
1493 pub mod BR7 {
1494 /// Offset (23 bits)
1495 pub const offset: u32 = 23;
1496 /// Mask (1 bit: 1 << 23)
1497 pub const mask: u32 = 1 << offset;
1498 /// Read-only values (empty)
1499 pub mod R {}
1500 /// Write-only values (empty)
1501 pub mod W {}
1502 /// Read-write values (empty)
1503 pub mod RW {}
1504 }
1505
1506 /// Port x reset bit y (y = 0..15)
1507 pub mod BR6 {
1508 /// Offset (22 bits)
1509 pub const offset: u32 = 22;
1510 /// Mask (1 bit: 1 << 22)
1511 pub const mask: u32 = 1 << offset;
1512 /// Read-only values (empty)
1513 pub mod R {}
1514 /// Write-only values (empty)
1515 pub mod W {}
1516 /// Read-write values (empty)
1517 pub mod RW {}
1518 }
1519
1520 /// Port x reset bit y (y = 0..15)
1521 pub mod BR5 {
1522 /// Offset (21 bits)
1523 pub const offset: u32 = 21;
1524 /// Mask (1 bit: 1 << 21)
1525 pub const mask: u32 = 1 << offset;
1526 /// Read-only values (empty)
1527 pub mod R {}
1528 /// Write-only values (empty)
1529 pub mod W {}
1530 /// Read-write values (empty)
1531 pub mod RW {}
1532 }
1533
1534 /// Port x reset bit y (y = 0..15)
1535 pub mod BR4 {
1536 /// Offset (20 bits)
1537 pub const offset: u32 = 20;
1538 /// Mask (1 bit: 1 << 20)
1539 pub const mask: u32 = 1 << offset;
1540 /// Read-only values (empty)
1541 pub mod R {}
1542 /// Write-only values (empty)
1543 pub mod W {}
1544 /// Read-write values (empty)
1545 pub mod RW {}
1546 }
1547
1548 /// Port x reset bit y (y = 0..15)
1549 pub mod BR3 {
1550 /// Offset (19 bits)
1551 pub const offset: u32 = 19;
1552 /// Mask (1 bit: 1 << 19)
1553 pub const mask: u32 = 1 << offset;
1554 /// Read-only values (empty)
1555 pub mod R {}
1556 /// Write-only values (empty)
1557 pub mod W {}
1558 /// Read-write values (empty)
1559 pub mod RW {}
1560 }
1561
1562 /// Port x reset bit y (y = 0..15)
1563 pub mod BR2 {
1564 /// Offset (18 bits)
1565 pub const offset: u32 = 18;
1566 /// Mask (1 bit: 1 << 18)
1567 pub const mask: u32 = 1 << offset;
1568 /// Read-only values (empty)
1569 pub mod R {}
1570 /// Write-only values (empty)
1571 pub mod W {}
1572 /// Read-write values (empty)
1573 pub mod RW {}
1574 }
1575
1576 /// Port x reset bit y (y = 0..15)
1577 pub mod BR1 {
1578 /// Offset (17 bits)
1579 pub const offset: u32 = 17;
1580 /// Mask (1 bit: 1 << 17)
1581 pub const mask: u32 = 1 << offset;
1582 /// Read-only values (empty)
1583 pub mod R {}
1584 /// Write-only values (empty)
1585 pub mod W {}
1586 /// Read-write values (empty)
1587 pub mod RW {}
1588 }
1589
1590 /// Port x set bit y (y= 0..15)
1591 pub mod BR0 {
1592 /// Offset (16 bits)
1593 pub const offset: u32 = 16;
1594 /// Mask (1 bit: 1 << 16)
1595 pub const mask: u32 = 1 << offset;
1596 /// Read-only values (empty)
1597 pub mod R {}
1598 /// Write-only values (empty)
1599 pub mod W {}
1600 /// Read-write values (empty)
1601 pub mod RW {}
1602 }
1603
1604 /// Port x set bit y (y= 0..15)
1605 pub mod BS15 {
1606 /// Offset (15 bits)
1607 pub const offset: u32 = 15;
1608 /// Mask (1 bit: 1 << 15)
1609 pub const mask: u32 = 1 << offset;
1610 /// Read-only values (empty)
1611 pub mod R {}
1612 /// Write-only values (empty)
1613 pub mod W {}
1614 /// Read-write values (empty)
1615 pub mod RW {}
1616 }
1617
1618 /// Port x set bit y (y= 0..15)
1619 pub mod BS14 {
1620 /// Offset (14 bits)
1621 pub const offset: u32 = 14;
1622 /// Mask (1 bit: 1 << 14)
1623 pub const mask: u32 = 1 << offset;
1624 /// Read-only values (empty)
1625 pub mod R {}
1626 /// Write-only values (empty)
1627 pub mod W {}
1628 /// Read-write values (empty)
1629 pub mod RW {}
1630 }
1631
1632 /// Port x set bit y (y= 0..15)
1633 pub mod BS13 {
1634 /// Offset (13 bits)
1635 pub const offset: u32 = 13;
1636 /// Mask (1 bit: 1 << 13)
1637 pub const mask: u32 = 1 << offset;
1638 /// Read-only values (empty)
1639 pub mod R {}
1640 /// Write-only values (empty)
1641 pub mod W {}
1642 /// Read-write values (empty)
1643 pub mod RW {}
1644 }
1645
1646 /// Port x set bit y (y= 0..15)
1647 pub mod BS12 {
1648 /// Offset (12 bits)
1649 pub const offset: u32 = 12;
1650 /// Mask (1 bit: 1 << 12)
1651 pub const mask: u32 = 1 << offset;
1652 /// Read-only values (empty)
1653 pub mod R {}
1654 /// Write-only values (empty)
1655 pub mod W {}
1656 /// Read-write values (empty)
1657 pub mod RW {}
1658 }
1659
1660 /// Port x set bit y (y= 0..15)
1661 pub mod BS11 {
1662 /// Offset (11 bits)
1663 pub const offset: u32 = 11;
1664 /// Mask (1 bit: 1 << 11)
1665 pub const mask: u32 = 1 << offset;
1666 /// Read-only values (empty)
1667 pub mod R {}
1668 /// Write-only values (empty)
1669 pub mod W {}
1670 /// Read-write values (empty)
1671 pub mod RW {}
1672 }
1673
1674 /// Port x set bit y (y= 0..15)
1675 pub mod BS10 {
1676 /// Offset (10 bits)
1677 pub const offset: u32 = 10;
1678 /// Mask (1 bit: 1 << 10)
1679 pub const mask: u32 = 1 << offset;
1680 /// Read-only values (empty)
1681 pub mod R {}
1682 /// Write-only values (empty)
1683 pub mod W {}
1684 /// Read-write values (empty)
1685 pub mod RW {}
1686 }
1687
1688 /// Port x set bit y (y= 0..15)
1689 pub mod BS9 {
1690 /// Offset (9 bits)
1691 pub const offset: u32 = 9;
1692 /// Mask (1 bit: 1 << 9)
1693 pub const mask: u32 = 1 << offset;
1694 /// Read-only values (empty)
1695 pub mod R {}
1696 /// Write-only values (empty)
1697 pub mod W {}
1698 /// Read-write values (empty)
1699 pub mod RW {}
1700 }
1701
1702 /// Port x set bit y (y= 0..15)
1703 pub mod BS8 {
1704 /// Offset (8 bits)
1705 pub const offset: u32 = 8;
1706 /// Mask (1 bit: 1 << 8)
1707 pub const mask: u32 = 1 << offset;
1708 /// Read-only values (empty)
1709 pub mod R {}
1710 /// Write-only values (empty)
1711 pub mod W {}
1712 /// Read-write values (empty)
1713 pub mod RW {}
1714 }
1715
1716 /// Port x set bit y (y= 0..15)
1717 pub mod BS7 {
1718 /// Offset (7 bits)
1719 pub const offset: u32 = 7;
1720 /// Mask (1 bit: 1 << 7)
1721 pub const mask: u32 = 1 << offset;
1722 /// Read-only values (empty)
1723 pub mod R {}
1724 /// Write-only values (empty)
1725 pub mod W {}
1726 /// Read-write values (empty)
1727 pub mod RW {}
1728 }
1729
1730 /// Port x set bit y (y= 0..15)
1731 pub mod BS6 {
1732 /// Offset (6 bits)
1733 pub const offset: u32 = 6;
1734 /// Mask (1 bit: 1 << 6)
1735 pub const mask: u32 = 1 << offset;
1736 /// Read-only values (empty)
1737 pub mod R {}
1738 /// Write-only values (empty)
1739 pub mod W {}
1740 /// Read-write values (empty)
1741 pub mod RW {}
1742 }
1743
1744 /// Port x set bit y (y= 0..15)
1745 pub mod BS5 {
1746 /// Offset (5 bits)
1747 pub const offset: u32 = 5;
1748 /// Mask (1 bit: 1 << 5)
1749 pub const mask: u32 = 1 << offset;
1750 /// Read-only values (empty)
1751 pub mod R {}
1752 /// Write-only values (empty)
1753 pub mod W {}
1754 /// Read-write values (empty)
1755 pub mod RW {}
1756 }
1757
1758 /// Port x set bit y (y= 0..15)
1759 pub mod BS4 {
1760 /// Offset (4 bits)
1761 pub const offset: u32 = 4;
1762 /// Mask (1 bit: 1 << 4)
1763 pub const mask: u32 = 1 << offset;
1764 /// Read-only values (empty)
1765 pub mod R {}
1766 /// Write-only values (empty)
1767 pub mod W {}
1768 /// Read-write values (empty)
1769 pub mod RW {}
1770 }
1771
1772 /// Port x set bit y (y= 0..15)
1773 pub mod BS3 {
1774 /// Offset (3 bits)
1775 pub const offset: u32 = 3;
1776 /// Mask (1 bit: 1 << 3)
1777 pub const mask: u32 = 1 << offset;
1778 /// Read-only values (empty)
1779 pub mod R {}
1780 /// Write-only values (empty)
1781 pub mod W {}
1782 /// Read-write values (empty)
1783 pub mod RW {}
1784 }
1785
1786 /// Port x set bit y (y= 0..15)
1787 pub mod BS2 {
1788 /// Offset (2 bits)
1789 pub const offset: u32 = 2;
1790 /// Mask (1 bit: 1 << 2)
1791 pub const mask: u32 = 1 << offset;
1792 /// Read-only values (empty)
1793 pub mod R {}
1794 /// Write-only values (empty)
1795 pub mod W {}
1796 /// Read-write values (empty)
1797 pub mod RW {}
1798 }
1799
1800 /// Port x set bit y (y= 0..15)
1801 pub mod BS1 {
1802 /// Offset (1 bits)
1803 pub const offset: u32 = 1;
1804 /// Mask (1 bit: 1 << 1)
1805 pub const mask: u32 = 1 << offset;
1806 /// Read-only values (empty)
1807 pub mod R {}
1808 /// Write-only values (empty)
1809 pub mod W {}
1810 /// Read-write values (empty)
1811 pub mod RW {}
1812 }
1813
1814 /// Port x set bit y (y= 0..15)
1815 pub mod BS0 {
1816 /// Offset (0 bits)
1817 pub const offset: u32 = 0;
1818 /// Mask (1 bit: 1 << 0)
1819 pub const mask: u32 = 1 << offset;
1820 /// Read-only values (empty)
1821 pub mod R {}
1822 /// Write-only values (empty)
1823 pub mod W {}
1824 /// Read-write values (empty)
1825 pub mod RW {}
1826 }
1827}
1828
1829/// GPIO port configuration lock register
1830pub mod LCKR {
1831
1832 /// Port x lock bit y (y= 0..15)
1833 pub mod LCKK {
1834 /// Offset (16 bits)
1835 pub const offset: u32 = 16;
1836 /// Mask (1 bit: 1 << 16)
1837 pub const mask: u32 = 1 << offset;
1838 /// Read-only values (empty)
1839 pub mod R {}
1840 /// Write-only values (empty)
1841 pub mod W {}
1842 /// Read-write values (empty)
1843 pub mod RW {}
1844 }
1845
1846 /// Port x lock bit y (y= 0..15)
1847 pub mod LCK15 {
1848 /// Offset (15 bits)
1849 pub const offset: u32 = 15;
1850 /// Mask (1 bit: 1 << 15)
1851 pub const mask: u32 = 1 << offset;
1852 /// Read-only values (empty)
1853 pub mod R {}
1854 /// Write-only values (empty)
1855 pub mod W {}
1856 /// Read-write values (empty)
1857 pub mod RW {}
1858 }
1859
1860 /// Port x lock bit y (y= 0..15)
1861 pub mod LCK14 {
1862 /// Offset (14 bits)
1863 pub const offset: u32 = 14;
1864 /// Mask (1 bit: 1 << 14)
1865 pub const mask: u32 = 1 << offset;
1866 /// Read-only values (empty)
1867 pub mod R {}
1868 /// Write-only values (empty)
1869 pub mod W {}
1870 /// Read-write values (empty)
1871 pub mod RW {}
1872 }
1873
1874 /// Port x lock bit y (y= 0..15)
1875 pub mod LCK13 {
1876 /// Offset (13 bits)
1877 pub const offset: u32 = 13;
1878 /// Mask (1 bit: 1 << 13)
1879 pub const mask: u32 = 1 << offset;
1880 /// Read-only values (empty)
1881 pub mod R {}
1882 /// Write-only values (empty)
1883 pub mod W {}
1884 /// Read-write values (empty)
1885 pub mod RW {}
1886 }
1887
1888 /// Port x lock bit y (y= 0..15)
1889 pub mod LCK12 {
1890 /// Offset (12 bits)
1891 pub const offset: u32 = 12;
1892 /// Mask (1 bit: 1 << 12)
1893 pub const mask: u32 = 1 << offset;
1894 /// Read-only values (empty)
1895 pub mod R {}
1896 /// Write-only values (empty)
1897 pub mod W {}
1898 /// Read-write values (empty)
1899 pub mod RW {}
1900 }
1901
1902 /// Port x lock bit y (y= 0..15)
1903 pub mod LCK11 {
1904 /// Offset (11 bits)
1905 pub const offset: u32 = 11;
1906 /// Mask (1 bit: 1 << 11)
1907 pub const mask: u32 = 1 << offset;
1908 /// Read-only values (empty)
1909 pub mod R {}
1910 /// Write-only values (empty)
1911 pub mod W {}
1912 /// Read-write values (empty)
1913 pub mod RW {}
1914 }
1915
1916 /// Port x lock bit y (y= 0..15)
1917 pub mod LCK10 {
1918 /// Offset (10 bits)
1919 pub const offset: u32 = 10;
1920 /// Mask (1 bit: 1 << 10)
1921 pub const mask: u32 = 1 << offset;
1922 /// Read-only values (empty)
1923 pub mod R {}
1924 /// Write-only values (empty)
1925 pub mod W {}
1926 /// Read-write values (empty)
1927 pub mod RW {}
1928 }
1929
1930 /// Port x lock bit y (y= 0..15)
1931 pub mod LCK9 {
1932 /// Offset (9 bits)
1933 pub const offset: u32 = 9;
1934 /// Mask (1 bit: 1 << 9)
1935 pub const mask: u32 = 1 << offset;
1936 /// Read-only values (empty)
1937 pub mod R {}
1938 /// Write-only values (empty)
1939 pub mod W {}
1940 /// Read-write values (empty)
1941 pub mod RW {}
1942 }
1943
1944 /// Port x lock bit y (y= 0..15)
1945 pub mod LCK8 {
1946 /// Offset (8 bits)
1947 pub const offset: u32 = 8;
1948 /// Mask (1 bit: 1 << 8)
1949 pub const mask: u32 = 1 << offset;
1950 /// Read-only values (empty)
1951 pub mod R {}
1952 /// Write-only values (empty)
1953 pub mod W {}
1954 /// Read-write values (empty)
1955 pub mod RW {}
1956 }
1957
1958 /// Port x lock bit y (y= 0..15)
1959 pub mod LCK7 {
1960 /// Offset (7 bits)
1961 pub const offset: u32 = 7;
1962 /// Mask (1 bit: 1 << 7)
1963 pub const mask: u32 = 1 << offset;
1964 /// Read-only values (empty)
1965 pub mod R {}
1966 /// Write-only values (empty)
1967 pub mod W {}
1968 /// Read-write values (empty)
1969 pub mod RW {}
1970 }
1971
1972 /// Port x lock bit y (y= 0..15)
1973 pub mod LCK6 {
1974 /// Offset (6 bits)
1975 pub const offset: u32 = 6;
1976 /// Mask (1 bit: 1 << 6)
1977 pub const mask: u32 = 1 << offset;
1978 /// Read-only values (empty)
1979 pub mod R {}
1980 /// Write-only values (empty)
1981 pub mod W {}
1982 /// Read-write values (empty)
1983 pub mod RW {}
1984 }
1985
1986 /// Port x lock bit y (y= 0..15)
1987 pub mod LCK5 {
1988 /// Offset (5 bits)
1989 pub const offset: u32 = 5;
1990 /// Mask (1 bit: 1 << 5)
1991 pub const mask: u32 = 1 << offset;
1992 /// Read-only values (empty)
1993 pub mod R {}
1994 /// Write-only values (empty)
1995 pub mod W {}
1996 /// Read-write values (empty)
1997 pub mod RW {}
1998 }
1999
2000 /// Port x lock bit y (y= 0..15)
2001 pub mod LCK4 {
2002 /// Offset (4 bits)
2003 pub const offset: u32 = 4;
2004 /// Mask (1 bit: 1 << 4)
2005 pub const mask: u32 = 1 << offset;
2006 /// Read-only values (empty)
2007 pub mod R {}
2008 /// Write-only values (empty)
2009 pub mod W {}
2010 /// Read-write values (empty)
2011 pub mod RW {}
2012 }
2013
2014 /// Port x lock bit y (y= 0..15)
2015 pub mod LCK3 {
2016 /// Offset (3 bits)
2017 pub const offset: u32 = 3;
2018 /// Mask (1 bit: 1 << 3)
2019 pub const mask: u32 = 1 << offset;
2020 /// Read-only values (empty)
2021 pub mod R {}
2022 /// Write-only values (empty)
2023 pub mod W {}
2024 /// Read-write values (empty)
2025 pub mod RW {}
2026 }
2027
2028 /// Port x lock bit y (y= 0..15)
2029 pub mod LCK2 {
2030 /// Offset (2 bits)
2031 pub const offset: u32 = 2;
2032 /// Mask (1 bit: 1 << 2)
2033 pub const mask: u32 = 1 << offset;
2034 /// Read-only values (empty)
2035 pub mod R {}
2036 /// Write-only values (empty)
2037 pub mod W {}
2038 /// Read-write values (empty)
2039 pub mod RW {}
2040 }
2041
2042 /// Port x lock bit y (y= 0..15)
2043 pub mod LCK1 {
2044 /// Offset (1 bits)
2045 pub const offset: u32 = 1;
2046 /// Mask (1 bit: 1 << 1)
2047 pub const mask: u32 = 1 << offset;
2048 /// Read-only values (empty)
2049 pub mod R {}
2050 /// Write-only values (empty)
2051 pub mod W {}
2052 /// Read-write values (empty)
2053 pub mod RW {}
2054 }
2055
2056 /// Port x lock bit y (y= 0..15)
2057 pub mod LCK0 {
2058 /// Offset (0 bits)
2059 pub const offset: u32 = 0;
2060 /// Mask (1 bit: 1 << 0)
2061 pub const mask: u32 = 1 << offset;
2062 /// Read-only values (empty)
2063 pub mod R {}
2064 /// Write-only values (empty)
2065 pub mod W {}
2066 /// Read-write values (empty)
2067 pub mod RW {}
2068 }
2069}
2070
2071/// GPIO alternate function low register
2072pub mod AFRL {
2073
2074 /// Alternate function selection for port x bit y (y = 0..7)
2075 pub mod AFSEL7 {
2076 /// Offset (28 bits)
2077 pub const offset: u32 = 28;
2078 /// Mask (4 bits: 0b1111 << 28)
2079 pub const mask: u32 = 0b1111 << offset;
2080 /// Read-only values (empty)
2081 pub mod R {}
2082 /// Write-only values (empty)
2083 pub mod W {}
2084 /// Read-write values (empty)
2085 pub mod RW {}
2086 }
2087
2088 /// Alternate function selection for port x bit y (y = 0..7)
2089 pub mod AFSEL6 {
2090 /// Offset (24 bits)
2091 pub const offset: u32 = 24;
2092 /// Mask (4 bits: 0b1111 << 24)
2093 pub const mask: u32 = 0b1111 << offset;
2094 /// Read-only values (empty)
2095 pub mod R {}
2096 /// Write-only values (empty)
2097 pub mod W {}
2098 /// Read-write values (empty)
2099 pub mod RW {}
2100 }
2101
2102 /// Alternate function selection for port x bit y (y = 0..7)
2103 pub mod AFSEL5 {
2104 /// Offset (20 bits)
2105 pub const offset: u32 = 20;
2106 /// Mask (4 bits: 0b1111 << 20)
2107 pub const mask: u32 = 0b1111 << offset;
2108 /// Read-only values (empty)
2109 pub mod R {}
2110 /// Write-only values (empty)
2111 pub mod W {}
2112 /// Read-write values (empty)
2113 pub mod RW {}
2114 }
2115
2116 /// Alternate function selection for port x bit y (y = 0..7)
2117 pub mod AFSEL4 {
2118 /// Offset (16 bits)
2119 pub const offset: u32 = 16;
2120 /// Mask (4 bits: 0b1111 << 16)
2121 pub const mask: u32 = 0b1111 << offset;
2122 /// Read-only values (empty)
2123 pub mod R {}
2124 /// Write-only values (empty)
2125 pub mod W {}
2126 /// Read-write values (empty)
2127 pub mod RW {}
2128 }
2129
2130 /// Alternate function selection for port x bit y (y = 0..7)
2131 pub mod AFSEL3 {
2132 /// Offset (12 bits)
2133 pub const offset: u32 = 12;
2134 /// Mask (4 bits: 0b1111 << 12)
2135 pub const mask: u32 = 0b1111 << offset;
2136 /// Read-only values (empty)
2137 pub mod R {}
2138 /// Write-only values (empty)
2139 pub mod W {}
2140 /// Read-write values (empty)
2141 pub mod RW {}
2142 }
2143
2144 /// Alternate function selection for port x bit y (y = 0..7)
2145 pub mod AFSEL2 {
2146 /// Offset (8 bits)
2147 pub const offset: u32 = 8;
2148 /// Mask (4 bits: 0b1111 << 8)
2149 pub const mask: u32 = 0b1111 << offset;
2150 /// Read-only values (empty)
2151 pub mod R {}
2152 /// Write-only values (empty)
2153 pub mod W {}
2154 /// Read-write values (empty)
2155 pub mod RW {}
2156 }
2157
2158 /// Alternate function selection for port x bit y (y = 0..7)
2159 pub mod AFSEL1 {
2160 /// Offset (4 bits)
2161 pub const offset: u32 = 4;
2162 /// Mask (4 bits: 0b1111 << 4)
2163 pub const mask: u32 = 0b1111 << offset;
2164 /// Read-only values (empty)
2165 pub mod R {}
2166 /// Write-only values (empty)
2167 pub mod W {}
2168 /// Read-write values (empty)
2169 pub mod RW {}
2170 }
2171
2172 /// Alternate function selection for port x bit y (y = 0..7)
2173 pub mod AFSEL0 {
2174 /// Offset (0 bits)
2175 pub const offset: u32 = 0;
2176 /// Mask (4 bits: 0b1111 << 0)
2177 pub const mask: u32 = 0b1111 << offset;
2178 /// Read-only values (empty)
2179 pub mod R {}
2180 /// Write-only values (empty)
2181 pub mod W {}
2182 /// Read-write values (empty)
2183 pub mod RW {}
2184 }
2185}
2186
2187/// GPIO alternate function high register
2188pub mod AFRH {
2189
2190 /// Alternate function selection for port x bit y (y = 8..15)
2191 pub mod AFSEL15 {
2192 /// Offset (28 bits)
2193 pub const offset: u32 = 28;
2194 /// Mask (4 bits: 0b1111 << 28)
2195 pub const mask: u32 = 0b1111 << offset;
2196 /// Read-only values (empty)
2197 pub mod R {}
2198 /// Write-only values (empty)
2199 pub mod W {}
2200 /// Read-write values (empty)
2201 pub mod RW {}
2202 }
2203
2204 /// Alternate function selection for port x bit y (y = 8..15)
2205 pub mod AFSEL14 {
2206 /// Offset (24 bits)
2207 pub const offset: u32 = 24;
2208 /// Mask (4 bits: 0b1111 << 24)
2209 pub const mask: u32 = 0b1111 << offset;
2210 /// Read-only values (empty)
2211 pub mod R {}
2212 /// Write-only values (empty)
2213 pub mod W {}
2214 /// Read-write values (empty)
2215 pub mod RW {}
2216 }
2217
2218 /// Alternate function selection for port x bit y (y = 8..15)
2219 pub mod AFSEL13 {
2220 /// Offset (20 bits)
2221 pub const offset: u32 = 20;
2222 /// Mask (4 bits: 0b1111 << 20)
2223 pub const mask: u32 = 0b1111 << offset;
2224 /// Read-only values (empty)
2225 pub mod R {}
2226 /// Write-only values (empty)
2227 pub mod W {}
2228 /// Read-write values (empty)
2229 pub mod RW {}
2230 }
2231
2232 /// Alternate function selection for port x bit y (y = 8..15)
2233 pub mod AFSEL12 {
2234 /// Offset (16 bits)
2235 pub const offset: u32 = 16;
2236 /// Mask (4 bits: 0b1111 << 16)
2237 pub const mask: u32 = 0b1111 << offset;
2238 /// Read-only values (empty)
2239 pub mod R {}
2240 /// Write-only values (empty)
2241 pub mod W {}
2242 /// Read-write values (empty)
2243 pub mod RW {}
2244 }
2245
2246 /// Alternate function selection for port x bit y (y = 8..15)
2247 pub mod AFSEL11 {
2248 /// Offset (12 bits)
2249 pub const offset: u32 = 12;
2250 /// Mask (4 bits: 0b1111 << 12)
2251 pub const mask: u32 = 0b1111 << offset;
2252 /// Read-only values (empty)
2253 pub mod R {}
2254 /// Write-only values (empty)
2255 pub mod W {}
2256 /// Read-write values (empty)
2257 pub mod RW {}
2258 }
2259
2260 /// Alternate function selection for port x bit y (y = 8..15)
2261 pub mod AFSEL10 {
2262 /// Offset (8 bits)
2263 pub const offset: u32 = 8;
2264 /// Mask (4 bits: 0b1111 << 8)
2265 pub const mask: u32 = 0b1111 << offset;
2266 /// Read-only values (empty)
2267 pub mod R {}
2268 /// Write-only values (empty)
2269 pub mod W {}
2270 /// Read-write values (empty)
2271 pub mod RW {}
2272 }
2273
2274 /// Alternate function selection for port x bit y (y = 8..15)
2275 pub mod AFSEL9 {
2276 /// Offset (4 bits)
2277 pub const offset: u32 = 4;
2278 /// Mask (4 bits: 0b1111 << 4)
2279 pub const mask: u32 = 0b1111 << offset;
2280 /// Read-only values (empty)
2281 pub mod R {}
2282 /// Write-only values (empty)
2283 pub mod W {}
2284 /// Read-write values (empty)
2285 pub mod RW {}
2286 }
2287
2288 /// Alternate function selection for port x bit y (y = 8..15)
2289 pub mod AFSEL8 {
2290 /// Offset (0 bits)
2291 pub const offset: u32 = 0;
2292 /// Mask (4 bits: 0b1111 << 0)
2293 pub const mask: u32 = 0b1111 << offset;
2294 /// Read-only values (empty)
2295 pub mod R {}
2296 /// Write-only values (empty)
2297 pub mod W {}
2298 /// Read-write values (empty)
2299 pub mod RW {}
2300 }
2301}
2302
2303/// port bit reset register
2304pub mod BRR {
2305
2306 /// Port Reset bit
2307 pub mod BR0 {
2308 /// Offset (0 bits)
2309 pub const offset: u32 = 0;
2310 /// Mask (1 bit: 1 << 0)
2311 pub const mask: u32 = 1 << offset;
2312 /// Read-only values (empty)
2313 pub mod R {}
2314 /// Write-only values (empty)
2315 pub mod W {}
2316 /// Read-write values (empty)
2317 pub mod RW {}
2318 }
2319
2320 /// Port Reset bit
2321 pub mod BR1 {
2322 /// Offset (1 bits)
2323 pub const offset: u32 = 1;
2324 /// Mask (1 bit: 1 << 1)
2325 pub const mask: u32 = 1 << offset;
2326 /// Read-only values (empty)
2327 pub mod R {}
2328 /// Write-only values (empty)
2329 pub mod W {}
2330 /// Read-write values (empty)
2331 pub mod RW {}
2332 }
2333
2334 /// Port Reset bit
2335 pub mod BR2 {
2336 /// Offset (2 bits)
2337 pub const offset: u32 = 2;
2338 /// Mask (1 bit: 1 << 2)
2339 pub const mask: u32 = 1 << offset;
2340 /// Read-only values (empty)
2341 pub mod R {}
2342 /// Write-only values (empty)
2343 pub mod W {}
2344 /// Read-write values (empty)
2345 pub mod RW {}
2346 }
2347
2348 /// Port Reset bit
2349 pub mod BR3 {
2350 /// Offset (3 bits)
2351 pub const offset: u32 = 3;
2352 /// Mask (1 bit: 1 << 3)
2353 pub const mask: u32 = 1 << offset;
2354 /// Read-only values (empty)
2355 pub mod R {}
2356 /// Write-only values (empty)
2357 pub mod W {}
2358 /// Read-write values (empty)
2359 pub mod RW {}
2360 }
2361
2362 /// Port Reset bit
2363 pub mod BR4 {
2364 /// Offset (4 bits)
2365 pub const offset: u32 = 4;
2366 /// Mask (1 bit: 1 << 4)
2367 pub const mask: u32 = 1 << offset;
2368 /// Read-only values (empty)
2369 pub mod R {}
2370 /// Write-only values (empty)
2371 pub mod W {}
2372 /// Read-write values (empty)
2373 pub mod RW {}
2374 }
2375
2376 /// Port Reset bit
2377 pub mod BR5 {
2378 /// Offset (5 bits)
2379 pub const offset: u32 = 5;
2380 /// Mask (1 bit: 1 << 5)
2381 pub const mask: u32 = 1 << offset;
2382 /// Read-only values (empty)
2383 pub mod R {}
2384 /// Write-only values (empty)
2385 pub mod W {}
2386 /// Read-write values (empty)
2387 pub mod RW {}
2388 }
2389
2390 /// Port Reset bit
2391 pub mod BR6 {
2392 /// Offset (6 bits)
2393 pub const offset: u32 = 6;
2394 /// Mask (1 bit: 1 << 6)
2395 pub const mask: u32 = 1 << offset;
2396 /// Read-only values (empty)
2397 pub mod R {}
2398 /// Write-only values (empty)
2399 pub mod W {}
2400 /// Read-write values (empty)
2401 pub mod RW {}
2402 }
2403
2404 /// Port Reset bit
2405 pub mod BR7 {
2406 /// Offset (7 bits)
2407 pub const offset: u32 = 7;
2408 /// Mask (1 bit: 1 << 7)
2409 pub const mask: u32 = 1 << offset;
2410 /// Read-only values (empty)
2411 pub mod R {}
2412 /// Write-only values (empty)
2413 pub mod W {}
2414 /// Read-write values (empty)
2415 pub mod RW {}
2416 }
2417
2418 /// Port Reset bit
2419 pub mod BR8 {
2420 /// Offset (8 bits)
2421 pub const offset: u32 = 8;
2422 /// Mask (1 bit: 1 << 8)
2423 pub const mask: u32 = 1 << offset;
2424 /// Read-only values (empty)
2425 pub mod R {}
2426 /// Write-only values (empty)
2427 pub mod W {}
2428 /// Read-write values (empty)
2429 pub mod RW {}
2430 }
2431
2432 /// Port Reset bit
2433 pub mod BR9 {
2434 /// Offset (9 bits)
2435 pub const offset: u32 = 9;
2436 /// Mask (1 bit: 1 << 9)
2437 pub const mask: u32 = 1 << offset;
2438 /// Read-only values (empty)
2439 pub mod R {}
2440 /// Write-only values (empty)
2441 pub mod W {}
2442 /// Read-write values (empty)
2443 pub mod RW {}
2444 }
2445
2446 /// Port Reset bit
2447 pub mod BR10 {
2448 /// Offset (10 bits)
2449 pub const offset: u32 = 10;
2450 /// Mask (1 bit: 1 << 10)
2451 pub const mask: u32 = 1 << offset;
2452 /// Read-only values (empty)
2453 pub mod R {}
2454 /// Write-only values (empty)
2455 pub mod W {}
2456 /// Read-write values (empty)
2457 pub mod RW {}
2458 }
2459
2460 /// Port Reset bit
2461 pub mod BR11 {
2462 /// Offset (11 bits)
2463 pub const offset: u32 = 11;
2464 /// Mask (1 bit: 1 << 11)
2465 pub const mask: u32 = 1 << offset;
2466 /// Read-only values (empty)
2467 pub mod R {}
2468 /// Write-only values (empty)
2469 pub mod W {}
2470 /// Read-write values (empty)
2471 pub mod RW {}
2472 }
2473
2474 /// Port Reset bit
2475 pub mod BR12 {
2476 /// Offset (12 bits)
2477 pub const offset: u32 = 12;
2478 /// Mask (1 bit: 1 << 12)
2479 pub const mask: u32 = 1 << offset;
2480 /// Read-only values (empty)
2481 pub mod R {}
2482 /// Write-only values (empty)
2483 pub mod W {}
2484 /// Read-write values (empty)
2485 pub mod RW {}
2486 }
2487
2488 /// Port Reset bit
2489 pub mod BR13 {
2490 /// Offset (13 bits)
2491 pub const offset: u32 = 13;
2492 /// Mask (1 bit: 1 << 13)
2493 pub const mask: u32 = 1 << offset;
2494 /// Read-only values (empty)
2495 pub mod R {}
2496 /// Write-only values (empty)
2497 pub mod W {}
2498 /// Read-write values (empty)
2499 pub mod RW {}
2500 }
2501
2502 /// Port Reset bit
2503 pub mod BR14 {
2504 /// Offset (14 bits)
2505 pub const offset: u32 = 14;
2506 /// Mask (1 bit: 1 << 14)
2507 pub const mask: u32 = 1 << offset;
2508 /// Read-only values (empty)
2509 pub mod R {}
2510 /// Write-only values (empty)
2511 pub mod W {}
2512 /// Read-write values (empty)
2513 pub mod RW {}
2514 }
2515
2516 /// Port Reset bit
2517 pub mod BR15 {
2518 /// Offset (15 bits)
2519 pub const offset: u32 = 15;
2520 /// Mask (1 bit: 1 << 15)
2521 pub const mask: u32 = 1 << offset;
2522 /// Read-only values (empty)
2523 pub mod R {}
2524 /// Write-only values (empty)
2525 pub mod W {}
2526 /// Read-write values (empty)
2527 pub mod RW {}
2528 }
2529}
2530#[repr(C)]
2531pub struct RegisterBlock {
2532 /// GPIO port mode register
2533 pub MODER: RWRegister<u32>,
2534
2535 /// GPIO port output type register
2536 pub OTYPER: RWRegister<u32>,
2537
2538 /// GPIO port output speed register
2539 pub OSPEEDR: RWRegister<u32>,
2540
2541 /// GPIO port pull-up/pull-down register
2542 pub PUPDR: RWRegister<u32>,
2543
2544 /// GPIO port input data register
2545 pub IDR: RORegister<u32>,
2546
2547 /// GPIO port output data register
2548 pub ODR: RWRegister<u32>,
2549
2550 /// GPIO port bit set/reset register
2551 pub BSRR: WORegister<u32>,
2552
2553 /// GPIO port configuration lock register
2554 pub LCKR: RWRegister<u32>,
2555
2556 /// GPIO alternate function low register
2557 pub AFRL: RWRegister<u32>,
2558
2559 /// GPIO alternate function high register
2560 pub AFRH: RWRegister<u32>,
2561
2562 /// port bit reset register
2563 pub BRR: WORegister<u32>,
2564}
2565pub struct ResetValues {
2566 pub MODER: u32,
2567 pub OTYPER: u32,
2568 pub OSPEEDR: u32,
2569 pub PUPDR: u32,
2570 pub IDR: u32,
2571 pub ODR: u32,
2572 pub BSRR: u32,
2573 pub LCKR: u32,
2574 pub AFRL: u32,
2575 pub AFRH: u32,
2576 pub BRR: u32,
2577}
2578#[cfg(not(feature = "nosync"))]
2579pub struct Instance {
2580 pub(crate) addr: u32,
2581 pub(crate) _marker: PhantomData<*const RegisterBlock>,
2582}
2583#[cfg(not(feature = "nosync"))]
2584impl ::core::ops::Deref for Instance {
2585 type Target = RegisterBlock;
2586 #[inline(always)]
2587 fn deref(&self) -> &RegisterBlock {
2588 unsafe { &*(self.addr as *const _) }
2589 }
2590}
2591#[cfg(feature = "rtic")]
2592unsafe impl Send for Instance {}
2593
2594/// Access functions for the GPIOA peripheral instance
2595pub mod GPIOA {
2596 use super::ResetValues;
2597
2598 #[cfg(not(feature = "nosync"))]
2599 use super::Instance;
2600
2601 #[cfg(not(feature = "nosync"))]
2602 const INSTANCE: Instance = Instance {
2603 addr: 0x50000000,
2604 _marker: ::core::marker::PhantomData,
2605 };
2606
2607 /// Reset values for each field in GPIOA
2608 pub const reset: ResetValues = ResetValues {
2609 MODER: 0xEBFFFFFF,
2610 OTYPER: 0x00000000,
2611 OSPEEDR: 0x0C000000,
2612 PUPDR: 0x24000000,
2613 IDR: 0x00000000,
2614 ODR: 0x00000000,
2615 BSRR: 0x00000000,
2616 LCKR: 0x00000000,
2617 AFRL: 0x00000000,
2618 AFRH: 0x00000000,
2619 BRR: 0x00000000,
2620 };
2621
2622 #[cfg(not(feature = "nosync"))]
2623 #[allow(renamed_and_removed_lints)]
2624 #[allow(private_no_mangle_statics)]
2625 #[no_mangle]
2626 static mut GPIOA_TAKEN: bool = false;
2627
2628 /// Safe access to GPIOA
2629 ///
2630 /// This function returns `Some(Instance)` if this instance is not
2631 /// currently taken, and `None` if it is. This ensures that if you
2632 /// do get `Some(Instance)`, you are ensured unique access to
2633 /// the peripheral and there cannot be data races (unless other
2634 /// code uses `unsafe`, of course). You can then pass the
2635 /// `Instance` around to other functions as required. When you're
2636 /// done with it, you can call `release(instance)` to return it.
2637 ///
2638 /// `Instance` itself dereferences to a `RegisterBlock`, which
2639 /// provides access to the peripheral's registers.
2640 #[cfg(not(feature = "nosync"))]
2641 #[inline]
2642 pub fn take() -> Option<Instance> {
2643 external_cortex_m::interrupt::free(|_| unsafe {
2644 if GPIOA_TAKEN {
2645 None
2646 } else {
2647 GPIOA_TAKEN = true;
2648 Some(INSTANCE)
2649 }
2650 })
2651 }
2652
2653 /// Release exclusive access to GPIOA
2654 ///
2655 /// This function allows you to return an `Instance` so that it
2656 /// is available to `take()` again. This function will panic if
2657 /// you return a different `Instance` or if this instance is not
2658 /// already taken.
2659 #[cfg(not(feature = "nosync"))]
2660 #[inline]
2661 pub fn release(inst: Instance) {
2662 external_cortex_m::interrupt::free(|_| unsafe {
2663 if GPIOA_TAKEN && inst.addr == INSTANCE.addr {
2664 GPIOA_TAKEN = false;
2665 } else {
2666 panic!("Released a peripheral which was not taken");
2667 }
2668 });
2669 }
2670
2671 /// Unsafely steal GPIOA
2672 ///
2673 /// This function is similar to take() but forcibly takes the
2674 /// Instance, marking it as taken irregardless of its previous
2675 /// state.
2676 #[cfg(not(feature = "nosync"))]
2677 #[inline]
2678 pub unsafe fn steal() -> Instance {
2679 GPIOA_TAKEN = true;
2680 INSTANCE
2681 }
2682}
2683
2684/// Raw pointer to GPIOA
2685///
2686/// Dereferencing this is unsafe because you are not ensured unique
2687/// access to the peripheral, so you may encounter data races with
2688/// other users of this peripheral. It is up to you to ensure you
2689/// will not cause data races.
2690///
2691/// This constant is provided for ease of use in unsafe code: you can
2692/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
2693pub const GPIOA: *const RegisterBlock = 0x50000000 as *const _;
2694
2695/// Access functions for the GPIOB peripheral instance
2696pub mod GPIOB {
2697 use super::ResetValues;
2698
2699 #[cfg(not(feature = "nosync"))]
2700 use super::Instance;
2701
2702 #[cfg(not(feature = "nosync"))]
2703 const INSTANCE: Instance = Instance {
2704 addr: 0x50000400,
2705 _marker: ::core::marker::PhantomData,
2706 };
2707
2708 /// Reset values for each field in GPIOB
2709 pub const reset: ResetValues = ResetValues {
2710 MODER: 0xFFFFFFFF,
2711 OTYPER: 0x00000000,
2712 OSPEEDR: 0x00000000,
2713 PUPDR: 0x00000000,
2714 IDR: 0x00000000,
2715 ODR: 0x00000000,
2716 BSRR: 0x00000000,
2717 LCKR: 0x00000000,
2718 AFRL: 0x00000000,
2719 AFRH: 0x00000000,
2720 BRR: 0x00000000,
2721 };
2722
2723 #[cfg(not(feature = "nosync"))]
2724 #[allow(renamed_and_removed_lints)]
2725 #[allow(private_no_mangle_statics)]
2726 #[no_mangle]
2727 static mut GPIOB_TAKEN: bool = false;
2728
2729 /// Safe access to GPIOB
2730 ///
2731 /// This function returns `Some(Instance)` if this instance is not
2732 /// currently taken, and `None` if it is. This ensures that if you
2733 /// do get `Some(Instance)`, you are ensured unique access to
2734 /// the peripheral and there cannot be data races (unless other
2735 /// code uses `unsafe`, of course). You can then pass the
2736 /// `Instance` around to other functions as required. When you're
2737 /// done with it, you can call `release(instance)` to return it.
2738 ///
2739 /// `Instance` itself dereferences to a `RegisterBlock`, which
2740 /// provides access to the peripheral's registers.
2741 #[cfg(not(feature = "nosync"))]
2742 #[inline]
2743 pub fn take() -> Option<Instance> {
2744 external_cortex_m::interrupt::free(|_| unsafe {
2745 if GPIOB_TAKEN {
2746 None
2747 } else {
2748 GPIOB_TAKEN = true;
2749 Some(INSTANCE)
2750 }
2751 })
2752 }
2753
2754 /// Release exclusive access to GPIOB
2755 ///
2756 /// This function allows you to return an `Instance` so that it
2757 /// is available to `take()` again. This function will panic if
2758 /// you return a different `Instance` or if this instance is not
2759 /// already taken.
2760 #[cfg(not(feature = "nosync"))]
2761 #[inline]
2762 pub fn release(inst: Instance) {
2763 external_cortex_m::interrupt::free(|_| unsafe {
2764 if GPIOB_TAKEN && inst.addr == INSTANCE.addr {
2765 GPIOB_TAKEN = false;
2766 } else {
2767 panic!("Released a peripheral which was not taken");
2768 }
2769 });
2770 }
2771
2772 /// Unsafely steal GPIOB
2773 ///
2774 /// This function is similar to take() but forcibly takes the
2775 /// Instance, marking it as taken irregardless of its previous
2776 /// state.
2777 #[cfg(not(feature = "nosync"))]
2778 #[inline]
2779 pub unsafe fn steal() -> Instance {
2780 GPIOB_TAKEN = true;
2781 INSTANCE
2782 }
2783}
2784
2785/// Raw pointer to GPIOB
2786///
2787/// Dereferencing this is unsafe because you are not ensured unique
2788/// access to the peripheral, so you may encounter data races with
2789/// other users of this peripheral. It is up to you to ensure you
2790/// will not cause data races.
2791///
2792/// This constant is provided for ease of use in unsafe code: you can
2793/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
2794pub const GPIOB: *const RegisterBlock = 0x50000400 as *const _;
2795
2796/// Access functions for the GPIOC peripheral instance
2797pub mod GPIOC {
2798 use super::ResetValues;
2799
2800 #[cfg(not(feature = "nosync"))]
2801 use super::Instance;
2802
2803 #[cfg(not(feature = "nosync"))]
2804 const INSTANCE: Instance = Instance {
2805 addr: 0x50000800,
2806 _marker: ::core::marker::PhantomData,
2807 };
2808
2809 /// Reset values for each field in GPIOC
2810 pub const reset: ResetValues = ResetValues {
2811 MODER: 0xFFFFFFFF,
2812 OTYPER: 0x00000000,
2813 OSPEEDR: 0x00000000,
2814 PUPDR: 0x00000000,
2815 IDR: 0x00000000,
2816 ODR: 0x00000000,
2817 BSRR: 0x00000000,
2818 LCKR: 0x00000000,
2819 AFRL: 0x00000000,
2820 AFRH: 0x00000000,
2821 BRR: 0x00000000,
2822 };
2823
2824 #[cfg(not(feature = "nosync"))]
2825 #[allow(renamed_and_removed_lints)]
2826 #[allow(private_no_mangle_statics)]
2827 #[no_mangle]
2828 static mut GPIOC_TAKEN: bool = false;
2829
2830 /// Safe access to GPIOC
2831 ///
2832 /// This function returns `Some(Instance)` if this instance is not
2833 /// currently taken, and `None` if it is. This ensures that if you
2834 /// do get `Some(Instance)`, you are ensured unique access to
2835 /// the peripheral and there cannot be data races (unless other
2836 /// code uses `unsafe`, of course). You can then pass the
2837 /// `Instance` around to other functions as required. When you're
2838 /// done with it, you can call `release(instance)` to return it.
2839 ///
2840 /// `Instance` itself dereferences to a `RegisterBlock`, which
2841 /// provides access to the peripheral's registers.
2842 #[cfg(not(feature = "nosync"))]
2843 #[inline]
2844 pub fn take() -> Option<Instance> {
2845 external_cortex_m::interrupt::free(|_| unsafe {
2846 if GPIOC_TAKEN {
2847 None
2848 } else {
2849 GPIOC_TAKEN = true;
2850 Some(INSTANCE)
2851 }
2852 })
2853 }
2854
2855 /// Release exclusive access to GPIOC
2856 ///
2857 /// This function allows you to return an `Instance` so that it
2858 /// is available to `take()` again. This function will panic if
2859 /// you return a different `Instance` or if this instance is not
2860 /// already taken.
2861 #[cfg(not(feature = "nosync"))]
2862 #[inline]
2863 pub fn release(inst: Instance) {
2864 external_cortex_m::interrupt::free(|_| unsafe {
2865 if GPIOC_TAKEN && inst.addr == INSTANCE.addr {
2866 GPIOC_TAKEN = false;
2867 } else {
2868 panic!("Released a peripheral which was not taken");
2869 }
2870 });
2871 }
2872
2873 /// Unsafely steal GPIOC
2874 ///
2875 /// This function is similar to take() but forcibly takes the
2876 /// Instance, marking it as taken irregardless of its previous
2877 /// state.
2878 #[cfg(not(feature = "nosync"))]
2879 #[inline]
2880 pub unsafe fn steal() -> Instance {
2881 GPIOC_TAKEN = true;
2882 INSTANCE
2883 }
2884}
2885
2886/// Raw pointer to GPIOC
2887///
2888/// Dereferencing this is unsafe because you are not ensured unique
2889/// access to the peripheral, so you may encounter data races with
2890/// other users of this peripheral. It is up to you to ensure you
2891/// will not cause data races.
2892///
2893/// This constant is provided for ease of use in unsafe code: you can
2894/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
2895pub const GPIOC: *const RegisterBlock = 0x50000800 as *const _;
2896
2897/// Access functions for the GPIOD peripheral instance
2898pub mod GPIOD {
2899 use super::ResetValues;
2900
2901 #[cfg(not(feature = "nosync"))]
2902 use super::Instance;
2903
2904 #[cfg(not(feature = "nosync"))]
2905 const INSTANCE: Instance = Instance {
2906 addr: 0x50000c00,
2907 _marker: ::core::marker::PhantomData,
2908 };
2909
2910 /// Reset values for each field in GPIOD
2911 pub const reset: ResetValues = ResetValues {
2912 MODER: 0xFFFFFFFF,
2913 OTYPER: 0x00000000,
2914 OSPEEDR: 0x00000000,
2915 PUPDR: 0x00000000,
2916 IDR: 0x00000000,
2917 ODR: 0x00000000,
2918 BSRR: 0x00000000,
2919 LCKR: 0x00000000,
2920 AFRL: 0x00000000,
2921 AFRH: 0x00000000,
2922 BRR: 0x00000000,
2923 };
2924
2925 #[cfg(not(feature = "nosync"))]
2926 #[allow(renamed_and_removed_lints)]
2927 #[allow(private_no_mangle_statics)]
2928 #[no_mangle]
2929 static mut GPIOD_TAKEN: bool = false;
2930
2931 /// Safe access to GPIOD
2932 ///
2933 /// This function returns `Some(Instance)` if this instance is not
2934 /// currently taken, and `None` if it is. This ensures that if you
2935 /// do get `Some(Instance)`, you are ensured unique access to
2936 /// the peripheral and there cannot be data races (unless other
2937 /// code uses `unsafe`, of course). You can then pass the
2938 /// `Instance` around to other functions as required. When you're
2939 /// done with it, you can call `release(instance)` to return it.
2940 ///
2941 /// `Instance` itself dereferences to a `RegisterBlock`, which
2942 /// provides access to the peripheral's registers.
2943 #[cfg(not(feature = "nosync"))]
2944 #[inline]
2945 pub fn take() -> Option<Instance> {
2946 external_cortex_m::interrupt::free(|_| unsafe {
2947 if GPIOD_TAKEN {
2948 None
2949 } else {
2950 GPIOD_TAKEN = true;
2951 Some(INSTANCE)
2952 }
2953 })
2954 }
2955
2956 /// Release exclusive access to GPIOD
2957 ///
2958 /// This function allows you to return an `Instance` so that it
2959 /// is available to `take()` again. This function will panic if
2960 /// you return a different `Instance` or if this instance is not
2961 /// already taken.
2962 #[cfg(not(feature = "nosync"))]
2963 #[inline]
2964 pub fn release(inst: Instance) {
2965 external_cortex_m::interrupt::free(|_| unsafe {
2966 if GPIOD_TAKEN && inst.addr == INSTANCE.addr {
2967 GPIOD_TAKEN = false;
2968 } else {
2969 panic!("Released a peripheral which was not taken");
2970 }
2971 });
2972 }
2973
2974 /// Unsafely steal GPIOD
2975 ///
2976 /// This function is similar to take() but forcibly takes the
2977 /// Instance, marking it as taken irregardless of its previous
2978 /// state.
2979 #[cfg(not(feature = "nosync"))]
2980 #[inline]
2981 pub unsafe fn steal() -> Instance {
2982 GPIOD_TAKEN = true;
2983 INSTANCE
2984 }
2985}
2986
2987/// Raw pointer to GPIOD
2988///
2989/// Dereferencing this is unsafe because you are not ensured unique
2990/// access to the peripheral, so you may encounter data races with
2991/// other users of this peripheral. It is up to you to ensure you
2992/// will not cause data races.
2993///
2994/// This constant is provided for ease of use in unsafe code: you can
2995/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
2996pub const GPIOD: *const RegisterBlock = 0x50000c00 as *const _;
2997
2998/// Access functions for the GPIOF peripheral instance
2999pub mod GPIOF {
3000 use super::ResetValues;
3001
3002 #[cfg(not(feature = "nosync"))]
3003 use super::Instance;
3004
3005 #[cfg(not(feature = "nosync"))]
3006 const INSTANCE: Instance = Instance {
3007 addr: 0x50001400,
3008 _marker: ::core::marker::PhantomData,
3009 };
3010
3011 /// Reset values for each field in GPIOF
3012 pub const reset: ResetValues = ResetValues {
3013 MODER: 0xFFFFFFFF,
3014 OTYPER: 0x00000000,
3015 OSPEEDR: 0x00000000,
3016 PUPDR: 0x00000000,
3017 IDR: 0x00000000,
3018 ODR: 0x00000000,
3019 BSRR: 0x00000000,
3020 LCKR: 0x00000000,
3021 AFRL: 0x00000000,
3022 AFRH: 0x00000000,
3023 BRR: 0x00000000,
3024 };
3025
3026 #[cfg(not(feature = "nosync"))]
3027 #[allow(renamed_and_removed_lints)]
3028 #[allow(private_no_mangle_statics)]
3029 #[no_mangle]
3030 static mut GPIOF_TAKEN: bool = false;
3031
3032 /// Safe access to GPIOF
3033 ///
3034 /// This function returns `Some(Instance)` if this instance is not
3035 /// currently taken, and `None` if it is. This ensures that if you
3036 /// do get `Some(Instance)`, you are ensured unique access to
3037 /// the peripheral and there cannot be data races (unless other
3038 /// code uses `unsafe`, of course). You can then pass the
3039 /// `Instance` around to other functions as required. When you're
3040 /// done with it, you can call `release(instance)` to return it.
3041 ///
3042 /// `Instance` itself dereferences to a `RegisterBlock`, which
3043 /// provides access to the peripheral's registers.
3044 #[cfg(not(feature = "nosync"))]
3045 #[inline]
3046 pub fn take() -> Option<Instance> {
3047 external_cortex_m::interrupt::free(|_| unsafe {
3048 if GPIOF_TAKEN {
3049 None
3050 } else {
3051 GPIOF_TAKEN = true;
3052 Some(INSTANCE)
3053 }
3054 })
3055 }
3056
3057 /// Release exclusive access to GPIOF
3058 ///
3059 /// This function allows you to return an `Instance` so that it
3060 /// is available to `take()` again. This function will panic if
3061 /// you return a different `Instance` or if this instance is not
3062 /// already taken.
3063 #[cfg(not(feature = "nosync"))]
3064 #[inline]
3065 pub fn release(inst: Instance) {
3066 external_cortex_m::interrupt::free(|_| unsafe {
3067 if GPIOF_TAKEN && inst.addr == INSTANCE.addr {
3068 GPIOF_TAKEN = false;
3069 } else {
3070 panic!("Released a peripheral which was not taken");
3071 }
3072 });
3073 }
3074
3075 /// Unsafely steal GPIOF
3076 ///
3077 /// This function is similar to take() but forcibly takes the
3078 /// Instance, marking it as taken irregardless of its previous
3079 /// state.
3080 #[cfg(not(feature = "nosync"))]
3081 #[inline]
3082 pub unsafe fn steal() -> Instance {
3083 GPIOF_TAKEN = true;
3084 INSTANCE
3085 }
3086}
3087
3088/// Raw pointer to GPIOF
3089///
3090/// Dereferencing this is unsafe because you are not ensured unique
3091/// access to the peripheral, so you may encounter data races with
3092/// other users of this peripheral. It is up to you to ensure you
3093/// will not cause data races.
3094///
3095/// This constant is provided for ease of use in unsafe code: you can
3096/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
3097pub const GPIOF: *const RegisterBlock = 0x50001400 as *const _;