stm32ral/stm32g0/stm32g07x/adc.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Analog to Digital Converter instance 1
4
5use crate::{RORegister, RWRegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// ADC interrupt and status register
10pub mod ISR {
11
12 /// Channel Configuration Ready flag
13 pub mod CCRDY {
14 /// Offset (13 bits)
15 pub const offset: u32 = 13;
16 /// Mask (1 bit: 1 << 13)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25
26 /// End Of Calibration flag
27 pub mod EOCAL {
28 /// Offset (11 bits)
29 pub const offset: u32 = 11;
30 /// Mask (1 bit: 1 << 11)
31 pub const mask: u32 = 1 << offset;
32 /// Read-only values (empty)
33 pub mod R {}
34 /// Write-only values (empty)
35 pub mod W {}
36 /// Read-write values (empty)
37 pub mod RW {}
38 }
39
40 /// ADC analog watchdog 3 flag
41 pub mod AWD3 {
42 /// Offset (9 bits)
43 pub const offset: u32 = 9;
44 /// Mask (1 bit: 1 << 9)
45 pub const mask: u32 = 1 << offset;
46 /// Read-only values (empty)
47 pub mod R {}
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53
54 /// ADC analog watchdog 2 flag
55 pub mod AWD2 {
56 /// Offset (8 bits)
57 pub const offset: u32 = 8;
58 /// Mask (1 bit: 1 << 8)
59 pub const mask: u32 = 1 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// ADC analog watchdog 1 flag
69 pub mod AWD1 {
70 /// Offset (7 bits)
71 pub const offset: u32 = 7;
72 /// Mask (1 bit: 1 << 7)
73 pub const mask: u32 = 1 << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// ADC group regular overrun flag
83 pub mod OVR {
84 /// Offset (4 bits)
85 pub const offset: u32 = 4;
86 /// Mask (1 bit: 1 << 4)
87 pub const mask: u32 = 1 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 /// Read-write values (empty)
93 pub mod RW {}
94 }
95
96 /// ADC group regular end of sequence conversions flag
97 pub mod EOS {
98 /// Offset (3 bits)
99 pub const offset: u32 = 3;
100 /// Mask (1 bit: 1 << 3)
101 pub const mask: u32 = 1 << offset;
102 /// Read-only values (empty)
103 pub mod R {}
104 /// Write-only values (empty)
105 pub mod W {}
106 /// Read-write values (empty)
107 pub mod RW {}
108 }
109
110 /// ADC group regular end of unitary conversion flag
111 pub mod EOC {
112 /// Offset (2 bits)
113 pub const offset: u32 = 2;
114 /// Mask (1 bit: 1 << 2)
115 pub const mask: u32 = 1 << offset;
116 /// Read-only values (empty)
117 pub mod R {}
118 /// Write-only values (empty)
119 pub mod W {}
120 /// Read-write values (empty)
121 pub mod RW {}
122 }
123
124 /// ADC group regular end of sampling flag
125 pub mod EOSMP {
126 /// Offset (1 bits)
127 pub const offset: u32 = 1;
128 /// Mask (1 bit: 1 << 1)
129 pub const mask: u32 = 1 << offset;
130 /// Read-only values (empty)
131 pub mod R {}
132 /// Write-only values (empty)
133 pub mod W {}
134 /// Read-write values (empty)
135 pub mod RW {}
136 }
137
138 /// ADC ready flag
139 pub mod ADRDY {
140 /// Offset (0 bits)
141 pub const offset: u32 = 0;
142 /// Mask (1 bit: 1 << 0)
143 pub const mask: u32 = 1 << offset;
144 /// Read-only values (empty)
145 pub mod R {}
146 /// Write-only values (empty)
147 pub mod W {}
148 /// Read-write values (empty)
149 pub mod RW {}
150 }
151}
152
153/// ADC interrupt enable register
154pub mod IER {
155
156 /// Channel Configuration Ready Interrupt enable
157 pub mod CCRDYIE {
158 /// Offset (13 bits)
159 pub const offset: u32 = 13;
160 /// Mask (1 bit: 1 << 13)
161 pub const mask: u32 = 1 << offset;
162 /// Read-only values (empty)
163 pub mod R {}
164 /// Write-only values (empty)
165 pub mod W {}
166 /// Read-write values (empty)
167 pub mod RW {}
168 }
169
170 /// End of calibration interrupt enable
171 pub mod EOCALIE {
172 /// Offset (11 bits)
173 pub const offset: u32 = 11;
174 /// Mask (1 bit: 1 << 11)
175 pub const mask: u32 = 1 << offset;
176 /// Read-only values (empty)
177 pub mod R {}
178 /// Write-only values (empty)
179 pub mod W {}
180 /// Read-write values (empty)
181 pub mod RW {}
182 }
183
184 /// ADC analog watchdog 3 interrupt
185 pub mod AWD3IE {
186 /// Offset (9 bits)
187 pub const offset: u32 = 9;
188 /// Mask (1 bit: 1 << 9)
189 pub const mask: u32 = 1 << offset;
190 /// Read-only values (empty)
191 pub mod R {}
192 /// Write-only values (empty)
193 pub mod W {}
194 /// Read-write values (empty)
195 pub mod RW {}
196 }
197
198 /// ADC analog watchdog 2 interrupt
199 pub mod AWD2IE {
200 /// Offset (8 bits)
201 pub const offset: u32 = 8;
202 /// Mask (1 bit: 1 << 8)
203 pub const mask: u32 = 1 << offset;
204 /// Read-only values (empty)
205 pub mod R {}
206 /// Write-only values (empty)
207 pub mod W {}
208 /// Read-write values (empty)
209 pub mod RW {}
210 }
211
212 /// ADC analog watchdog 1 interrupt
213 pub mod AWD1IE {
214 /// Offset (7 bits)
215 pub const offset: u32 = 7;
216 /// Mask (1 bit: 1 << 7)
217 pub const mask: u32 = 1 << offset;
218 /// Read-only values (empty)
219 pub mod R {}
220 /// Write-only values (empty)
221 pub mod W {}
222 /// Read-write values (empty)
223 pub mod RW {}
224 }
225
226 /// ADC group regular overrun interrupt
227 pub mod OVRIE {
228 /// Offset (4 bits)
229 pub const offset: u32 = 4;
230 /// Mask (1 bit: 1 << 4)
231 pub const mask: u32 = 1 << offset;
232 /// Read-only values (empty)
233 pub mod R {}
234 /// Write-only values (empty)
235 pub mod W {}
236 /// Read-write values (empty)
237 pub mod RW {}
238 }
239
240 /// ADC group regular end of sequence conversions interrupt
241 pub mod EOSIE {
242 /// Offset (3 bits)
243 pub const offset: u32 = 3;
244 /// Mask (1 bit: 1 << 3)
245 pub const mask: u32 = 1 << offset;
246 /// Read-only values (empty)
247 pub mod R {}
248 /// Write-only values (empty)
249 pub mod W {}
250 /// Read-write values (empty)
251 pub mod RW {}
252 }
253
254 /// ADC group regular end of unitary conversion interrupt
255 pub mod EOCIE {
256 /// Offset (2 bits)
257 pub const offset: u32 = 2;
258 /// Mask (1 bit: 1 << 2)
259 pub const mask: u32 = 1 << offset;
260 /// Read-only values (empty)
261 pub mod R {}
262 /// Write-only values (empty)
263 pub mod W {}
264 /// Read-write values (empty)
265 pub mod RW {}
266 }
267
268 /// ADC group regular end of sampling interrupt
269 pub mod EOSMPIE {
270 /// Offset (1 bits)
271 pub const offset: u32 = 1;
272 /// Mask (1 bit: 1 << 1)
273 pub const mask: u32 = 1 << offset;
274 /// Read-only values (empty)
275 pub mod R {}
276 /// Write-only values (empty)
277 pub mod W {}
278 /// Read-write values (empty)
279 pub mod RW {}
280 }
281
282 /// ADC ready interrupt
283 pub mod ADRDYIE {
284 /// Offset (0 bits)
285 pub const offset: u32 = 0;
286 /// Mask (1 bit: 1 << 0)
287 pub const mask: u32 = 1 << offset;
288 /// Read-only values (empty)
289 pub mod R {}
290 /// Write-only values (empty)
291 pub mod W {}
292 /// Read-write values (empty)
293 pub mod RW {}
294 }
295}
296
297/// ADC control register
298pub mod CR {
299
300 /// ADC calibration
301 pub mod ADCAL {
302 /// Offset (31 bits)
303 pub const offset: u32 = 31;
304 /// Mask (1 bit: 1 << 31)
305 pub const mask: u32 = 1 << offset;
306 /// Read-only values (empty)
307 pub mod R {}
308 /// Write-only values (empty)
309 pub mod W {}
310 /// Read-write values (empty)
311 pub mod RW {}
312 }
313
314 /// ADC voltage regulator enable
315 pub mod ADVREGEN {
316 /// Offset (28 bits)
317 pub const offset: u32 = 28;
318 /// Mask (1 bit: 1 << 28)
319 pub const mask: u32 = 1 << offset;
320 /// Read-only values (empty)
321 pub mod R {}
322 /// Write-only values (empty)
323 pub mod W {}
324 /// Read-write values (empty)
325 pub mod RW {}
326 }
327
328 /// ADC group regular conversion stop
329 pub mod ADSTP {
330 /// Offset (4 bits)
331 pub const offset: u32 = 4;
332 /// Mask (1 bit: 1 << 4)
333 pub const mask: u32 = 1 << offset;
334 /// Read-only values (empty)
335 pub mod R {}
336 /// Write-only values (empty)
337 pub mod W {}
338 /// Read-write values (empty)
339 pub mod RW {}
340 }
341
342 /// ADC group regular conversion start
343 pub mod ADSTART {
344 /// Offset (2 bits)
345 pub const offset: u32 = 2;
346 /// Mask (1 bit: 1 << 2)
347 pub const mask: u32 = 1 << offset;
348 /// Read-only values (empty)
349 pub mod R {}
350 /// Write-only values (empty)
351 pub mod W {}
352 /// Read-write values (empty)
353 pub mod RW {}
354 }
355
356 /// ADC disable
357 pub mod ADDIS {
358 /// Offset (1 bits)
359 pub const offset: u32 = 1;
360 /// Mask (1 bit: 1 << 1)
361 pub const mask: u32 = 1 << offset;
362 /// Read-only values (empty)
363 pub mod R {}
364 /// Write-only values (empty)
365 pub mod W {}
366 /// Read-write values (empty)
367 pub mod RW {}
368 }
369
370 /// ADC enable
371 pub mod ADEN {
372 /// Offset (0 bits)
373 pub const offset: u32 = 0;
374 /// Mask (1 bit: 1 << 0)
375 pub const mask: u32 = 1 << offset;
376 /// Read-only values (empty)
377 pub mod R {}
378 /// Write-only values (empty)
379 pub mod W {}
380 /// Read-write values (empty)
381 pub mod RW {}
382 }
383}
384
385/// ADC configuration register 1
386pub mod CFGR1 {
387
388 /// ADC analog watchdog 1 monitored channel selection
389 pub mod AWDCH1CH {
390 /// Offset (26 bits)
391 pub const offset: u32 = 26;
392 /// Mask (5 bits: 0b11111 << 26)
393 pub const mask: u32 = 0b11111 << offset;
394 /// Read-only values (empty)
395 pub mod R {}
396 /// Write-only values (empty)
397 pub mod W {}
398 /// Read-write values (empty)
399 pub mod RW {}
400 }
401
402 /// ADC analog watchdog 1 enable on scope ADC group regular
403 pub mod AWD1EN {
404 /// Offset (23 bits)
405 pub const offset: u32 = 23;
406 /// Mask (1 bit: 1 << 23)
407 pub const mask: u32 = 1 << offset;
408 /// Read-only values (empty)
409 pub mod R {}
410 /// Write-only values (empty)
411 pub mod W {}
412 /// Read-write values (empty)
413 pub mod RW {}
414 }
415
416 /// ADC analog watchdog 1 monitoring a single channel or all channels
417 pub mod AWD1SGL {
418 /// Offset (22 bits)
419 pub const offset: u32 = 22;
420 /// Mask (1 bit: 1 << 22)
421 pub const mask: u32 = 1 << offset;
422 /// Read-only values (empty)
423 pub mod R {}
424 /// Write-only values (empty)
425 pub mod W {}
426 /// Read-write values (empty)
427 pub mod RW {}
428 }
429
430 /// Mode selection of the ADC_CHSELR register
431 pub mod CHSELRMOD {
432 /// Offset (21 bits)
433 pub const offset: u32 = 21;
434 /// Mask (1 bit: 1 << 21)
435 pub const mask: u32 = 1 << offset;
436 /// Read-only values (empty)
437 pub mod R {}
438 /// Write-only values (empty)
439 pub mod W {}
440 /// Read-write values (empty)
441 pub mod RW {}
442 }
443
444 /// ADC group regular sequencer discontinuous mode
445 pub mod DISCEN {
446 /// Offset (16 bits)
447 pub const offset: u32 = 16;
448 /// Mask (1 bit: 1 << 16)
449 pub const mask: u32 = 1 << offset;
450 /// Read-only values (empty)
451 pub mod R {}
452 /// Write-only values (empty)
453 pub mod W {}
454 /// Read-write values (empty)
455 pub mod RW {}
456 }
457
458 /// Auto-off mode
459 pub mod AUTOFF {
460 /// Offset (15 bits)
461 pub const offset: u32 = 15;
462 /// Mask (1 bit: 1 << 15)
463 pub const mask: u32 = 1 << offset;
464 /// Read-only values (empty)
465 pub mod R {}
466 /// Write-only values (empty)
467 pub mod W {}
468 /// Read-write values (empty)
469 pub mod RW {}
470 }
471
472 /// Wait conversion mode
473 pub mod WAIT {
474 /// Offset (14 bits)
475 pub const offset: u32 = 14;
476 /// Mask (1 bit: 1 << 14)
477 pub const mask: u32 = 1 << offset;
478 /// Read-only values (empty)
479 pub mod R {}
480 /// Write-only values (empty)
481 pub mod W {}
482 /// Read-write values (empty)
483 pub mod RW {}
484 }
485
486 /// ADC group regular continuous conversion mode
487 pub mod CONT {
488 /// Offset (13 bits)
489 pub const offset: u32 = 13;
490 /// Mask (1 bit: 1 << 13)
491 pub const mask: u32 = 1 << offset;
492 /// Read-only values (empty)
493 pub mod R {}
494 /// Write-only values (empty)
495 pub mod W {}
496 /// Read-write values (empty)
497 pub mod RW {}
498 }
499
500 /// ADC group regular overrun configuration
501 pub mod OVRMOD {
502 /// Offset (12 bits)
503 pub const offset: u32 = 12;
504 /// Mask (1 bit: 1 << 12)
505 pub const mask: u32 = 1 << offset;
506 /// Read-only values (empty)
507 pub mod R {}
508 /// Write-only values (empty)
509 pub mod W {}
510 /// Read-write values (empty)
511 pub mod RW {}
512 }
513
514 /// ADC group regular external trigger polarity
515 pub mod EXTEN {
516 /// Offset (10 bits)
517 pub const offset: u32 = 10;
518 /// Mask (2 bits: 0b11 << 10)
519 pub const mask: u32 = 0b11 << offset;
520 /// Read-only values (empty)
521 pub mod R {}
522 /// Write-only values (empty)
523 pub mod W {}
524 /// Read-write values (empty)
525 pub mod RW {}
526 }
527
528 /// ADC group regular external trigger source
529 pub mod EXTSEL {
530 /// Offset (6 bits)
531 pub const offset: u32 = 6;
532 /// Mask (3 bits: 0b111 << 6)
533 pub const mask: u32 = 0b111 << offset;
534 /// Read-only values (empty)
535 pub mod R {}
536 /// Write-only values (empty)
537 pub mod W {}
538 /// Read-write values (empty)
539 pub mod RW {}
540 }
541
542 /// ADC data alignement
543 pub mod ALIGN {
544 /// Offset (5 bits)
545 pub const offset: u32 = 5;
546 /// Mask (1 bit: 1 << 5)
547 pub const mask: u32 = 1 << offset;
548 /// Read-only values (empty)
549 pub mod R {}
550 /// Write-only values (empty)
551 pub mod W {}
552 /// Read-write values (empty)
553 pub mod RW {}
554 }
555
556 /// ADC data resolution
557 pub mod RES {
558 /// Offset (3 bits)
559 pub const offset: u32 = 3;
560 /// Mask (2 bits: 0b11 << 3)
561 pub const mask: u32 = 0b11 << offset;
562 /// Read-only values (empty)
563 pub mod R {}
564 /// Write-only values (empty)
565 pub mod W {}
566 /// Read-write values (empty)
567 pub mod RW {}
568 }
569
570 /// Scan sequence direction
571 pub mod SCANDIR {
572 /// Offset (2 bits)
573 pub const offset: u32 = 2;
574 /// Mask (1 bit: 1 << 2)
575 pub const mask: u32 = 1 << offset;
576 /// Read-only values (empty)
577 pub mod R {}
578 /// Write-only values (empty)
579 pub mod W {}
580 /// Read-write values (empty)
581 pub mod RW {}
582 }
583
584 /// ADC DMA transfer configuration
585 pub mod DMACFG {
586 /// Offset (1 bits)
587 pub const offset: u32 = 1;
588 /// Mask (1 bit: 1 << 1)
589 pub const mask: u32 = 1 << offset;
590 /// Read-only values (empty)
591 pub mod R {}
592 /// Write-only values (empty)
593 pub mod W {}
594 /// Read-write values (empty)
595 pub mod RW {}
596 }
597
598 /// ADC DMA transfer enable
599 pub mod DMAEN {
600 /// Offset (0 bits)
601 pub const offset: u32 = 0;
602 /// Mask (1 bit: 1 << 0)
603 pub const mask: u32 = 1 << offset;
604 /// Read-only values (empty)
605 pub mod R {}
606 /// Write-only values (empty)
607 pub mod W {}
608 /// Read-write values (empty)
609 pub mod RW {}
610 }
611}
612
613/// ADC configuration register 2
614pub mod CFGR2 {
615
616 /// ADC clock mode
617 pub mod CKMODE {
618 /// Offset (30 bits)
619 pub const offset: u32 = 30;
620 /// Mask (2 bits: 0b11 << 30)
621 pub const mask: u32 = 0b11 << offset;
622 /// Read-only values (empty)
623 pub mod R {}
624 /// Write-only values (empty)
625 pub mod W {}
626 /// Read-write values (empty)
627 pub mod RW {}
628 }
629
630 /// Low frequency trigger mode enable
631 pub mod LFTRIG {
632 /// Offset (29 bits)
633 pub const offset: u32 = 29;
634 /// Mask (1 bit: 1 << 29)
635 pub const mask: u32 = 1 << offset;
636 /// Read-only values (empty)
637 pub mod R {}
638 /// Write-only values (empty)
639 pub mod W {}
640 /// Read-write values (empty)
641 pub mod RW {}
642 }
643
644 /// ADC oversampling discontinuous mode (triggered mode) for ADC group regular
645 pub mod TOVS {
646 /// Offset (9 bits)
647 pub const offset: u32 = 9;
648 /// Mask (1 bit: 1 << 9)
649 pub const mask: u32 = 1 << offset;
650 /// Read-only values (empty)
651 pub mod R {}
652 /// Write-only values (empty)
653 pub mod W {}
654 /// Read-write values (empty)
655 pub mod RW {}
656 }
657
658 /// ADC oversampling shift
659 pub mod OVSS {
660 /// Offset (5 bits)
661 pub const offset: u32 = 5;
662 /// Mask (4 bits: 0b1111 << 5)
663 pub const mask: u32 = 0b1111 << offset;
664 /// Read-only values (empty)
665 pub mod R {}
666 /// Write-only values (empty)
667 pub mod W {}
668 /// Read-write values (empty)
669 pub mod RW {}
670 }
671
672 /// ADC oversampling ratio
673 pub mod OVSR {
674 /// Offset (2 bits)
675 pub const offset: u32 = 2;
676 /// Mask (3 bits: 0b111 << 2)
677 pub const mask: u32 = 0b111 << offset;
678 /// Read-only values (empty)
679 pub mod R {}
680 /// Write-only values (empty)
681 pub mod W {}
682 /// Read-write values (empty)
683 pub mod RW {}
684 }
685
686 /// ADC oversampler enable on scope ADC group regular
687 pub mod OVSE {
688 /// Offset (0 bits)
689 pub const offset: u32 = 0;
690 /// Mask (1 bit: 1 << 0)
691 pub const mask: u32 = 1 << offset;
692 /// Read-only values (empty)
693 pub mod R {}
694 /// Write-only values (empty)
695 pub mod W {}
696 /// Read-write values (empty)
697 pub mod RW {}
698 }
699}
700
701/// ADC sampling time register
702pub mod SMPR {
703
704 /// Sampling time selection
705 pub mod SMP1 {
706 /// Offset (0 bits)
707 pub const offset: u32 = 0;
708 /// Mask (3 bits: 0b111 << 0)
709 pub const mask: u32 = 0b111 << offset;
710 /// Read-only values (empty)
711 pub mod R {}
712 /// Write-only values (empty)
713 pub mod W {}
714 /// Read-write values (empty)
715 pub mod RW {}
716 }
717
718 /// Sampling time selection
719 pub mod SMP2 {
720 /// Offset (4 bits)
721 pub const offset: u32 = 4;
722 /// Mask (3 bits: 0b111 << 4)
723 pub const mask: u32 = 0b111 << offset;
724 /// Read-only values (empty)
725 pub mod R {}
726 /// Write-only values (empty)
727 pub mod W {}
728 /// Read-write values (empty)
729 pub mod RW {}
730 }
731
732 /// Channel sampling time selection
733 pub mod SMPSEL {
734 /// Offset (8 bits)
735 pub const offset: u32 = 8;
736 /// Mask (19 bits: 0x7ffff << 8)
737 pub const mask: u32 = 0x7ffff << offset;
738 /// Read-only values (empty)
739 pub mod R {}
740 /// Write-only values (empty)
741 pub mod W {}
742 /// Read-write values (empty)
743 pub mod RW {}
744 }
745}
746
747/// watchdog threshold register
748pub mod AWD1TR {
749
750 /// ADC analog watchdog 1 threshold high
751 pub mod HT1 {
752 /// Offset (16 bits)
753 pub const offset: u32 = 16;
754 /// Mask (12 bits: 0xfff << 16)
755 pub const mask: u32 = 0xfff << offset;
756 /// Read-only values (empty)
757 pub mod R {}
758 /// Write-only values (empty)
759 pub mod W {}
760 /// Read-write values (empty)
761 pub mod RW {}
762 }
763
764 /// ADC analog watchdog 1 threshold low
765 pub mod LT1 {
766 /// Offset (0 bits)
767 pub const offset: u32 = 0;
768 /// Mask (12 bits: 0xfff << 0)
769 pub const mask: u32 = 0xfff << offset;
770 /// Read-only values (empty)
771 pub mod R {}
772 /// Write-only values (empty)
773 pub mod W {}
774 /// Read-write values (empty)
775 pub mod RW {}
776 }
777}
778
779/// watchdog threshold register
780pub mod AWD2TR {
781
782 /// ADC analog watchdog 2 threshold high
783 pub mod HT2 {
784 /// Offset (16 bits)
785 pub const offset: u32 = 16;
786 /// Mask (12 bits: 0xfff << 16)
787 pub const mask: u32 = 0xfff << offset;
788 /// Read-only values (empty)
789 pub mod R {}
790 /// Write-only values (empty)
791 pub mod W {}
792 /// Read-write values (empty)
793 pub mod RW {}
794 }
795
796 /// ADC analog watchdog 2 threshold low
797 pub mod LT2 {
798 /// Offset (0 bits)
799 pub const offset: u32 = 0;
800 /// Mask (12 bits: 0xfff << 0)
801 pub const mask: u32 = 0xfff << offset;
802 /// Read-only values (empty)
803 pub mod R {}
804 /// Write-only values (empty)
805 pub mod W {}
806 /// Read-write values (empty)
807 pub mod RW {}
808 }
809}
810
811/// CHSELR and CHSELR_1
812/// CHSELR: channel selection register
813/// CHSELR_1: channel selection register CHSELRMOD = 1 in ADC_CFGR1
814pub mod CHSELR {
815
816 /// Channel-x selection
817 pub mod CHSEL {
818 /// Offset (0 bits)
819 pub const offset: u32 = 0;
820 /// Mask (19 bits: 0x7ffff << 0)
821 pub const mask: u32 = 0x7ffff << offset;
822 /// Read-only values (empty)
823 pub mod R {}
824 /// Write-only values (empty)
825 pub mod W {}
826 /// Read-write values (empty)
827 pub mod RW {}
828 }
829
830 /// conversion of the sequence
831 pub mod SQ1 {
832 /// Offset (0 bits)
833 pub const offset: u32 = 0;
834 /// Mask (4 bits: 0b1111 << 0)
835 pub const mask: u32 = 0b1111 << offset;
836 /// Read-only values (empty)
837 pub mod R {}
838 /// Write-only values (empty)
839 pub mod W {}
840 /// Read-write values (empty)
841 pub mod RW {}
842 }
843
844 /// conversion of the sequence
845 pub mod SQ2 {
846 /// Offset (4 bits)
847 pub const offset: u32 = 4;
848 /// Mask (4 bits: 0b1111 << 4)
849 pub const mask: u32 = 0b1111 << offset;
850 /// Read-only values (empty)
851 pub mod R {}
852 /// Write-only values (empty)
853 pub mod W {}
854 /// Read-write values (empty)
855 pub mod RW {}
856 }
857
858 /// conversion of the sequence
859 pub mod SQ3 {
860 /// Offset (8 bits)
861 pub const offset: u32 = 8;
862 /// Mask (4 bits: 0b1111 << 8)
863 pub const mask: u32 = 0b1111 << offset;
864 /// Read-only values (empty)
865 pub mod R {}
866 /// Write-only values (empty)
867 pub mod W {}
868 /// Read-write values (empty)
869 pub mod RW {}
870 }
871
872 /// conversion of the sequence
873 pub mod SQ4 {
874 /// Offset (12 bits)
875 pub const offset: u32 = 12;
876 /// Mask (4 bits: 0b1111 << 12)
877 pub const mask: u32 = 0b1111 << offset;
878 /// Read-only values (empty)
879 pub mod R {}
880 /// Write-only values (empty)
881 pub mod W {}
882 /// Read-write values (empty)
883 pub mod RW {}
884 }
885
886 /// conversion of the sequence
887 pub mod SQ5 {
888 /// Offset (16 bits)
889 pub const offset: u32 = 16;
890 /// Mask (4 bits: 0b1111 << 16)
891 pub const mask: u32 = 0b1111 << offset;
892 /// Read-only values (empty)
893 pub mod R {}
894 /// Write-only values (empty)
895 pub mod W {}
896 /// Read-write values (empty)
897 pub mod RW {}
898 }
899
900 /// conversion of the sequence
901 pub mod SQ6 {
902 /// Offset (20 bits)
903 pub const offset: u32 = 20;
904 /// Mask (4 bits: 0b1111 << 20)
905 pub const mask: u32 = 0b1111 << offset;
906 /// Read-only values (empty)
907 pub mod R {}
908 /// Write-only values (empty)
909 pub mod W {}
910 /// Read-write values (empty)
911 pub mod RW {}
912 }
913
914 /// conversion of the sequence
915 pub mod SQ7 {
916 /// Offset (24 bits)
917 pub const offset: u32 = 24;
918 /// Mask (4 bits: 0b1111 << 24)
919 pub const mask: u32 = 0b1111 << offset;
920 /// Read-only values (empty)
921 pub mod R {}
922 /// Write-only values (empty)
923 pub mod W {}
924 /// Read-write values (empty)
925 pub mod RW {}
926 }
927
928 /// conversion of the sequence
929 pub mod SQ8 {
930 /// Offset (28 bits)
931 pub const offset: u32 = 28;
932 /// Mask (4 bits: 0b1111 << 28)
933 pub const mask: u32 = 0b1111 << offset;
934 /// Read-only values (empty)
935 pub mod R {}
936 /// Write-only values (empty)
937 pub mod W {}
938 /// Read-write values (empty)
939 pub mod RW {}
940 }
941}
942
943/// watchdog threshold register
944pub mod AWD3TR {
945
946 /// ADC analog watchdog 3 threshold high
947 pub mod HT3 {
948 /// Offset (16 bits)
949 pub const offset: u32 = 16;
950 /// Mask (12 bits: 0xfff << 16)
951 pub const mask: u32 = 0xfff << offset;
952 /// Read-only values (empty)
953 pub mod R {}
954 /// Write-only values (empty)
955 pub mod W {}
956 /// Read-write values (empty)
957 pub mod RW {}
958 }
959
960 /// ADC analog watchdog 3 threshold high
961 pub mod LT3 {
962 /// Offset (0 bits)
963 pub const offset: u32 = 0;
964 /// Mask (12 bits: 0xfff << 0)
965 pub const mask: u32 = 0xfff << offset;
966 /// Read-only values (empty)
967 pub mod R {}
968 /// Write-only values (empty)
969 pub mod W {}
970 /// Read-write values (empty)
971 pub mod RW {}
972 }
973}
974
975/// ADC group regular conversion data register
976pub mod DR {
977
978 /// ADC group regular conversion data
979 pub mod regularDATA {
980 /// Offset (0 bits)
981 pub const offset: u32 = 0;
982 /// Mask (16 bits: 0xffff << 0)
983 pub const mask: u32 = 0xffff << offset;
984 /// Read-only values (empty)
985 pub mod R {}
986 /// Write-only values (empty)
987 pub mod W {}
988 /// Read-write values (empty)
989 pub mod RW {}
990 }
991}
992
993/// ADC analog watchdog 2 configuration register
994pub mod AWD2CR {
995
996 /// ADC analog watchdog 2 monitored channel selection
997 pub mod AWD2CH {
998 /// Offset (0 bits)
999 pub const offset: u32 = 0;
1000 /// Mask (19 bits: 0x7ffff << 0)
1001 pub const mask: u32 = 0x7ffff << offset;
1002 /// Read-only values (empty)
1003 pub mod R {}
1004 /// Write-only values (empty)
1005 pub mod W {}
1006 /// Read-write values (empty)
1007 pub mod RW {}
1008 }
1009}
1010
1011/// ADC analog watchdog 3 configuration register
1012pub mod AWD3CR {
1013
1014 /// ADC analog watchdog 3 monitored channel selection
1015 pub mod AWD3CH {
1016 /// Offset (0 bits)
1017 pub const offset: u32 = 0;
1018 /// Mask (19 bits: 0x7ffff << 0)
1019 pub const mask: u32 = 0x7ffff << offset;
1020 /// Read-only values (empty)
1021 pub mod R {}
1022 /// Write-only values (empty)
1023 pub mod W {}
1024 /// Read-write values (empty)
1025 pub mod RW {}
1026 }
1027}
1028
1029/// ADC calibration factors register
1030pub mod CALFACT {
1031
1032 /// ADC calibration factor in single-ended mode
1033 pub mod CALFACT {
1034 /// Offset (0 bits)
1035 pub const offset: u32 = 0;
1036 /// Mask (7 bits: 0x7f << 0)
1037 pub const mask: u32 = 0x7f << offset;
1038 /// Read-only values (empty)
1039 pub mod R {}
1040 /// Write-only values (empty)
1041 pub mod W {}
1042 /// Read-write values (empty)
1043 pub mod RW {}
1044 }
1045}
1046
1047/// ADC common control register
1048pub mod CCR {
1049
1050 /// ADC prescaler
1051 pub mod PRESC {
1052 /// Offset (18 bits)
1053 pub const offset: u32 = 18;
1054 /// Mask (4 bits: 0b1111 << 18)
1055 pub const mask: u32 = 0b1111 << offset;
1056 /// Read-only values (empty)
1057 pub mod R {}
1058 /// Write-only values (empty)
1059 pub mod W {}
1060 /// Read-write values (empty)
1061 pub mod RW {}
1062 }
1063
1064 /// VREFINT enable
1065 pub mod VREFEN {
1066 /// Offset (22 bits)
1067 pub const offset: u32 = 22;
1068 /// Mask (1 bit: 1 << 22)
1069 pub const mask: u32 = 1 << offset;
1070 /// Read-only values (empty)
1071 pub mod R {}
1072 /// Write-only values (empty)
1073 pub mod W {}
1074 /// Read-write values (empty)
1075 pub mod RW {}
1076 }
1077
1078 /// Temperature sensor enable
1079 pub mod TSEN {
1080 /// Offset (23 bits)
1081 pub const offset: u32 = 23;
1082 /// Mask (1 bit: 1 << 23)
1083 pub const mask: u32 = 1 << offset;
1084 /// Read-only values (empty)
1085 pub mod R {}
1086 /// Write-only values (empty)
1087 pub mod W {}
1088 /// Read-write values (empty)
1089 pub mod RW {}
1090 }
1091
1092 /// VBAT enable
1093 pub mod VBATEN {
1094 /// Offset (24 bits)
1095 pub const offset: u32 = 24;
1096 /// Mask (1 bit: 1 << 24)
1097 pub const mask: u32 = 1 << offset;
1098 /// Read-only values (empty)
1099 pub mod R {}
1100 /// Write-only values (empty)
1101 pub mod W {}
1102 /// Read-write values (empty)
1103 pub mod RW {}
1104 }
1105}
1106
1107/// Hardware Configuration Register
1108pub mod HWCFGR6 {
1109
1110 /// Input channel mapping
1111 pub mod CHMAP20 {
1112 /// Offset (0 bits)
1113 pub const offset: u32 = 0;
1114 /// Mask (5 bits: 0b11111 << 0)
1115 pub const mask: u32 = 0b11111 << offset;
1116 /// Read-only values (empty)
1117 pub mod R {}
1118 /// Write-only values (empty)
1119 pub mod W {}
1120 /// Read-write values (empty)
1121 pub mod RW {}
1122 }
1123
1124 /// Input channel mapping
1125 pub mod CHMAP21 {
1126 /// Offset (8 bits)
1127 pub const offset: u32 = 8;
1128 /// Mask (5 bits: 0b11111 << 8)
1129 pub const mask: u32 = 0b11111 << offset;
1130 /// Read-only values (empty)
1131 pub mod R {}
1132 /// Write-only values (empty)
1133 pub mod W {}
1134 /// Read-write values (empty)
1135 pub mod RW {}
1136 }
1137
1138 /// Input channel mapping
1139 pub mod CHMAP22 {
1140 /// Offset (16 bits)
1141 pub const offset: u32 = 16;
1142 /// Mask (5 bits: 0b11111 << 16)
1143 pub const mask: u32 = 0b11111 << offset;
1144 /// Read-only values (empty)
1145 pub mod R {}
1146 /// Write-only values (empty)
1147 pub mod W {}
1148 /// Read-write values (empty)
1149 pub mod RW {}
1150 }
1151
1152 /// Input channel mapping
1153 pub mod CHMAP23 {
1154 /// Offset (24 bits)
1155 pub const offset: u32 = 24;
1156 /// Mask (5 bits: 0b11111 << 24)
1157 pub const mask: u32 = 0b11111 << offset;
1158 /// Read-only values (empty)
1159 pub mod R {}
1160 /// Write-only values (empty)
1161 pub mod W {}
1162 /// Read-write values (empty)
1163 pub mod RW {}
1164 }
1165}
1166
1167/// Hardware Configuration Register
1168pub mod HWCFGR5 {
1169
1170 /// Input channel mapping
1171 pub mod CHMAP19 {
1172 /// Offset (0 bits)
1173 pub const offset: u32 = 0;
1174 /// Mask (5 bits: 0b11111 << 0)
1175 pub const mask: u32 = 0b11111 << offset;
1176 /// Read-only values (empty)
1177 pub mod R {}
1178 /// Write-only values (empty)
1179 pub mod W {}
1180 /// Read-write values (empty)
1181 pub mod RW {}
1182 }
1183
1184 /// Input channel mapping
1185 pub mod CHMAP18 {
1186 /// Offset (8 bits)
1187 pub const offset: u32 = 8;
1188 /// Mask (5 bits: 0b11111 << 8)
1189 pub const mask: u32 = 0b11111 << offset;
1190 /// Read-only values (empty)
1191 pub mod R {}
1192 /// Write-only values (empty)
1193 pub mod W {}
1194 /// Read-write values (empty)
1195 pub mod RW {}
1196 }
1197
1198 /// Input channel mapping
1199 pub mod CHMAP17 {
1200 /// Offset (16 bits)
1201 pub const offset: u32 = 16;
1202 /// Mask (5 bits: 0b11111 << 16)
1203 pub const mask: u32 = 0b11111 << offset;
1204 /// Read-only values (empty)
1205 pub mod R {}
1206 /// Write-only values (empty)
1207 pub mod W {}
1208 /// Read-write values (empty)
1209 pub mod RW {}
1210 }
1211
1212 /// Input channel mapping
1213 pub mod CHMAP16 {
1214 /// Offset (24 bits)
1215 pub const offset: u32 = 24;
1216 /// Mask (5 bits: 0b11111 << 24)
1217 pub const mask: u32 = 0b11111 << offset;
1218 /// Read-only values (empty)
1219 pub mod R {}
1220 /// Write-only values (empty)
1221 pub mod W {}
1222 /// Read-write values (empty)
1223 pub mod RW {}
1224 }
1225}
1226
1227/// Hardware Configuration Register
1228pub mod HWCFGR4 {
1229
1230 /// Input channel mapping
1231 pub mod CHMAP15 {
1232 /// Offset (0 bits)
1233 pub const offset: u32 = 0;
1234 /// Mask (5 bits: 0b11111 << 0)
1235 pub const mask: u32 = 0b11111 << offset;
1236 /// Read-only values (empty)
1237 pub mod R {}
1238 /// Write-only values (empty)
1239 pub mod W {}
1240 /// Read-write values (empty)
1241 pub mod RW {}
1242 }
1243
1244 /// Input channel mapping
1245 pub mod CHMAP14 {
1246 /// Offset (8 bits)
1247 pub const offset: u32 = 8;
1248 /// Mask (5 bits: 0b11111 << 8)
1249 pub const mask: u32 = 0b11111 << offset;
1250 /// Read-only values (empty)
1251 pub mod R {}
1252 /// Write-only values (empty)
1253 pub mod W {}
1254 /// Read-write values (empty)
1255 pub mod RW {}
1256 }
1257
1258 /// Input channel mapping
1259 pub mod CHMAP13 {
1260 /// Offset (16 bits)
1261 pub const offset: u32 = 16;
1262 /// Mask (5 bits: 0b11111 << 16)
1263 pub const mask: u32 = 0b11111 << offset;
1264 /// Read-only values (empty)
1265 pub mod R {}
1266 /// Write-only values (empty)
1267 pub mod W {}
1268 /// Read-write values (empty)
1269 pub mod RW {}
1270 }
1271
1272 /// Input channel mapping
1273 pub mod CHMAP12 {
1274 /// Offset (24 bits)
1275 pub const offset: u32 = 24;
1276 /// Mask (5 bits: 0b11111 << 24)
1277 pub const mask: u32 = 0b11111 << offset;
1278 /// Read-only values (empty)
1279 pub mod R {}
1280 /// Write-only values (empty)
1281 pub mod W {}
1282 /// Read-write values (empty)
1283 pub mod RW {}
1284 }
1285}
1286
1287/// Hardware Configuration Register
1288pub mod HWCFGR3 {
1289
1290 /// Input channel mapping
1291 pub mod CHMAP11 {
1292 /// Offset (0 bits)
1293 pub const offset: u32 = 0;
1294 /// Mask (5 bits: 0b11111 << 0)
1295 pub const mask: u32 = 0b11111 << offset;
1296 /// Read-only values (empty)
1297 pub mod R {}
1298 /// Write-only values (empty)
1299 pub mod W {}
1300 /// Read-write values (empty)
1301 pub mod RW {}
1302 }
1303
1304 /// Input channel mapping
1305 pub mod CHMAP10 {
1306 /// Offset (8 bits)
1307 pub const offset: u32 = 8;
1308 /// Mask (5 bits: 0b11111 << 8)
1309 pub const mask: u32 = 0b11111 << offset;
1310 /// Read-only values (empty)
1311 pub mod R {}
1312 /// Write-only values (empty)
1313 pub mod W {}
1314 /// Read-write values (empty)
1315 pub mod RW {}
1316 }
1317
1318 /// Input channel mapping
1319 pub mod CHMAP9 {
1320 /// Offset (16 bits)
1321 pub const offset: u32 = 16;
1322 /// Mask (5 bits: 0b11111 << 16)
1323 pub const mask: u32 = 0b11111 << offset;
1324 /// Read-only values (empty)
1325 pub mod R {}
1326 /// Write-only values (empty)
1327 pub mod W {}
1328 /// Read-write values (empty)
1329 pub mod RW {}
1330 }
1331
1332 /// Input channel mapping
1333 pub mod CHMAP8 {
1334 /// Offset (24 bits)
1335 pub const offset: u32 = 24;
1336 /// Mask (5 bits: 0b11111 << 24)
1337 pub const mask: u32 = 0b11111 << offset;
1338 /// Read-only values (empty)
1339 pub mod R {}
1340 /// Write-only values (empty)
1341 pub mod W {}
1342 /// Read-write values (empty)
1343 pub mod RW {}
1344 }
1345}
1346
1347/// Hardware Configuration Register
1348pub mod HWCFGR2 {
1349
1350 /// Input channel mapping
1351 pub mod CHMAP7 {
1352 /// Offset (0 bits)
1353 pub const offset: u32 = 0;
1354 /// Mask (5 bits: 0b11111 << 0)
1355 pub const mask: u32 = 0b11111 << offset;
1356 /// Read-only values (empty)
1357 pub mod R {}
1358 /// Write-only values (empty)
1359 pub mod W {}
1360 /// Read-write values (empty)
1361 pub mod RW {}
1362 }
1363
1364 /// Input channel mapping
1365 pub mod CHMAP6 {
1366 /// Offset (8 bits)
1367 pub const offset: u32 = 8;
1368 /// Mask (5 bits: 0b11111 << 8)
1369 pub const mask: u32 = 0b11111 << offset;
1370 /// Read-only values (empty)
1371 pub mod R {}
1372 /// Write-only values (empty)
1373 pub mod W {}
1374 /// Read-write values (empty)
1375 pub mod RW {}
1376 }
1377
1378 /// Input channel mapping
1379 pub mod CHMAP5 {
1380 /// Offset (16 bits)
1381 pub const offset: u32 = 16;
1382 /// Mask (5 bits: 0b11111 << 16)
1383 pub const mask: u32 = 0b11111 << offset;
1384 /// Read-only values (empty)
1385 pub mod R {}
1386 /// Write-only values (empty)
1387 pub mod W {}
1388 /// Read-write values (empty)
1389 pub mod RW {}
1390 }
1391
1392 /// Input channel mapping
1393 pub mod CHMAP4 {
1394 /// Offset (24 bits)
1395 pub const offset: u32 = 24;
1396 /// Mask (5 bits: 0b11111 << 24)
1397 pub const mask: u32 = 0b11111 << offset;
1398 /// Read-only values (empty)
1399 pub mod R {}
1400 /// Write-only values (empty)
1401 pub mod W {}
1402 /// Read-write values (empty)
1403 pub mod RW {}
1404 }
1405}
1406
1407/// Hardware Configuration Register
1408pub mod HWCFGR1 {
1409
1410 /// Input channel mapping
1411 pub mod CHMAP3 {
1412 /// Offset (0 bits)
1413 pub const offset: u32 = 0;
1414 /// Mask (5 bits: 0b11111 << 0)
1415 pub const mask: u32 = 0b11111 << offset;
1416 /// Read-only values (empty)
1417 pub mod R {}
1418 /// Write-only values (empty)
1419 pub mod W {}
1420 /// Read-write values (empty)
1421 pub mod RW {}
1422 }
1423
1424 /// Input channel mapping
1425 pub mod CHMAP2 {
1426 /// Offset (8 bits)
1427 pub const offset: u32 = 8;
1428 /// Mask (5 bits: 0b11111 << 8)
1429 pub const mask: u32 = 0b11111 << offset;
1430 /// Read-only values (empty)
1431 pub mod R {}
1432 /// Write-only values (empty)
1433 pub mod W {}
1434 /// Read-write values (empty)
1435 pub mod RW {}
1436 }
1437
1438 /// Input channel mapping
1439 pub mod CHMAP1 {
1440 /// Offset (16 bits)
1441 pub const offset: u32 = 16;
1442 /// Mask (5 bits: 0b11111 << 16)
1443 pub const mask: u32 = 0b11111 << offset;
1444 /// Read-only values (empty)
1445 pub mod R {}
1446 /// Write-only values (empty)
1447 pub mod W {}
1448 /// Read-write values (empty)
1449 pub mod RW {}
1450 }
1451
1452 /// Input channel mapping
1453 pub mod CHMAP0 {
1454 /// Offset (24 bits)
1455 pub const offset: u32 = 24;
1456 /// Mask (5 bits: 0b11111 << 24)
1457 pub const mask: u32 = 0b11111 << offset;
1458 /// Read-only values (empty)
1459 pub mod R {}
1460 /// Write-only values (empty)
1461 pub mod W {}
1462 /// Read-write values (empty)
1463 pub mod RW {}
1464 }
1465}
1466
1467/// Hardware Configuration Register
1468pub mod HWCFGR0 {
1469
1470 /// NUM_CHAN_24
1471 pub mod NUM_CHAN_24 {
1472 /// Offset (0 bits)
1473 pub const offset: u32 = 0;
1474 /// Mask (4 bits: 0b1111 << 0)
1475 pub const mask: u32 = 0b1111 << offset;
1476 /// Read-only values (empty)
1477 pub mod R {}
1478 /// Write-only values (empty)
1479 pub mod W {}
1480 /// Read-write values (empty)
1481 pub mod RW {}
1482 }
1483
1484 /// Extra analog watchdog
1485 pub mod EXTRA_AWDS {
1486 /// Offset (4 bits)
1487 pub const offset: u32 = 4;
1488 /// Mask (4 bits: 0b1111 << 4)
1489 pub const mask: u32 = 0b1111 << offset;
1490 /// Read-only values (empty)
1491 pub mod R {}
1492 /// Write-only values (empty)
1493 pub mod W {}
1494 /// Read-write values (empty)
1495 pub mod RW {}
1496 }
1497
1498 /// Oversampling
1499 pub mod OVS {
1500 /// Offset (8 bits)
1501 pub const offset: u32 = 8;
1502 /// Mask (4 bits: 0b1111 << 8)
1503 pub const mask: u32 = 0b1111 << offset;
1504 /// Read-only values (empty)
1505 pub mod R {}
1506 /// Write-only values (empty)
1507 pub mod W {}
1508 /// Read-write values (empty)
1509 pub mod RW {}
1510 }
1511}
1512
1513/// EXTI IP Version register
1514pub mod VERR {
1515
1516 /// Minor Revision number
1517 pub mod MINREV {
1518 /// Offset (0 bits)
1519 pub const offset: u32 = 0;
1520 /// Mask (4 bits: 0b1111 << 0)
1521 pub const mask: u32 = 0b1111 << offset;
1522 /// Read-only values (empty)
1523 pub mod R {}
1524 /// Write-only values (empty)
1525 pub mod W {}
1526 /// Read-write values (empty)
1527 pub mod RW {}
1528 }
1529
1530 /// Major Revision number
1531 pub mod MAJREV {
1532 /// Offset (4 bits)
1533 pub const offset: u32 = 4;
1534 /// Mask (4 bits: 0b1111 << 4)
1535 pub const mask: u32 = 0b1111 << offset;
1536 /// Read-only values (empty)
1537 pub mod R {}
1538 /// Write-only values (empty)
1539 pub mod W {}
1540 /// Read-write values (empty)
1541 pub mod RW {}
1542 }
1543}
1544
1545/// EXTI Identification register
1546pub mod IPIDR {
1547
1548 /// IP Identification
1549 pub mod IPID {
1550 /// Offset (0 bits)
1551 pub const offset: u32 = 0;
1552 /// Mask (32 bits: 0xffffffff << 0)
1553 pub const mask: u32 = 0xffffffff << offset;
1554 /// Read-only values (empty)
1555 pub mod R {}
1556 /// Write-only values (empty)
1557 pub mod W {}
1558 /// Read-write values (empty)
1559 pub mod RW {}
1560 }
1561}
1562
1563/// EXTI Size ID register
1564pub mod SIDR {
1565
1566 /// Size Identification
1567 pub mod SID {
1568 /// Offset (0 bits)
1569 pub const offset: u32 = 0;
1570 /// Mask (32 bits: 0xffffffff << 0)
1571 pub const mask: u32 = 0xffffffff << offset;
1572 /// Read-only values (empty)
1573 pub mod R {}
1574 /// Write-only values (empty)
1575 pub mod W {}
1576 /// Read-write values (empty)
1577 pub mod RW {}
1578 }
1579}
1580#[repr(C)]
1581pub struct RegisterBlock {
1582 /// ADC interrupt and status register
1583 pub ISR: RWRegister<u32>,
1584
1585 /// ADC interrupt enable register
1586 pub IER: RWRegister<u32>,
1587
1588 /// ADC control register
1589 pub CR: RWRegister<u32>,
1590
1591 /// ADC configuration register 1
1592 pub CFGR1: RWRegister<u32>,
1593
1594 /// ADC configuration register 2
1595 pub CFGR2: RWRegister<u32>,
1596
1597 /// ADC sampling time register
1598 pub SMPR: RWRegister<u32>,
1599
1600 _reserved1: [u8; 8],
1601
1602 /// watchdog threshold register
1603 pub AWD1TR: RWRegister<u32>,
1604
1605 /// watchdog threshold register
1606 pub AWD2TR: RWRegister<u32>,
1607
1608 /// CHSELR and CHSELR_1
1609 /// CHSELR: channel selection register
1610 /// CHSELR_1: channel selection register CHSELRMOD = 1 in ADC_CFGR1
1611 pub CHSELR: RWRegister<u32>,
1612
1613 /// watchdog threshold register
1614 pub AWD3TR: RWRegister<u32>,
1615
1616 _reserved2: [u8; 16],
1617
1618 /// ADC group regular conversion data register
1619 pub DR: RORegister<u32>,
1620
1621 _reserved3: [u8; 92],
1622
1623 /// ADC analog watchdog 2 configuration register
1624 pub AWD2CR: RWRegister<u32>,
1625
1626 /// ADC analog watchdog 3 configuration register
1627 pub AWD3CR: RWRegister<u32>,
1628
1629 _reserved4: [u8; 12],
1630
1631 /// ADC calibration factors register
1632 pub CALFACT: RWRegister<u32>,
1633
1634 _reserved5: [u8; 592],
1635
1636 /// ADC common control register
1637 pub CCR: RWRegister<u32>,
1638
1639 _reserved6: [u8; 204],
1640
1641 /// Hardware Configuration Register
1642 pub HWCFGR6: RWRegister<u32>,
1643
1644 /// Hardware Configuration Register
1645 pub HWCFGR5: RWRegister<u32>,
1646
1647 /// Hardware Configuration Register
1648 pub HWCFGR4: RWRegister<u32>,
1649
1650 /// Hardware Configuration Register
1651 pub HWCFGR3: RWRegister<u32>,
1652
1653 /// Hardware Configuration Register
1654 pub HWCFGR2: RWRegister<u32>,
1655
1656 /// Hardware Configuration Register
1657 pub HWCFGR1: RWRegister<u32>,
1658
1659 /// Hardware Configuration Register
1660 pub HWCFGR0: RORegister<u32>,
1661
1662 /// EXTI IP Version register
1663 pub VERR: RORegister<u32>,
1664
1665 /// EXTI Identification register
1666 pub IPIDR: RORegister<u32>,
1667
1668 /// EXTI Size ID register
1669 pub SIDR: RORegister<u32>,
1670}
1671pub struct ResetValues {
1672 pub ISR: u32,
1673 pub IER: u32,
1674 pub CR: u32,
1675 pub CFGR1: u32,
1676 pub CFGR2: u32,
1677 pub SMPR: u32,
1678 pub AWD1TR: u32,
1679 pub AWD2TR: u32,
1680 pub CHSELR: u32,
1681 pub AWD3TR: u32,
1682 pub DR: u32,
1683 pub AWD2CR: u32,
1684 pub AWD3CR: u32,
1685 pub CALFACT: u32,
1686 pub CCR: u32,
1687 pub HWCFGR6: u32,
1688 pub HWCFGR5: u32,
1689 pub HWCFGR4: u32,
1690 pub HWCFGR3: u32,
1691 pub HWCFGR2: u32,
1692 pub HWCFGR1: u32,
1693 pub HWCFGR0: u32,
1694 pub VERR: u32,
1695 pub IPIDR: u32,
1696 pub SIDR: u32,
1697}
1698#[cfg(not(feature = "nosync"))]
1699pub struct Instance {
1700 pub(crate) addr: u32,
1701 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1702}
1703#[cfg(not(feature = "nosync"))]
1704impl ::core::ops::Deref for Instance {
1705 type Target = RegisterBlock;
1706 #[inline(always)]
1707 fn deref(&self) -> &RegisterBlock {
1708 unsafe { &*(self.addr as *const _) }
1709 }
1710}
1711#[cfg(feature = "rtic")]
1712unsafe impl Send for Instance {}
1713
1714/// Access functions for the ADC peripheral instance
1715pub mod ADC {
1716 use super::ResetValues;
1717
1718 #[cfg(not(feature = "nosync"))]
1719 use super::Instance;
1720
1721 #[cfg(not(feature = "nosync"))]
1722 const INSTANCE: Instance = Instance {
1723 addr: 0x40012400,
1724 _marker: ::core::marker::PhantomData,
1725 };
1726
1727 /// Reset values for each field in ADC
1728 pub const reset: ResetValues = ResetValues {
1729 ISR: 0x00000000,
1730 IER: 0x00000000,
1731 CR: 0x00000000,
1732 CFGR1: 0x00000000,
1733 CFGR2: 0x00000000,
1734 SMPR: 0x00000000,
1735 AWD1TR: 0x0FFF0000,
1736 AWD2TR: 0x0FFF0000,
1737 CHSELR: 0x00000000,
1738 AWD3TR: 0x0FFF0000,
1739 DR: 0x00000000,
1740 AWD2CR: 0x00000000,
1741 AWD3CR: 0x00000000,
1742 CALFACT: 0x00000000,
1743 CCR: 0x00000000,
1744 HWCFGR6: 0x1F1F1F1F,
1745 HWCFGR5: 0x1F080807,
1746 HWCFGR4: 0x070B0A09,
1747 HWCFGR3: 0x07060605,
1748 HWCFGR2: 0x05050404,
1749 HWCFGR1: 0x03020100,
1750 HWCFGR0: 0x00000110,
1751 VERR: 0x00000000,
1752 IPIDR: 0x00000000,
1753 SIDR: 0x00000000,
1754 };
1755
1756 #[cfg(not(feature = "nosync"))]
1757 #[allow(renamed_and_removed_lints)]
1758 #[allow(private_no_mangle_statics)]
1759 #[no_mangle]
1760 static mut ADC_TAKEN: bool = false;
1761
1762 /// Safe access to ADC
1763 ///
1764 /// This function returns `Some(Instance)` if this instance is not
1765 /// currently taken, and `None` if it is. This ensures that if you
1766 /// do get `Some(Instance)`, you are ensured unique access to
1767 /// the peripheral and there cannot be data races (unless other
1768 /// code uses `unsafe`, of course). You can then pass the
1769 /// `Instance` around to other functions as required. When you're
1770 /// done with it, you can call `release(instance)` to return it.
1771 ///
1772 /// `Instance` itself dereferences to a `RegisterBlock`, which
1773 /// provides access to the peripheral's registers.
1774 #[cfg(not(feature = "nosync"))]
1775 #[inline]
1776 pub fn take() -> Option<Instance> {
1777 external_cortex_m::interrupt::free(|_| unsafe {
1778 if ADC_TAKEN {
1779 None
1780 } else {
1781 ADC_TAKEN = true;
1782 Some(INSTANCE)
1783 }
1784 })
1785 }
1786
1787 /// Release exclusive access to ADC
1788 ///
1789 /// This function allows you to return an `Instance` so that it
1790 /// is available to `take()` again. This function will panic if
1791 /// you return a different `Instance` or if this instance is not
1792 /// already taken.
1793 #[cfg(not(feature = "nosync"))]
1794 #[inline]
1795 pub fn release(inst: Instance) {
1796 external_cortex_m::interrupt::free(|_| unsafe {
1797 if ADC_TAKEN && inst.addr == INSTANCE.addr {
1798 ADC_TAKEN = false;
1799 } else {
1800 panic!("Released a peripheral which was not taken");
1801 }
1802 });
1803 }
1804
1805 /// Unsafely steal ADC
1806 ///
1807 /// This function is similar to take() but forcibly takes the
1808 /// Instance, marking it as taken irregardless of its previous
1809 /// state.
1810 #[cfg(not(feature = "nosync"))]
1811 #[inline]
1812 pub unsafe fn steal() -> Instance {
1813 ADC_TAKEN = true;
1814 INSTANCE
1815 }
1816}
1817
1818/// Raw pointer to ADC
1819///
1820/// Dereferencing this is unsafe because you are not ensured unique
1821/// access to the peripheral, so you may encounter data races with
1822/// other users of this peripheral. It is up to you to ensure you
1823/// will not cause data races.
1824///
1825/// This constant is provided for ease of use in unsafe code: you can
1826/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
1827pub const ADC: *const RegisterBlock = 0x40012400 as *const _;